JP2010219440A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply optimal stress to each of an N-type transistor and a P-type transistor, in a semiconductor device including an N-type MIS-FET and a P-type MIS-FET. <P>SOLUTION: In first insulation regions 101 being element isolation regions, second insulation regions 107 for providing tensile stress to the circumference and third insulation regions 108 for providing compressive stress to the circumference are formed. The second insulation regions 107 and the third insulation regions 108 are arranged for the N-type MIS-FET 50 to respectively provide tensile stress to the circumference of a first active region 103 in directions vertical to and parallel to a moving direction of electrons, and arranged for the P-type MIS-FET 60 to provide compressive stress to the circumference of a second active region 104 in a direction parallel to a moving direction of holes and provide tensile stress thereto in the direction vertical to the moving direction of the holes. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that applies stress to a channel region of a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.

  In recent years, with the integration of semiconductor integrated circuit devices, an STI (Shallow Trench Isolation) technique is widely used as an element isolation technique.

  However, with the miniaturization of elements, the stress exerted by the STI region on the element region has become a problem. That is, the STI region is usually formed by embedding a silicon oxide film by a chemical vapor deposition (CVD) method, and the silicon oxide film formed by the CVD method is generally volume-expandable. To give compressive stress. According to recent research, in N-type MIS-FET (MIS-type Field Effect Transistor), when compressive stress is applied in a direction perpendicular to and parallel to the direction of movement of electrons as carriers, the movement of electrons In a P-type MIS-FET, when compressive stress is applied in a direction perpendicular to the direction of movement of holes that are carriers, the mobility of holes that are carriers decreases. In some cases, it is reported that the performance of the MIS-FET is deteriorated. For P-type MIS-FETs, it has also been reported that the hole mobility improves when compressive stress is applied in a direction parallel to the hole movement direction.

  Therefore, in the CMIS (Complementary MIS) type semiconductor integrated circuit, the arrangement density of the dummy active region for ensuring the flatness of the surface at the time of processing by the chemical mechanical polishing (CMP) method is defined as N-type MIS-FET. The compressive stress applied to the N-type MIS-FET and the P-type MIS-FET is changed by making the region different from that of the P-type MIS-FET region, thereby improving the performance of the N-type and P-type MIS-FETs. Techniques for improving both have been proposed.

  Hereinafter, a method for changing the compressive stress applied to the N-type MIS-FET and the P-type MIS-FET shown in Patent Document 1 will be described with reference to FIG.

  As shown in FIG. 8, the arrangement density of the dummy active regions 11 made of silicon formed in the P well 3 constituting the N-type MIS-FET is formed in the N well 4 constituting the P-type MIS-FET. It is lower than the arrangement density of the dummy active regions 12. As a result, the stress applied to the P-type active region 5 in the P-well 3 is smaller than that in the N-type active region 6 in the N-well 4, so that the decrease in drive current of the N-type MIS-FET can be reduced. it can.

On the other hand, the arrangement density of the dummy active regions 12 made of silicon formed in the N well 4 constituting the P-type MIS-FET is relatively high. Thereby, the stress applied to the N-type active region 6 in the N-well 4 is relatively large, and the drive current of the P-type MIS-FET can be increased. Note that the magnitude of the stress is such that the total length dimension of the boundary line 22La in the P well 3 of the trench isolation insulating film 22 and the total length dimension of the boundary line 22Lb in the N well 4 of the trench isolation insulating film 22 It is described that the compressive stress of the P-type MIS-FET is larger than the compressive stress of the N-type MIS-FET because the total length is longer than the total length of the boundary line 22La.
JP 2004-55824 A

  However, the conventional semiconductor device has the following problems.

  That is, the conventional method in which the arrangement density of the dummy active regions is different in each peripheral region of the N-type MIS-FET and the P-type MIS-FET can reduce the magnitude of the compressive stress given by the STI. However, a tensile stress cannot be positively applied to the channel region in order to improve the performance of the N-type MIS-FET.

  In addition, since the stress application direction is isotropic within the upper surface of the semiconductor substrate, the effect of improving the performance of the P-type MIS-FET is limited.

  Also, the size, shape, and placement location of the dummy active region cannot be placed at any position because of the need to ensure flatness during CMP processing.

  In view of the above, the present invention enables an optimum stress to be independently applied to an N-type transistor and a P-type transistor in a semiconductor device including an N-type MIS-FET and a P-type MIS-FET. With the goal.

  In order to achieve the above object, the present invention provides an N-type semiconductor device by selectively disposing a region made of a member that applies tensile stress to the periphery and a member that applies compressive stress to the periphery in the element isolation region. A configuration in which optimum stress is applied to each of the transistor and the P-type transistor.

  Specifically, a semiconductor device according to the present invention is formed in a first active region and a first active region formed in a semiconductor region and insulated from each other by an element isolation region. A first conductive type element including a channel region serving as a carrier; and a second conductive type element formed in the second active region and including a channel region including a hole as a carrier. A first region having a property, and a first region formed around the first active region and the second active region in the first region with a first region interposed therebetween, and a member that applies tensile stress to the periphery. 2 region and a third region made of a member that applies compressive stress to the surroundings, and the second region and the third region are the first active region with respect to the first conductivity type element. Around the direction perpendicular to the direction of electron movement And a compressive stress in the direction parallel to the direction of movement of holes around the second active region for the second conductivity type element. On the other hand, they are arranged so as to give a tensile stress in a direction perpendicular to the direction of movement of holes.

  According to the semiconductor device of the present invention, the element isolation region includes the first active region and the first active region around the first active region and the second active region in the first region. A second region formed of a member that applies a tensile stress to the periphery, and a third region formed of a member that applies a compressive stress to the periphery, each formed between the second active region and the first region. It is composed of Further, the second region and the third region give a tensile stress to the periphery of the first active region with respect to the first conductivity type element in a direction perpendicular to and parallel to the electron movement direction, respectively. For the second conductivity type element, a compressive stress is applied to the periphery of the second active region in a direction parallel to the hole movement direction, while being perpendicular to the hole movement direction. It is arranged to give a tensile stress in the direction. For this reason, in the first conductivity type element (for example, N-type MIS-FET), the second region is arranged around the first active region, and thus the direction perpendicular to the electron moving direction and A tensile stress is applied to the channel region in a parallel direction. Further, in the second conductivity type element (for example, P-type MIS-FET), the second region is arranged in a direction perpendicular to the hole moving direction, and the third region is parallel to the hole moving direction. By arranging them in such a direction, tensile stress is applied in the direction perpendicular to the direction of hole movement, and compressive stress is applied to the channel region in the parallel direction. For this reason, since the optimal stress can be applied simultaneously and independently to both the first conductivity type element and the second conductivity type element, the performance of both elements can be improved.

  In the semiconductor device of the present invention, the second region has a direction perpendicular to and parallel to the electron movement direction around the first active region, and a hole movement direction in the second active region. The third region may be formed in a direction parallel to the hole moving direction in the second active region.

  In the semiconductor device of the present invention, an ozone TEOS (tetra-ethyl-ortho-silicate) film, a silicon nitride film, or a porous silicon oxide film can be used for the second region.

  In the semiconductor device of the present invention, a high-density plasma TEOS (tetra-ethyl-ortho-silicate) film or a silicon-rich oxide film can be used for the third region. Here, the silicon-rich oxide film refers to a film made of silicon oxide in which the composition ratio of silicon (Si) is higher than the stoichiometric ratio.

  In the semiconductor device of the present invention, at least one of the second region and the third region may be divided into a plurality.

  In the semiconductor device of the present invention, the planar dimensions of the second region and the third region may be not less than 100 nm and not more than 10 μm.

  In the semiconductor device of the present invention, the first conductivity type element and the second conductivity type element may constitute an inverter circuit by being electrically connected.

  In the method for manufacturing a semiconductor device according to the present invention, a first active region surrounded by an element isolation region is formed by selectively forming an insulating element isolation region in a first region above the semiconductor region. Forming a region and a second active region, respectively, and applying a tensile stress to the periphery of the first region with a space around at least one of the first active region and the second active region A step (b) of selectively forming a second region made of a member, and a compressive stress around the first active region and at least one of the second active regions in the first region with a space therebetween. A step (c) of selectively forming a third region made of a material providing a member, and a step (d) of forming a first conductivity type element including a channel region having electrons as carriers in the first active region. And holes in the second active region And (e) forming a second conductivity type element including a channel region serving as a carrier, wherein the second region and the third region are the first active region with respect to the first conductivity type element. Around the periphery of the second active region with respect to the second conductivity type element, the hole is moved so that tensile stress is applied to the periphery in a direction perpendicular to and parallel to the electron movement direction. The compressive stress is applied in the direction parallel to the direction, and the tensile stress is applied in the direction perpendicular to the hole moving direction.

  According to the method for manufacturing a semiconductor device of the present invention, the second region and the third region formed in the element isolation region are arranged around the first active region with respect to the first conductivity type element. A direction parallel to the direction of movement of holes around the second active region with respect to the second conductivity type element, so that tensile stress is applied in a direction perpendicular to the direction of movement and a direction parallel to the direction of movement. While compressive stress is applied, the tensile stress is applied in a direction perpendicular to the direction of hole movement. As described above, in the first conductivity type element (for example, N-type MIS-FET), the second region is arranged around the first active region, and thereby the direction perpendicular to the moving direction of electrons and A tensile stress is applied to the channel region in a parallel direction. In the second conductivity type element (for example, P-type MIS-FET), the second region is arranged in a direction perpendicular to the hole movement direction, and the third region is parallel to the hole movement direction. By arranging in such a direction, tensile stress is applied in the direction perpendicular to the direction of hole movement, and compressive stress is applied to the channel region in the parallel direction. For this reason, since the optimal stress can be applied simultaneously and independently to both the first conductivity type element and the second conductivity type element, the performance of both elements can be improved.

  In the method for manufacturing a semiconductor device of the present invention, the second region includes a direction around the first active region and in a direction perpendicular to and parallel to the direction of electron movement, and holes in the second active region. The third region may be formed in a direction parallel to the moving direction of holes in the second active region.

  In the method for manufacturing a semiconductor device of the present invention, an ozone TEOS (tetra-ethyl-ortho-silicate) film, a silicon nitride film, or a porous silicon oxide film can be used for the second region.

  In the semiconductor device manufacturing method of the present invention, a high-density plasma TEOS (tetra-ethyl-ortho-silicate) film or a silicon-rich oxide film can be used in the third region.

  According to the semiconductor device and the manufacturing method of the present invention, in a semiconductor device including an N-type MIS-FET and a P-type MIS-FET, optimum stress can be independently applied to the N-type transistor and the P-type transistor, respectively. Therefore, performance can be improved by applying stress to both the N-type MIS-FET and the P-type MIS-FET.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a planar configuration of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, for example, a semiconductor substrate 201 made of silicon (Si) includes a P-type first active region (P-well) 103 partitioned by a first insulating region 101 and an N-type second. An active region (N well) 104 is formed. A gate electrode 105 with a gate insulating film (not shown) interposed is formed on the first active region 103, and a gate insulating film (not shown) is formed on the second active region 104. ) Is formed.

  An N-type dopant, for example, phosphorus (P) ions or arsenic (As) ions are implanted into the first active region 103 as source and drain implantation, and the source 103a and drain whose surface is made N-type in the vicinity thereof. 103b is formed. In addition, in the second active region 104, a P-type dopant, for example, boron (B) ions, is implanted as a source and drain, and a source 104b and a drain 104a whose surface is in the P-type are formed. ing.

  By adopting such a configuration, the N-type MIS-FET 50 is formed in the first active region 103, and the P-type MIS-FET 60 is formed in the second active region 104.

Around the first active region 103 in the first insulating region 101, there are a plurality of second regions adjacent to the first active region 103 and facing each other in the gate width direction and the gate length direction of the gate electrode 105. An insulating region 107 is disposed. Here, the first insulating region 101 is formed by filling a trench with silicon oxide by a normal CVD method. Each of the second insulating regions 107 is formed by filling a trench with an insulating material that applies tensile stress to the periphery, for example, ozone TEOS (O ₃ -TEOS). Thereby, tensile stress can be applied to the channel region of the N-type MIS-FET 50 in a direction parallel to and a direction perpendicular to the traveling direction of electrons as carriers.

  On the other hand, a second insulating region 107 is disposed around the second active region 104 in the first insulating region 101 so as to be close to the second active region 104 and to face each other in the gate width direction. The third insulating regions 108 are arranged so as to face each other in the gate length direction. Here, the third insulating region 108 is formed by filling a trench with an insulating material that applies compressive stress to the periphery, for example, a high-density plasma TEOS (HDP-TEOS) film. As described above, the second insulating region 107 and the third insulating region 108 are arranged in the first insulating region 101 close to the respective active regions 103 and 104 and selectively disposed in the channel region of the P-type MIS-FET 60. , A compressive stress is applied in a direction parallel to a traveling direction of holes serving as carriers, and a tensile stress is applied in a direction perpendicular thereto.

  Therefore, the element isolation region according to the present embodiment includes the first insulating region 101, the second insulating region 107, and the third insulating region 108.

  FIG. 2 shows the carrier traveling direction and the stress application direction that can improve the performance of the MIS-FETs 50 and 60 for the N-type MIS-FET 50 and the P-type MIS-FET 60. The stress application direction shown in FIG. 2 corresponds to the content described in FIG.

  The planar dimensions of the second insulating region 107 and the third insulating region 108 are such that the long side is about 100 nm or more and 10 μm or less, and the planar shape may be, for example, a square. Furthermore, at least one of the second insulating region 107 and the third insulating region 108 may be divided into a plurality of portions. The distances (intervals) between the second insulating region 107 and the third insulating region 108 and the active regions 103 and 104 are in the range of about 10 nm to about 10 μm, respectively.

  Here, as shown in FIG. 1, an N-type MIS-FET 50 and a P-type MIS-FET 60 are disposed adjacent to each other on a semiconductor substrate 201, and a gate electrode 105 of the N-type MIS-FET 50 and a gate of the P-type MIS-FET 60. The electrodes 106 are connected to each other to serve as signal input terminals. Further, the source 104b of the second active region 104 and a VDD terminal (not shown) are connected, the source 103a of the first active region 103 is grounded, and the drain 103b of the first active region 103 is connected to the second terminal 103b. By connecting the drain 104a of the active region 104 as an output terminal, a basic inverter circuit can be configured.

  As described above, according to the first embodiment, the stress in the optimum direction can be independently applied to each of the N-type MIS-FET 50 and the P-type MIS-FET 60. That is, in the N-type MIS-FET 50, the second insulating region that applies a tensile stress to the periphery of the first active region 103 so as to face each other in a direction parallel to and a direction perpendicular to the direction in which electrons flow. 107 is formed in the first insulating region 101. In the P-type MIS-FET 60, the second insulating region 107 that applies tensile stress to the periphery in the vicinity of the second active region 104 and in the direction perpendicular to the direction in which holes flow is provided in the first insulating region 101. Furthermore, a third insulating region 108 for applying compressive stress to the periphery in the vicinity of the second active region 104 and in a direction parallel to the direction in which holes flow is formed in the first insulating region 101. Yes. Thereby, the performance of each of the N-type MIS-FET 50 and the P-type MIS-FET 60 can be improved simultaneously and independently, so that an excellent semiconductor device can be realized.

  Further, since the stress applied to each MIS-FET 50, 60 can be controlled in a wide range depending on the size and position of the second insulating region 107 and the third insulating region 108, it is optimal for the individual MIS-FET 50, 60. Stress can be applied. For example, in the case of a MIS-FET having a sufficiently large channel width, it is not necessary to apply stress because the on-current is sufficiently large. As a result, the semiconductor device can be miniaturized by omitting the second insulating region 107 and the third insulating region 108 arranged around the periphery. Furthermore, it is possible to avoid the occurrence of crystal defects in the semiconductor substrate 201 made of silicon at the end of the element isolation region made of STI as a side effect of applying stress to the active regions 103 and 104.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  3 to 6 show cross-sectional structures in the order of steps of the semiconductor device manufacturing method according to the first embodiment of the present invention. 3 to 6 correspond to a cross section taken along line III-III in FIG.

  First, as shown in FIG. 3, a trench is selectively formed in an element isolation formation region on an upper part of a semiconductor substrate 201 made of silicon by a lithography method and an etching method. Thereafter, the trench is formed by CVD so as to fill the silicon oxide film. Subsequently, by removing the silicon oxide film deposited on the main surface of the semiconductor substrate 201 by a chemical mechanical polishing (CMP) method or an etching back method, the silicon oxide partitioning each active region on the upper portion of the semiconductor substrate 201 A first insulating region 101 made of is formed. Here, the depth of the first insulating region 101 formed in the semiconductor substrate 201 is, for example, about 300 nm. Thereafter, a P-type dopant, for example, boron (B) ions are selectively ion-implanted into the active region of the semiconductor substrate 201 by ion implantation, so that the active region becomes the P-type first active region 103. . Further, by selectively implanting an N-type dopant, for example, arsenic (As) ions, into the active region adjacent to the first active region 103 in the semiconductor substrate 201 by an ion implantation method, the active region is converted into an N-type. The second active region 104 of FIG. Note that the order of forming the first active region 103 and the second active region 104 is not particularly limited.

Next, as shown in FIG. 4, the first insulating region 101 is surrounded by the lithography method and the etching method around the first active region 103 at positions spaced from the first active region 103 and facing each other. A trench having a depth of about 200 nm is formed. At the same time, in the first insulating region 101, the region intersecting the gate electrode formed on the second active region 104 is spaced from the second active region 104 and has a depth of about 200 nm at a position facing each other. A trench is formed. Subsequently, an ozone TEOS (O ₃ -TEOS) film is formed so as to fill each trench on the entire surface of the semiconductor substrate 201 by a CVD method using TEOS as a silicon source and ozone (O ₃ ) as an oxygen source. accumulate. After that, the second insulating region 107 is formed by removing the ozone TEOS film on the main surface of the semiconductor substrate 201 and the first insulating region 101 by CMP method or etching back method.

  Since the second insulating region 107 is filled with the ozone TEOS film, a tensile stress is applied to the periphery. The depth of the second insulating region 107 may be any depth that can apply stress to the surface portions of the first active region 103 and the second active region 104, and is set to about 200 nm in this embodiment. However, as long as the second insulating region 107 is formed of an insulating material, it may be formed deeper than the first insulating region 101. Further, the second insulating region 107 formed in the vicinity of the second active region 104 does not appear in FIG.

Next, as shown in FIG. 5, the first insulating region 101 is spaced from the second active region 104 in a region located in parallel with the gate electrode formed on the second active region 104 and is mutually connected. A trench having a depth of about 200 nm is formed at the opposing position. Subsequently, a high density plasma TEOS (HDP−) is formed so as to fill each trench on the entire surface of the semiconductor substrate 201 by high density plasma CVD using TEOS as the silicon source and oxygen (O ₂ ) as the oxygen source. A TEOS) film is deposited. Thereafter, the HDP-TEOS film on the main surface of the semiconductor substrate 201, the first insulating region 101, and the second insulating region 107 is removed by a CMP method or an etching back method, whereby the third insulating region 108 is formed.

  Since the third insulating region 108 is filled with the HDP-TEOS film, a compressive stress is applied to the periphery. Note that the depth of the third insulating region 108 may be any depth that can apply stress to the surface portion of the second active region 104 as in the case of the second insulating film 107. In this embodiment, the depth is 200 nm. However, as long as the third insulating region 108 is formed of an insulating material, it may be formed deeper than the first insulating region 101.

  Next, as shown in FIG. 6, a gate insulating film 210 made of silicon oxide is formed on the first active region 103 and the second active region 104 by, for example, thermal oxidation. Thereafter, a polysilicon film having conductivity is deposited on the gate insulating film 210 by a CVD method. Subsequently, the polysilicon film and the gate insulating film 210 are patterned into a predetermined shape by lithography and etching, thereby forming the gate electrode 105 with the gate insulating film 210 interposed on the first active region 103. Then, the gate electrode 106 with the gate insulating film 210 interposed is formed on the second active region 104. Here, the polysilicon film may be subjected to ion implantation or the like for imparting conductivity after deposition instead of imparting conductivity during deposition. Further, in the step of imparting conductivity, the conductivity type of the gate electrode 105 constituting the N-type MIS-FET 50 may be N-type, and the conductivity type of the gate electrode 106 constituting the P-type MIS-FET 60 may be P-type. Good.

  After that, although not shown, a source 103a and a drain 103b are formed by selectively implanting N-type impurities into the first active region 103 using the gate electrode 105 as a mask. Further, by ion-implanting P-type impurities into the second active region 104 using the gate electrode 106 as a mask, the source 104b and the drain 104a are formed, and the semiconductor device shown in FIG. 1 is obtained.

  In the first embodiment, the ozone TEOS film is exemplified as a material filling the second insulating region 107, but the material is not limited to the ozone TEOS film. For example, any material that gives tensile stress to the surroundings, such as a silicon nitride film or a porous silicon oxide film, can be used in the same manner.

  Further, although the HDP-TEOS film is exemplified as a material filling the third insulating region 108, the material is not limited to the HDP-TEOS film. For example, any material that gives compressive stress to the surroundings, such as a silicon-rich oxide film, can be used similarly.

  Further, as is clear from this embodiment, the second insulating region 107 and the third insulating region 108 are surrounded by the first insulating region 101, so that the forming material is not limited to the insulating property. A conductive material such as silicon (Si) or germanium (Ge), or a compound thereof can be used.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 shows a planar configuration of a semiconductor device according to the second embodiment of the present invention. In FIG. 7, the same components as those in FIG.

  As shown in FIG. 7, the feature of the second embodiment is that the arrangement direction of the gate electrode 106 constituting the P-type MIS-FET 60 is rotated by 90 °, and the gate electrode 105 constituting the N-type MIS-FET 50 is rotated. The direction intersects the arrangement direction.

  By arranging the gate electrode 106 in such a manner, the second insulating region 107 that applies a tensile stress in a direction perpendicular to the direction of movement of holes in the channel region of the P-type MIS-FET 60 is an N-type. The MIS-FET 50 can be shared with the second insulating region 107 that applies a tensile stress. For this reason, the semiconductor device having the same effect as that of the first embodiment can be further miniaturized.

  Further, as shown in FIG. 7, when the N-type MIS-FET 50 and the P-type MIS-FET 60 are arranged adjacent to each other, an inverter circuit that is a basic circuit can be configured. That is, the gate electrode 105 of the N-type MIS-FET 50 and the gate electrode 106 of the P-type MIS-FET 60 are connected to each other to form a signal input terminal. Further, the source 104b of the second active region 104 and a VDD terminal (not shown) are connected, the source 103a of the first active region 103 is grounded, and the drain 103b of the first active region 103 is connected to the second terminal 103b. An output terminal may be connected to the drain 104a of the active region 104.

  In the first and second embodiments, the planar dimensions and depth dimensions of the second insulating region 107 and the third insulating region 108 are determined in advance, and then a material to be filled in each of the insulating regions 107 and 108 is selected. As a result, the magnitude of the stress can be adjusted.

  As long as the stress applied to the N-type MIS-FET 50 and the P-type MIS-FET 60 satisfies the relationship shown in FIG. 2, the arrangement positions of the second insulating region 107 and the third insulating region 108 are as shown in FIGS. It is not limited to the arrangement of. For example, as long as the stress satisfies the relationship shown in FIG. 2, the second insulating region 107 is arranged such that the third insulating region 108 is disposed outside the second insulating region 107 of the first active region 103 in the N-type MIS-FET 50. And the third insulating region 108 may be mixed.

  In the first and second embodiments, silicon is used for the semiconductor substrate 201. However, the present invention is not limited to silicon, and the present invention includes a semiconductor substrate having a semiconductor region made of silicon germanium (SiGe), and further gallium arsenide. The present invention can also be applied to a substrate made of (GaAs) or gallium nitride (GaN).

  The semiconductor device and the manufacturing method thereof according to the present invention can independently apply optimum stress to the N-type transistor and the P-type transistor in the semiconductor device including the N-type MIS-FET and the P-type MIS-FET, respectively. The performance can be improved by applying stress to both FETs, which is useful for semiconductor devices including MIS-FETs.

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is a schematic diagram explaining the stress applied to MIS-FET which is a semiconductor device which concerns on this invention. FIG. 6 is a cross-sectional view in order of the steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view in order of the steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view in order of the steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view in order of the steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. It is a top view which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the conventional semiconductor device.

50 N-type MIS-FET
60 P-type MIS-FET
101 first insulating region 103 first active region 103a source 103b drain 104 second active region 104a drain 104b source 105 gate electrode 106 gate electrode 107 second insulating region 108 third insulating region 201 semiconductor substrate 210 gate insulating film

Claims (11)

A first active region and a second active region formed in a semiconductor region and insulated from each other by an element isolation region;
A first conductivity type element including a channel region formed in the first active region and having electrons as carriers;
A second conductivity type element including a channel region formed in the second active region and having holes as carriers,
The element isolation region is
A first region having an insulating property and the first active region and the second active region in the first region are formed with the first region interposed therebetween, and a tensile stress is applied to the periphery. A second region composed of a member, and a third region composed of a member that applies compressive stress to the surroundings,
The second region and the third region apply tensile stress to the periphery of the first active region with respect to the first conductive type element in a direction perpendicular to and parallel to an electron moving direction, respectively. And a compressive stress is applied to the second conductive type element around the second active region in a direction parallel to the hole moving direction, while the hole moving direction. And a semiconductor device which is arranged so as to give a tensile stress in a direction perpendicular to the semiconductor device. The second region includes a direction around and parallel to the direction of movement of electrons around the first active region and a direction perpendicular to the direction of movement of holes in the second active region. Formed in the direction,
The semiconductor device according to claim 1, wherein the third region is formed in a direction parallel to a movement direction of holes in the second active region.   3. The semiconductor device according to claim 1, wherein the second region includes an ozone TEOS (tetra-ethyl-ortho-silicate) film, a silicon nitride film, or a porous silicon oxide film.   3. The semiconductor device according to claim 1, wherein the third region includes a high-density plasma TEOS (tetra-ethyl-ortho-silicate) film or a silicon-rich oxide film.   5. The semiconductor device according to claim 1, wherein at least one of the second region and the third region is divided into a plurality of portions.   6. The semiconductor device according to claim 1, wherein each of the planar dimensions of the second region and the third region is not less than 100 nm and not more than 10 μm.   The said 1st conductivity type element and the said 2nd conductivity type element comprise the inverter circuit by electrically connecting, The any one of Claims 1-6 characterized by the above-mentioned. Semiconductor device. By selectively forming an element isolation region having an insulating property in the first region above the semiconductor region, a first active region and a second active region surrounded by the element isolation region are formed, respectively. Step (a) to perform,
A step of selectively forming a second region made of a member that applies a tensile stress to the periphery of at least one of the first active region and the second active region in the first region. b) and
A step of selectively forming a third region made of a member that applies a compressive stress around the first active region and the second active region in the first region at an interval around at least one of the first active region and the second active region; c) and
Forming a first conductivity type element including a channel region in which electrons are carriers in the first active region (d);
Forming a second conductive type element including a channel region having holes as carriers in the second active region (e),
The second region and the third region give a tensile stress to the first conductive type element around the first active region in a direction perpendicular to and parallel to an electron movement direction, respectively. And compressive stress is applied in the direction parallel to the hole movement direction around the second active region with respect to the second conductive type element, while being perpendicular to the hole movement direction. A method of manufacturing a semiconductor device, wherein the semiconductor device is arranged so as to give a tensile stress in any direction. The second region includes a direction around and parallel to the direction of movement of electrons around the first active region and a direction perpendicular to the direction of movement of holes in the second active region. Forming with direction,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the third region is formed in a direction parallel to a movement direction of holes in the second active region.   10. The method of manufacturing a semiconductor device according to claim 8, wherein the second region is formed by an ozone TEOS (tetra-ethyl-ortho-silicate) film, a silicon nitride film, or a porous silicon oxide film. .   11. The semiconductor device according to claim 8, wherein the third region is formed of a high-density plasma TEOS (tetra-ethyl-ortho-silicate) film or a silicon-rich oxide film. Production method.

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