KR100717503B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention improves the performance of a semiconductor device, and is formed on a semiconductor substrate having an NMOS region and a PMOS region formed thereon, a buffer layer formed thereon, a first epilayer, and a first epilayer in an NMOS region of the semiconductor substrate. A second epi layer, a gate oxide film formed on the first epi layer in the NMOS region of the semiconductor substrate, and a first epi layer in the PMOS region of the semiconductor substrate, and a gate electrode formed on the gate oxide film. . Accordingly, by making the channel region under the gate electrode into the tensile silicon with a small gap between the silicon atoms, the mobility of the driving current of the semiconductor device can be increased by reducing the force of atoms that interfere with the movement of electrons flowing in the epi layer. .

Transistors, Junction Regions, Epitaxial

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2 to 7 are diagrams illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention in manufacturing steps.

The present invention relates to a semiconductor device and a method of manufacturing the same.

In general, a semiconductor device includes a transistor including a gate, a source, and a drain defined by a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) device isolation method.

Transistors of such semiconductor devices are classified into NMOS, PMOS, and CMOS according to channel formation.

N-channel metal oxide silicon (NMOS) forms n-channel, and p-channel metal oxide silicon (PMOS) forms p-channel. Complementary metal oxide silicon (CMOS) includes NMOS and PMOS, and forms n-channel and p-channel.

Next, a method for manufacturing a CMOS of a semiconductor device will be described.

First, a well is formed on a semiconductor substrate on which shallow trench isolation (STI) is formed, and a gate oxide film is formed. Here, the STI prevents malfunction between the elements by electrically isolating the elements formed on the semiconductor substrate.

At this time, the well is divided into p-well and n-well according to the type of ions implanted into the semiconductor substrate. The p-well is formed on the semiconductor substrate when the NMOS is formed, and the n-well is the semiconductor substrate when the PMOS is formed. To form. When ions are implanted to form one of the n-well and the p-well, the other well region covers and protects the photoresist.

Then, a poly silicon layer is deposited on the gate oxide film.

Subsequently, the gate oxide film and the polysilicon layer are photo-etched to form a gate electrode. At this time, the gate electrode is formed on the semiconductor substrate on which the STI is not formed.

Then, using the ion implantation device on the semiconductor substrate using the gate electrode as a mask, a high concentration of impurity ions are implanted, and annealing is performed to source and drain junctions to active regions of the semiconductor substrate exposed to both sides of the gate electrode. Form an area.

On the other hand, as the semiconductor device is highly integrated, the value of the driving current may decrease when the semiconductor device is driven by the existing driving voltage. As a result, deterioration may occur in the semiconductor device, thereby degrading performance.

Therefore, the technical problem of this invention is improving the performance of a semiconductor element.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, wherein the semiconductor substrate includes an NMOS region and a PMOS region, a buffer layer formed on the semiconductor substrate, a first epitaxial layer formed on the buffer layer, and an NMOS region. A second oxide layer formed on the first epitaxial layer, a gate oxide film formed on the second epitaxial layer in the NMOS region, and a first epitaxial layer in the PMOS region, and a gate formed on the gate oxide layer An electrode.

The buffer layer may include silicon oxide (SiO ₂ ), and the thickness of the buffer layer may be about 300 to about 3,000 μm.

The first epitaxial layer may include germanium (Ge), and the thickness of the first epitaxial layer may be 1,000 to 5,000 kPa.

The second epitaxial layer is made of tensile silicon, and the thickness of the second epitaxial layer may be 50 kPa to 1,000 kPa.

The semiconductor device may further include a sidewall formed on the side of the gate electrode, and a heavily doped region formed in the second epitaxial layer of the NMOS region and the first epitaxial layer of the PMOS region.

Arsenic (As) may be implanted into the heavily doped region of the NMOS region.

Boron B may be injected into the heavily doped region of the PMOS region.

Forming a buffer layer over a semiconductor substrate comprising an NMOS region and a PMOS region, forming a first epitaxial layer over the buffer layer, forming a second epitaxial layer over the first epitaxial layer in the NMOS region, the Forming a gate oxide layer on the exposed first epitaxial layer and the second epitaxial layer, and forming a gate electrode on the gate oxide layer.

The buffer layer may be made of silicon oxide (SiO ₂ ), and the buffer layer may be formed to a thickness of 300 to 3,000 μm.

The first epitaxial layer may include germanium (Ge), and the first epitaxial layer may be formed to a thickness of 1,000 to 5,000 Å.

The second epitaxial layer may be made of tensile silicon, and the second epitaxial layer may be formed to have a thickness of 50 kPa to 1,000 kPa.

Forming a sidewall on the side of the gate electrode, and implanting impurity ions into the second epitaxial layer of the NMOS region and the first epitaxial layer of the PMOS region to form a highly doped region. have.

As (arsenic) impurity ions may be implanted into the second epitaxial layer of the NMOS region.

The As impurity ions can be implanted with 5 ~ 50Kev energy.

Boron impurity ions may be implanted into the first epitaxial layer of the PMOS region.

The B impurity ions can be implanted with 1 ~ 50Kev energy.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a method of manufacturing a semiconductor device will be described in detail with reference to FIGS. 1 to 7.

1 is a diagram of a semiconductor device according to one embodiment of the present invention, and FIGS. 2 to 7 are diagrams illustrating manufacturing steps of a semiconductor device according to one embodiment of the present invention.

First, the structure of a semiconductor device will be described in detail with reference to FIG. 1.

As shown in Fig. 1, the CMOS of a semiconductor device includes an NMOS forming an n-channel and a PMOS forming a p-channel.

Here, in the NMOS, the buffer layer 2 is formed on the semiconductor substrate 1, and the device isolation film 6 spaced apart at predetermined intervals is formed on the buffer layer 2. The first epitaxial layer 3 is formed between the adjacent device isolation layers 6, and the second epitaxial layer 4 is formed on the first epitaxial layer 3. Here, high concentration junction regions 9a and 9b are formed in the second epitaxial layer 4. The gate oxide film 5 and the first gate electrode 7a are sequentially formed on the second epitaxial layer 4, and the sidewalls 8a are formed on the side surfaces of the gate oxide film 5 and the first gate electrode 7a. It is.

On the other hand, in the PMOS, the buffer layer 2 is formed on the semiconductor substrate 1, and the element isolation film 6 spaced apart at predetermined intervals is formed on the buffer layer 2. The first epitaxial layer 3 is formed between the adjacent device isolation layers 6, and the gate oxide film 5 and the second gate electrode 7b are sequentially formed on the first epitaxial layer 3. The sidewalls 8b are formed on the side surfaces of the gate oxide film 5 and the second gate electrode 7b. At this time, high concentration bonding regions 9b and 9c are formed in the first epitaxial layer 3.

Next, the manufacturing method of a semiconductor element is demonstrated in detail with reference to FIGS. 2-7. As shown in FIG. 2, the buffer layer 2 is formed on the semiconductor substrate 1. As shown in FIG. At this time, the buffer layer 2 is preferably silicon oxide (SiO ₂ ), and preferably made of a thickness of 300 to 3,000 Pa.

Subsequently, a first epitaxial layer 3 is formed on the buffer layer 2, and a second epitaxial layer 4 is formed thereon.

The first epitaxial layer 3 is formed by depositing gaseous semiconductor crystals and growing crystals along the crystal axis of the buffer layer 2 and contains germanium (Ge). The second epitaxial layer 4 is formed by depositing gaseous semiconductor crystals in the same manner as the first epitaxial layer 3 and growing the crystals along the crystal axis of the first epitaxial layer 3.

Here, the second epitaxial layer 4 is formed by the germanium (Ge) atoms included in the first epitaxial layer 3 in contact with the lower portion thereof, thereby increasing the spacing between the silicon atoms of the second epitaxial layer 4 to increase the tensile silicon ( strain silicon). As a result, the force of the atom that hinders the movement of the electrons flowing in the second epitaxial layer 4 may be reduced, thereby increasing the mobility of the driving current. Therefore, the performance of the semiconductor device which has become increasingly integrated in recent years can be improved.

It is preferable to form such a 1st epi layer 3 in thickness of 1,000-5,000 GPa, and it is preferable to form the 2nd epi layer 4 in thickness of 50-1,000 GPa.

Meanwhile, the above-described buffer layer 2 relieves the pressure between the semiconductor substrate 1 and the first epitaxial layer 2 having different lattice spacing, and the germanium (Ge) valence included in the first epitaxial layer 2 is reduced. Prevents diffusion into the semiconductor substrate 1

3, the photoresist film PR1 is formed on the NMOS region to remove the second epitaxial layer 4 present in the PMOS region.

4, the photoresist film PR1 is removed and a gate oxide film 5 is formed over the NMOS region and the PMOS region. At this time, the gate oxide film 5 is preferably formed to a thickness of 20 ~ 60Å.

Next, as shown in FIG. 5, the first and second epitaxial layers 3 and 4 are etched to form a trench t in the first epitaxial layer 3, and the inside of the trench t is undoped silicate. The device isolation layer 6 is formed by filling with an insulating material such as glass). At this time, the device isolation film 6 electrically isolates the devices formed on the semiconductor substrate 1 to prevent malfunction.

Subsequently, the first gate electrode 7a and the second gate electrode 7b are formed on the gate oxide film 5 of the NMOS region and the PMOS region, and the gate oxide film 5 is removed using the mask as a mask. Here, the first and second gate electrodes 7a and 7b are on the second epi layer 4 in the NMOS region and the first epi layer 3 in the PMOS region, respectively.

Meanwhile, as described above, the gate oxide film 5 and the second gate electrode 7b are sequentially disposed directly on the first epitaxial layer 3 of the PMOS region, so that holes flow in the first epitaxial layer 3. Their mobility may increase.

Next, as shown in FIG. 6, sidewalls 8a and 8b are formed on the side surfaces of the first and second gate electrodes 7a and 7b. Subsequently, the photoresist film PR2 is formed on the entire upper structure of the semiconductor substrate 1 in the PMOS region, and the impurity ions are implanted at a high concentration into the second epitaxial layer 4 exposed to the NMOS region. 9b). In this case, the impurity ions include As (asenic), and the implantation of the impurity ions proceeds with an energy of 5keV to 50keV capable of injecting 10 ¹⁴ to 50 ¹⁴ ions per 1 cm ² area.

Then, as shown in FIG. 7, the photoresist film PR2 is removed, and the photoresist film PR3 is formed over the entire upper structure of the semiconductor substrate 1 in the NMOS region. Thereafter, high concentration of impurity ions are implanted into the first epitaxial layer 3 exposed to the PMOS region to form high concentration junction regions 9c and 9d. In this case, the impurity ions include B (boron), and the implantation of the impurity ions proceeds with an energy of 1 keV to 50 keV capable of injecting 10 ¹⁴ to 50 ¹⁴ ions per 1 cm ² area.

1, the photoresist film PR3 is removed to complete the transistor of the semiconductor element.

According to the present invention, the channel region under the gate electrode is made of tensile silicon with a small gap between the silicon atoms, thereby reducing the force of atoms that interfere with the movement of electrons flowing in the epi layer, thereby increasing the mobility of the driving current of the semiconductor device. Can be.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (22)

A semiconductor substrate in which an NMOS region and a PMOS region are formed, A buffer layer formed on the semiconductor substrate, A first epitaxial layer formed on the buffer layer, A second epitaxial layer formed over the first epitaxial layer in the NMOS region, A gate oxide film formed over the second epitaxial layer in the NMOS region and the first epitaxial layer in the PMOS region, and Gate electrodes formed on the gate oxide layer Semiconductor device comprising a. In claim 1, The buffer layer includes a silicon oxide (SiO ₂ ). In claim 1, The semiconductor device has a thickness of 300 ~ 3,000 300. In claim 1, The first epitaxial layer includes germanium (Ge). In claim 1, The first epitaxial layer has a thickness of 1,000 ~ 5,000Å. In claim 1, The second epitaxial layer is a semiconductor device made of strain silicon. In claim 1, The second epitaxial layer has a thickness of 50 kPa to 1,000 kPa. In claim 1, A side wall formed on the side of the gate electrode, and A heavily doped region formed in the second epitaxial layer of the NMOS region and the first epitaxial layer of the PMOS region A semiconductor device further comprising. In claim 8, Arsenic (As) is implanted into the heavily doped region of the NMOS region. In claim 8, And boron (B) is injected into the heavily doped region of the PMOS region. Forming a buffer layer over the semiconductor substrate including the NMOS region and the PMOS region, Forming a first epitaxial layer on the buffer layer, Forming a second epitaxial layer on the first epitaxial layer in the NMOS region, Forming a gate oxide layer on the exposed first epitaxial layer and the second epitaxial layer, and Forming gate electrodes on the gate oxide layer Method for manufacturing a semiconductor device comprising a. In claim 11, The buffer layer is a method of manufacturing a semiconductor device made of silicon oxide (SiO ₂ ). In claim 11, The buffer layer is a manufacturing method of a semiconductor device to form a thickness of 300 ~ 3,000Å. In claim 11, The first epitaxial layer includes a germanium (Ge) manufacturing method of a semiconductor device. In claim 11, The first epitaxial layer is a semiconductor device manufacturing method to form a thickness of 1,000 ~ 5,000 ~. In claim 11, The second epitaxial layer is a method of manufacturing a semiconductor device made of tensile silicon. In claim 11, The second epitaxial layer is a semiconductor device manufacturing method to form a thickness of 50 kPa to 1,000 kPa. In claim 11, Forming a sidewall on the side of the gate electrode, and Implanting impurity ions into the second epitaxial layer of the NMOS region and the first epitaxial layer of the PMOS region to form a highly doped region Method of manufacturing a semiconductor device further comprising. The method of claim 18, A method for manufacturing a semiconductor device injecting As (arsenic) impurity ions into the second epitaxial layer of the NMOS region. The method of claim 19, The As impurity ions are implanted at 5 ~ 50Kev energy method of manufacturing a semiconductor device. The method of claim 18, A method for manufacturing a semiconductor device injecting B (boron) impurity ions into the first epitaxial layer of the PMOS region. The method of claim 21, The B impurity ions are implanted at a energy of 1 ~ 50Kev.

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