KR20040038379A - Smart power device built-in SiGe HBT and fabrication method of the same - Google Patents
Smart power device built-in SiGe HBT and fabrication method of the same Download PDFInfo
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- KR20040038379A KR20040038379A KR1020020067280A KR20020067280A KR20040038379A KR 20040038379 A KR20040038379 A KR 20040038379A KR 1020020067280 A KR1020020067280 A KR 1020020067280A KR 20020067280 A KR20020067280 A KR 20020067280A KR 20040038379 A KR20040038379 A KR 20040038379A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 44
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 11
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
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- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
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- 238000001312 dry etching Methods 0.000 description 3
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
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- 239000007943 implant Substances 0.000 description 2
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
Abstract
Description
본 발명은 전력집적회로 기술에 관한 것으로, 특히 이종접합바이폴라소자(Hetro junction Bipolar transistor; HBT)가 내장된 고속 지능형 전력소자(Smart power device)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power integrated circuit technology, and more particularly, to a high speed smart power device incorporating a heterojunction bipolar transistor (HBT).
최근에 정보통신 기술의 비약적인 발전에 따라 이와 관련된 부품소재 기술의 확보가 필히 요구되고 있다. 다기능화된 첨단 지능형 소자 및 집적회로 기술은 디지털 이동통신 기술 및 가전 제품을 비롯한 전자 산업, 고성능 컴퓨터 시스템, 자동차의 전자제어 시스템 등의 핵심 부품 기술로서 경제적 기술적 측면에서 매우 중요한 고부가 가치의 첨단 기술이다. 이러한 관점에서 볼 때 구동회로, 보호회로, 인터페이스회로 등을 온칩(On-chip)화한 지능형 소자 기술의 확보는 필수적이다.Recently, with the rapid development of information and communication technology, it is necessary to secure related parts and materials technology. Advanced multi-functional intelligent devices and integrated circuit technologies are key component technologies in the electronics industry, high-performance computer systems, automotive electronic control systems, including digital mobile communication technology and consumer electronics, and are high value-added technologies that are very important in economic and technical aspects. . From this point of view, it is essential to secure intelligent device technology in which a driving circuit, a protection circuit, and an interface circuit are on-chip.
도 1은 종래기술에 따른 온칩화된 지능형 전력소자의 수직 단면도이다.1 is a vertical cross-sectional view of an on-chip intelligent power device according to the prior art.
도 1에 도시된 바와 같이, 종래 지능형 전력소자는, V-pnp 바이폴라 소자, CMOS 소자, npn 바이폴라 소자, nLDMOS가 온칩화되어 있다.As shown in FIG. 1, in the conventional intelligent power device, a V-pnp bipolar device, a CMOS device, an npn bipolar device, and an nLDMOS are on-chip.
도 1의 지능형 전력소자는, 실리콘 에피 기술 및 접합격리 기술을 이용하여 주로 디지털 회로에서 적용되는 CMOS 소자, 아날로그 바이폴라 소자 및 전력 소자인 LDMOS(Lateral Double diffused MOS) 소자를 집적화한 Bipolar-CMOS-DMOS(BCD)소자이다.The intelligent power device of FIG. 1 is a bipolar-CMOS-DMOS (Integrated CMOS device, analog bipolar device, and LDMOS (Lateral Double diffused MOS) device mainly applied in digital circuits using silicon epi technology and junction isolation technology). BCD) device.
그러나, 종래기술은 일반적인 소자 격리 및 고내압 LDMOS 소자를 채택하고 있으며, 바이폴라 소자 역시 SOI 구조가 아닌 일반적인 SBL(Standard Buried layer) 기술을 적용하므로써 깊은 접합 깊이로 인한 넓은 면적을 수반하게 되는 단점을 갖는다. 또한, 종래기술은 서브마이크론급에서는 LDMOS의 고내압 특성을 만족시키기 어려우며, 고속 디지탈용 BiCMOS 소자에 적용될 수 있는 바이폴라 소자가 탑재되어 있지 않다.However, the prior art adopts a general device isolation and a high breakdown voltage LDMOS device, and the bipolar device also has a disadvantage that a large area due to a deep junction depth is applied by applying a general standard buried layer (SBL) technology instead of an SOI structure. . In addition, the conventional technology is difficult to satisfy the high breakdown voltage characteristics of the LDMOS in the sub-micron class, and bipolar devices that can be applied to high-speed digital BiCMOS devices are not mounted.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 서브마이크론급에서도 고내압, 초고속, 저전력 특성을 갖는 지능형 전력소자 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide an intelligent power device having a high breakdown voltage, ultra-high speed, and low power even in a sub-micron class and a manufacturing method thereof.
도 1은 종래기술에 따른 지능형 전력소자의 수직 단면도,1 is a vertical cross-sectional view of an intelligent power device according to the prior art,
도 2는 본 발명의 실시예에 따른 SiGe HBT가 내장된 지능형 전력소자의 수직 단면도,2 is a vertical cross-sectional view of an intelligent power device built-in SiGe HBT according to an embodiment of the present invention,
도 3a 내지 도 3i는 본 발명의 실시예에 따른 SiGe HBT가 내장된 지능형 전력소자의 제조 방법을 도시한 공정 단면도.3A to 3I are cross-sectional views illustrating a method of manufacturing an intelligent power device incorporating SiGe HBT according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : p형 기판 32 : 매몰 산화막31 p-type substrate 32 buried oxide film
33 : n형 에피층 34 : p웰33: n-type epi layer 34: p well
35 : 트렌치 38 : 다결정실리콘층35 trench 38 polycrystalline silicon layer
39a,39b,39c,39d : 필드산화막 40 : nLDMOS 소자의 개방형 드레인영역39a, 39b, 39c, 39d: field oxide film 40: open drain region of nLDMOS device
41 : 바이폴라소자의 콜렉터싱커 42 : 바이폴라소자의 베이스영역41: collector sinker of bipolar element 42: base area of bipolar element
43 : 바이폴라소자의 에미터터영역 44 : SiGe-HBT의 콜렉터영역43: emitter area of bipolar element 44: collector area of SiGe-HBT
47 : SiGe 베이스층 48 : 다결정실리콘층47: SiGe base layer 48: polycrystalline silicon layer
50 : 게이트산화막 51 : 게이트전극50: gate oxide film 51: gate electrode
상기 목적을 달성하기 위한 본 발명의 지능형 전력 소자는, 일정 지역에서 개방된 공간을 갖는 산소이온주입층이 두 반도체층 사이에 삽입된 기판, 상기 기판위에 형성된 실리콘게르마늄 이종접합 바이폴라 소자, 상기 기판위에 형성된 CMOS 소자, 상기 기판위에 형성된 바이폴라 소자, 및 상기 기판위에 형성된 LDMOS 소자를 포함함을 특징으로 하고, 상기 트렌치는 TEOS막과 다결정실리콘층이 매립된 것을 특징으로 하며, 상기 LDMOS 소자는, 소스영역, 드리프트층 및 상기 드리프트층내에 구비된 드레인영역을 갖고, 상기 드리프트층은 상기 산소이온주입층의 개방된 공간을 통해 상기 기판의 하부 반도체층까지 확산된 개방형 드리프트층인 것을 특징으로 한다.An intelligent power device of the present invention for achieving the above object is a substrate in which an oxygen ion implantation layer having an open space in a predetermined region is inserted between two semiconductor layers, a silicon germanium heterojunction bipolar device formed on the substrate, on the substrate And a CMOS device, a bipolar device formed on the substrate, and an LDMOS device formed on the substrate, wherein the trench is formed by embedding a TEOS film and a polysilicon layer, wherein the LDMOS device includes a source region. And a drift layer and a drain region provided in the drift layer, wherein the drift layer is an open drift layer diffused to the lower semiconductor layer of the substrate through the open space of the oxygen ion implantation layer.
그리고, 본 발명의 지능형 전력 소자의 제조 방법은 이종접합바이폴라소자, CMOS 소자, 바이폴라 소자 및 LDMOS 소자가 온칩화된 지능형 전력 소자의 제조 방법에 있어서, 일정 지역에서 개방된 공간을 갖는 매몰 산화막이 두 반도체층 사이에 삽입된 SOI 기판을 형성하는 단계, 상기 LDMOS의 소스영역과 상기 CMOS 소자의 nMOS 영역에 p웰을 형성하는 단계, 상기 기판을 선택적으로 식각하여 각 소자간 격리를 위한 트렌치와 각 소자의 활성영역을 정의하는 필드산화막을 형성하는 단계, 상기 LDMOS의 개방형 드레인과 상기 바이폴라소자의 콜렉터싱커를 동시에 형성하는 단계, 상기 바이폴라소자의 베이스영역을 형성하는 단계, 상기 바이폴라소자의 에미터영역과 상기 이종접합바이폴라소자의 콜렉터영역을 동시에 형성하는 단계, 상기 CMOS 소자의 pMOS 영역에 n웰을 형성하는 단계, 상기 n웰을 포함한 전면에 상기 이종접합바이폴라소자의 활성영역을 노출시키는 창을 갖는 산화막을 형성하는 단계, 상기 창을 통해 상기 이종접합바이폴라소자의 활성영역에 연결되는 실리콘게르마늄 베이스층을 형성하는 단계, 상기 CMOS 소자와 상기 LDMOS 소자의 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 상기 CMOS 소자와 상기 LDMOS 소자의 게이트전극을 형성함과 동시에 상기 실리콘게르마늄 베이스층에 연결되는 상기 이종접합바이폴라소자의 에미터를 형성하는 단계, 상기 CMOS 소자와 상기 LDMOS의 LDD 영역을 동시에 형성하는 단계, 상기 LDMOS와 상기 CMOS 소자의 소스/드레인영역과 상기 이종접합바이폴라소자의 콜렉터영역과 상기 바이폴라소자의 베이스와 콜렉터 영역을 각각 형성하는 단계를 포함함을 특징으로 한다.The intelligent power device manufacturing method of the present invention is a method of manufacturing an intelligent power device in which heterojunction bipolar devices, CMOS devices, bipolar devices, and LDMOS devices are on-chip. Forming a SOI substrate interposed between the semiconductor layers, forming a p well in the source region of the LDMOS and the nMOS region of the CMOS device, selectively etching the substrate to isolate trenches and isolation for each device Forming a field oxide film defining an active region of the bipolar element, simultaneously forming an open drain of the LDMOS and a collector sinker of the bipolar element, forming a base region of the bipolar element, and an emitter region of the bipolar element Simultaneously forming a collector region of the heterojunction bipolar device; n well in a pMOS region of the CMOS device Forming an oxide film having a window exposing an active region of the heterojunction bipolar device on a front surface of the n well, wherein the silicon germanium base layer is connected to an active region of the heterojunction bipolar device through the window; Forming a gate oxide film of the CMOS device and the LDMOS device; forming a gate electrode of the CMOS device and the LDMOS device on the gate oxide film and simultaneously connecting to the silicon germanium base layer; Forming an emitter of a junction bipolar device, simultaneously forming an LDD region of the CMOS device and the LDMOS, a source / drain region of the LDMOS and the CMOS device, a collector region of the heterojunction bipolar device, and the bipolar device Forming a base and a collector region of the respective .
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
후술할 본 발명은 통상의 SOI 바이폴라/LDMOS 기술을 한단계 수준향상시키고 실리콘게르마늄 이종접합바이폴라소자(SiGe Hetero-junction Bipolar Transistor; 이하 'SiGe HBT'라고 약칭함)를 고내압소자와 동시에 온칩화하므로써 서브마이크론급에서도 고내압/초고속/저전력 특성을 갖는 SiGe HBT 내장형 지능형 전력소자의 구조 및 공정 기술을 제안한다. 즉, SOI 기판을 이용하여 서브마이크론급 고내압 LD(Lateral Diffusion)-MOS/고내압 바이폴라 소자/고집적 CMOS 소자/고속 SiGe HBT를 온칩(On-chip)화하는 지능형 전력소자를 제안한다.The present invention, which will be described later, improves the conventional SOI bipolar / LDMOS technology by one level, and simultaneously converts a silicon germanium heterojunction bipolar device (hereinafter, referred to as SiGe Hetero-junction Bipolar Transistor; In the micron class, we propose the structure and process technology of SiGe HBT embedded intelligent power device with high breakdown voltage / ultra high speed / low power. In other words, the present invention proposes an intelligent power device that uses a SOI substrate to on-chip a submicron high breakdown voltage (LD) -MOS / high breakdown voltage bipolar device / highly integrated CMOS device / high speed SiGe HBT.
도 2는 본 발명의 실시예에 따른 지능형 전력소자의 수직 단면도이다.2 is a vertical cross-sectional view of an intelligent power device according to an embodiment of the present invention.
도 2에 도시된 바와 같이, SIMOX 기술에 의한 SOI 기판상에, SiGe HBT, CMOS 소자, 고내압 바이폴라 소자, nLDMOS 소자가 온칩화되어 있다.As shown in FIG. 2, SiGe HBTs, CMOS devices, high breakdown voltage bipolar devices, and nLDMOS devices are on-chip on an SOI substrate by SIMOX technology.
먼저 SOI 기판은, p형 기판(31), 매몰 산화막(Buried oxide, 32), n형 에피층(33)의 순서로 적층된 것으로, 특히 매몰 산화막(32)은 p형 기판(31)상에 얇은 에피층을 형성한 후 선택적 마스크 작업을 통하여 에피층에 산소를 이온주입하여 0.1㎛∼1.0㎛ 두께로 형성한 산소이온주입층이다.First, the SOI substrate is stacked in the order of the p-type substrate 31, the buried oxide film 32, and the n-type epi layer 33. In particular, the buried oxide film 32 is formed on the p-type substrate 31. Oxygen ion implantation layer formed 0.1 μm to 1.0 μm thick by ion implanting oxygen into the epi layer through the selective mask operation after forming a thin epi layer.
SiGe HBT는, SOI 기판의 n형 에피층(33)의 소정영역에 필드산화막(39b)이 형성되고, 필드산화막(39b)에 의해 정의된 활성영역중 일측내에 n형 콜렉터층(56f)이 형성되며, 산화막(46)에 의해 노출되는 타측 활성영역상에 형성된 SiGe층(47)과 산화막(46)상에서 필드산화막(39b)과 오버랩되는 다결정실리콘층(48)으로 이루어진 베이스층이 형성된다. 그리고, 베이스층의 SiGe층(47)과 에미터층(51)이 산화막(49)이 제공하는 창을 통해 연결되고 있다.In SiGe HBT, a field oxide film 39b is formed in a predetermined region of an n-type epi layer 33 of an SOI substrate, and an n-type collector layer 56f is formed in one side of an active region defined by the field oxide film 39b. The base layer is formed of a SiGe layer 47 formed on the other active region exposed by the oxide film 46 and a polysilicon layer 48 overlapping the field oxide film 39b on the oxide film 46. The SiGe layer 47 and the emitter layer 51 of the base layer are connected through the window provided by the oxide film 49.
CMOS 소자는, SOI 기판상에서 필드산화막(39c)에 의해 서로 분리된 nMOS 소자와 pMOS 소자로 이루어지는데, nMOS 소자는 SOI 기판의 n형 에피층(33)내에 형성된 p웰(34)과 p웰(34) 상의 게이트산화막(50)과 게이트산화막(50)상의 게이트전극(51)과 nLDD(54a) 구조의 n형 소스/드레인영역(56c/56d)을 갖고, pMOS 소자는 SOI 기판의 n형 에피층(33)내에 형성된 n웰(45)과 n웰(45) 상의 게이트산화막(50)과 게이트산화막(50)상의 게이트전극(51)과 pLDD(54b) 구조의 p형 소스/드레인영역(57b/57c)을 갖는다. 여기서, 각 게이트전극(51)은 그 양측벽에 스페이서(55)를 구비한다.The CMOS device is composed of an nMOS device and a pMOS device separated from each other by a field oxide film 39c on the SOI substrate, and the nMOS device includes p wells 34 and p wells formed in the n-type epi layer 33 of the SOI substrate. 34 has a gate oxide film 50 on the gate oxide film 50, a gate electrode 51 on the gate oxide film 50, and an n-type source / drain region 56c / 56d having an nLDD 54a structure, and the pMOS device has an n-type epi of an SOI substrate. P-type source / drain regions 57b having a structure of a gate oxide film 50 on the n well 45 and an n well 45 formed in the layer 33, a gate electrode 51 on the gate oxide film 50, and a pLDD 54b structure. / 57c). Here, each gate electrode 51 has spacers 55 on both side walls thereof.
고내압 npn 바이폴라 소자는, n형 에피층(33)내에서 필드산화막(39d)에 의해 서로 분리되는 저농도 베이스층(42)과 콜렉터 싱커(41), 콜렉터 싱커(41)내에 형성된 콜렉터층(57d), 저농도 베이스층(42)내에서 이온주입을 통해 서로 거리를 두고 형성된 고농도 베이스층(56e)과 에미터층(43), 전체 구조물 상부를 덮는 층간절연막(58)을 관통하여 콜렉터층(57d), 베이스층(56e), 에미터층(43)에 각각 연결된 접점(59)을 포함한다. 여기서, 콜렉터 싱커(41)는, n형 에피층(33)내에서 이온주입 및 확산을 통해 매몰산화막(32)에 연결되고 있다.The high breakdown voltage npn bipolar element is a collector layer 57d formed in the low concentration base layer 42 and the collector sinker 41 and the collector sinker 41 which are separated from each other by the field oxide film 39d in the n-type epi layer 33. ), The collector layer 57d penetrates the high concentration base layer 56e, the emitter layer 43, and the interlayer insulating film 58 covering the entire structure, formed at a distance from each other through ion implantation in the low concentration base layer 42. And a contact 59 connected to the base layer 56e and the emitter layer 43, respectively. Here, the collector sinker 41 is connected to the buried oxide film 32 through ion implantation and diffusion in the n-type epitaxial layer 33.
nLDMOS 소자는, 필드산화막(39e)과 활성영역으로 정의된 n형 에피층(33)에 걸쳐서 형성된 판구조의 게이트전극(51), 게이트전극(51) 아래의 게이트산화막(50), 게이트전극(51)과 게이트산화막(50)의 적층물 양측벽에 구비된 스페이서(55), 게이트전극(51)의 일측 n형 에피층(33)내에 구비된 nLDD(54a) 구조의 소스영역(56a), 필드산화막(39e)에 의해 분리된 일측 n형 에피층(33)내에 구비된 n형 드리프트층(40), n형 드리프트층(40)내에 구비된 n형 드레인영역(56d), 전체 구조물 상부를 덮는 층간절연막(58)을 관통하여 게이트전극(51), 소스영역(56a), 드레인영역(56d)에 각각 연결된 접점(59)을 포함한다. 여기서, n형 드리프트층(40)은 선택적으로 p형 기판(31)상에 형성된 매몰산화막(32)간 개방된 공간을 통하여 p형 기판(31)까지 그 깊이가 이르는 개방형 드리프트층 구조를 갖는다.The nLDMOS device includes a plate-shaped gate electrode 51 formed over a field oxide film 39e and an n-type epi layer 33 defined as an active region, a gate oxide film 50 under the gate electrode 51, and a gate electrode ( A spacer 55 provided on both sidewalls of the stack 51 of the gate oxide film 50 and a source region 56a of an nLDD 54a structure provided in one n-type epi layer 33 on the gate electrode 51; N-type drift layer 40 provided in one side n-type epi layer 33 separated by field oxide film 39e, n-type drain region 56d provided in n-type drift layer 40, and the upper part of the entire structure. The contact 59 is connected to the gate electrode 51, the source region 56a, and the drain region 56d through the interlayer insulating layer 58. Here, the n-type drift layer 40 has an open drift layer structure in which the depth reaches to the p-type substrate 31 through an open space between the buried oxide films 32 formed on the p-type substrate 31.
한편, SiGe HBT와 CMOS 소자, CMOS 소자와 고내압 바이폴라 소자, 고내압 바이폴라 소자와 nLDMOS 소자 사이는 LOCOS법에 의한 필드산화막 하부의 트렌치에 매립된 TEOS막과 다결정실리콘층에 의해 서로 격리되고 있다. 여기서, 트렌치의 측벽에 측벽산화막이 형성되고 있다.On the other hand, between the SiGe HBT, the CMOS element, the CMOS element, the high breakdown voltage bipolar element, the high breakdown voltage bipolar element, and the nLDMOS element are separated from each other by the TEOS film and the polycrystalline silicon layer embedded in the trench under the field oxide film by the LOCOS method. Here, a sidewall oxide film is formed on the sidewall of the trench.
전술한 바와 같이, 본 발명의 지능형 전력소자는 고내압 특성을 갖는 서브미크론급 nLDMOS 소자, 고내압/고전류 특성을 만족시키기 위한 바이폴라 소자, 고속디지털 회로용 CMOS 소자 및 초고속 논리회로 구현을 위한 SiGe HBT를 하나의 SOI 기판에 구현하고, LDMOS 소자에서 드리프트층을 개방형으로 형성하여 드레인전계를 효과적으로 분산시키므로써 100V이상의 고내압 특성을 구현하고, 1.5㎛ 급의 에피층을 이용하여 초고속/고내압 특성을 동시에 만족시키고 있고, 트렌치 격리기술을 이용하여 집적도를 향상시킨다. 또한, SiGe HBT에서 차단주파수 특성 개선을 위하여 활성영역에 산화막을 선택적으로 마스킹한 후 SiGe를 증착하였다.As described above, the intelligent power device of the present invention is a sub-micron class nLDMOS device having high breakdown voltage characteristics, a bipolar device for satisfying high breakdown voltage / high current characteristics, a CMOS device for high-speed digital circuits, and a SiGe HBT for ultrafast logic circuit implementation. Implemented on one SOI substrate and forming a drift layer in an LDMOS device to effectively disperse the drain electric field to realize high breakdown voltage characteristics of 100V or more, and simultaneously use ultrafast / high breakdown voltage characteristics by using an epitaxial layer of 1.5µm. Satisfies and improves the density by using trench isolation technology. In addition, in order to improve the blocking frequency characteristics in SiGe HBT, SiGe was deposited after selectively masking an oxide film in an active region.
도 3a 내지 도 3i는 본 발명의 실시예에 따른 지능형 전력소자의 제조 방법을 도시한 공정 단면도이다.3A to 3I are cross-sectional views illustrating a method of manufacturing an intelligent power device according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, p형 실리콘기판(31), 매몰 산화막(Buried oxide, 32)과 n형 에피층(33)의 순서로 적층된 SOI(Silicon On Insulator) 기판을 형성하는데, 먼저 p형 실리콘 기판(31)상에 1×1015∼1×1016cm-3의 도핑농도를 갖는 0.5㎛ 두께의 n형 에피층을 형성시킨 후 선택적 마스크 작업을 통하여 산소를 이온주입하여 약 0.1㎛∼1.0㎛ 두께의 선태적 매몰산화막(32)을 형성한다. 즉, SIMOX(Separation by Implantation of Oxygen) 기술을 이용하여 SOI 기판을 형성한다. 다음에, 1×1015∼1×1016cm-3의 도핑농도를 갖는 전체 0.5㎛∼2.0㎛ 두께의 n형 에피층(33)을 성장시키므로써, SOI 구조를 완성한다.As shown in FIG. 3A, a silicon on insulator (SOI) substrate stacked in the order of the p-type silicon substrate 31, the buried oxide layer 32, and the n-type epitaxial layer 33 is formed. 0.5 nm thick n-type epi layer having a doping concentration of 1 × 10 15 to 1 × 10 16 cm -3 is formed on the silicon substrate 31, and oxygen is ion implanted through selective masking to perform 0.1 nm implantation. A selective investment oxide film 32 having a thickness of ˜1.0 μm is formed. That is, an SOI substrate is formed by using a Separation by Implantation of Oxygen (SIMOX) technology. Next, the SOI structure is completed by growing the n-type epi layer 33 having a total thickness of 0.5 µm to 2.0 µm having a doping concentration of 1 × 10 15 to 1 × 10 16 cm -3 .
다음에, nLDMOS 및 nNMOS의 p형 웰(34) 형성을 위하여 마스크작업을 통해 n형 에피층(33)에 붕소를 1×1012∼1×1013cm-3의 도핑농도와 60KeV∼120KeV의 에너지로 이온주입한다.Next, in order to form the p-type wells 34 of nLDMOS and nNMOS, boron was implanted into the n-type epitaxial layer 33 through a masking operation with a doping concentration of 1 × 10 12 to 1 × 10 13 cm −3 and 60KeV to 120 KeV. Ion implantation with energy.
도 3b에 도시된 바와 같이, SiGe-HBT와 CMOS 소자, CMOS 소자와 바이폴라 소자, 바이폴라 소자와 nLDMOS 소자간을 격리시키는 트렌치(35)를 형성하며, 트렌치내에 측벽산화막(36), TEOS막(37) 및 다결정실리콘층(38)을 매립시킨다.As shown in FIG. 3B, a trench 35 is formed to isolate SiGe-HBT and CMOS devices, CMOS devices and bipolar devices, bipolar devices and nLDMOS devices, and sidewall oxide films 36 and TEOS films 37 are formed in the trenches. ) And the polysilicon layer 38 are embedded.
트렌치(35)의 매립 방법에 대해 설명하면, 먼저 500Å 두께의 제1 산화막, 2000Å 두께의 제1 질화막, 1㎛ 두께의 제2 산화막을 마스크층으로 사용하여 실리콘웨이퍼를 SOI기판의 매몰산화막(32)에 이를때까지 건식식각하여 수직프로파일의 트렌치(35)를 형성한 후, 습식산화를 실시하여 측벽산화막(36)을 형성한다. 이어서, 트렌치(35)에 4000Å 두께의 TEOS막(37)을 LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 형성하고, TEOS막(37)위에 다시 9000Å의 다결정실리콘층(38)을 형성하여 트렌치(35)를 매립시킨다.A method of filling the trench 35 will be described. First, a silicon wafer is used as an buried oxide film 32 of an SOI substrate using a 500 nm thick first oxide film, a 2000 nm thick first nitride film, and a 1 μm thick second oxide film as a mask layer. Dry etching until the trench is formed to form the trench 35 of the vertical profile, and then wet oxidation is performed to form the sidewall oxide layer 36. Subsequently, a 4000 mm thick TEOS film 37 is formed in the trench 35 by LPCVD (Low Pressure Chemical Vapor Deposition) method, and a 9000 mm polycrystalline silicon layer 38 is formed again on the TEOS film 37 to form a trench 35. Landfill).
다음으로, 트렌치(35) 부분을 제외한 다른 부분에 형성된 다결정실리콘층(38)을 제거하기 위하여 제1 질화막이 노출될 때까지 다결정실리콘층(38), TEOS막(37)과 제2 산화막(36)을 래핑(lapping) 방법으로 제거한다. 래핑에 의해 손상된 제1 질화막은 습식식각으로 제거하고 다시 LPCVD 방법으로 1200Å 두께의 제2 질화막을 적층한 후 활성영역을 마스크 작업한 다음, 건식식각법으로 제2 질화막을 식각한다.Next, the polysilicon layer 38, the TEOS film 37, and the second oxide film 36 until the first nitride film is exposed to remove the polysilicon layer 38 formed in other portions except the trench 35 portion. ) Is removed by lapping. The first nitride film damaged by the lapping is removed by wet etching, a second nitride film having a thickness of 1200 Å is laminated by LPCVD, and then the active region is masked, and the second nitride film is etched by dry etching.
다음으로, 식각처리된 제2 질화막을 마스크로 노출된 활성영역에 7500Å 두께의 필드산화막(39a, 39b, 39c, 39d, 39e)을 열산화 방법으로 성장시켜 소자 격리를 완료한 후, 제2 질화막을 제거한다.Subsequently, a 7500Å thick field oxide film 39a, 39b, 39c, 39d, 39e is grown by a thermal oxidation method in the active region exposed by using the etched second nitride film as a mask to complete device isolation, and then the second nitride film. Remove it.
이때, 필드산화막(39a, 39b, 39c, 39d, 39e)중에서 제1 필드산화막(39a)은 각 트렌치(35) 상부에 형성되고, 제2 필드산화막(39b)은 SiGe-HBT의 활성영역에 형성되며, 제3 필드산화막(39c)은 CMOS 소자의 nMOS 소자와 pMOS 소자 사이의 활성영역에 형성되고, 제4 필드산화막(39d)은 바이폴라 소자의 활성영역에 형성되며, 제5필드산화막(39e)은 nLDMOS 소자의 활성영역 상부에 형성된다.At this time, among the field oxide films 39a, 39b, 39c, 39d, and 39e, the first field oxide film 39a is formed on each trench 35, and the second field oxide film 39b is formed in the active region of SiGe-HBT. The third field oxide film 39c is formed in the active region between the nMOS device and the pMOS device of the CMOS device, and the fourth field oxide film 39d is formed in the active area of the bipolar device, and the fifth field oxide film 39e is formed. Is formed over the active region of the nLDMOS device.
이상에서 설명한 바와 같이, 질화막을 마스크로 이용하여 필드산화막을 형성하는 방법은 통상적으로 LOCOS(Local oxidation of silicon)법으로 알려져 있다.As described above, a method of forming a field oxide film using a nitride film as a mask is commonly known as a LOCOS (Local oxidation of silicon) method.
그 다음은, 마스크 작업을 통하여 nLDMOS 소자의 개방형 드레인영역(40)과 바이폴라소자의 콜렉터싱커(41)를 형성한다. 먼저 드레인영역(40)과 콜렉터싱커(41)는 직렬 저항 감소 특성을 위하여 인(Phosphorous; P)을 1×1014∼1×1016cm-3의 도핑농도와 40KeV∼120KeV의 에너지로 이온주입한 후 800℃∼1100℃에서 10분∼200분간 열처리하여 형성한다.Next, an open drain region 40 of the nLDMOS device and a collector sinker 41 of the bipolar device are formed through a mask operation. First, in the drain region 40 and the collector sinker 41, phosphorous (P) is implanted at a doping concentration of 1 × 10 14 to 1 × 10 16 cm -3 and an energy of 40 KeV to 120 KeV for the series resistance reduction characteristics. Then, it is formed by heat treatment at 800 ° C to 1100 ° C for 10 to 200 minutes.
도 3c에 도시된 바와 같이, 바이폴라소자의 베이스영역(42) 및 에미터영역(43)을 형성한다.As shown in FIG. 3C, the base region 42 and the emitter region 43 of the bipolar element are formed.
먼저, 베이스 영역(42)을 형성하기 위하여 마스크 작업을 통하여 붕소(Boron; B)를 1×1013∼1×1015cm-3의 도핑농도와 10KeV∼100KeV의 에너지로 이온주입한 후, 800℃∼1100℃에서 10분∼200분간 열처리한다. 다음에, 에미터 영역(43)의 마스크 작업을 통하여 비소(As)를 1×1015∼1×1016cm-3의 도핑농도와 50KeV∼150KeV의 에너지로 이온주입한 후, 800℃∼1100℃에서 10분∼200분간 열처리한다. 이때, SiGe-HBT의 콜렉터 영역(44)도 동시에 형성된다.First, in order to form the base region 42, boron (B) is implanted at a doping concentration of 1 × 10 13 to 1 × 10 15 cm −3 and an energy of 10 KeV to 100 KeV through a mask operation, and then 800 The heat treatment is performed at 10 ° C. to 1100 ° C. for 10 minutes to 200 minutes. Next, arsenic (As) is ion implanted at a doping concentration of 1 × 10 15 to 1 × 10 16 cm -3 and energy of 50 KeV to 150 KeV through a mask operation of the emitter region 43, and then 800 ° C. to 1100. Heat-treat at 10 degreeC-200 minute (s). At this time, the collector region 44 of SiGe-HBT is also formed at the same time.
도 3d에 도시된 바와 같이, nLDMOS와 nMOS의 문턱전압 조절, pMOS의 n 웰, SiGe-HBT의 SiGe 베이스 박막, 폴리실리콘 베이스 전극을 형성한다.As shown in FIG. 3D, threshold voltage regulation of nLDMOS and nMOS, n well of pMOS, SiGe base thin film of SiGe-HBT, and polysilicon base electrode are formed.
먼저 nLDMOS 및 nMOS의 문턱전압 조절(n-CH Vtimplant)을 위하여 마스크 작업한 후 붕소(B)를 1×1011∼1×1013cm-3의 도핑농도와 10KeV∼100KeV의 에너지로 이온주입한다. 그리고 pMOS의 n형 웰(45) 및 문턱전압 조절(n well and p-CH Vtimplant)을 위하여 마스크 작업한 후 각각 인(P)과 붕소(B)를 1×1012∼1×1014cm-3의 도핑농도와 100KeV∼1000KeV의 에너지로 주입하고, 1×1011∼1×1013cm-3의 도핑농도와 10KeV∼100KeV의 에너지로 주입한다. 이때, 이온주입된 인(P)은 게이트산화막 형성 과정 등의 후속 열공정에 의하여 확산되어 n형 웰(45)을 형성하게 된다.First, masking is performed for nLDMOS and n-CH V t implant control, and then boron (B) is ionized at a doping concentration of 1 × 10 11 to 1 × 10 13 cm -3 and energy of 10 KeV to 100 KeV. Inject. And after masking for n type well 45 and threshold voltage control (n well and p-CH V t implant) of pMOS, phosphorus (P) and boron (B) are respectively 1 × 10 12 to 1 × 10 14 A doping concentration of cm −3 and an energy of 100 KeV to 1000 KeV are injected, and a doping concentration of 1 × 10 11 to 1 × 10 13 cm −3 and an energy of 10 KeV to 100 KeV. At this time, the ion-implanted phosphorus (P) is diffused by a subsequent thermal process such as a gate oxide film forming process to form an n-type well (45).
다음, SiGe 베이스 박막 및 베이스 전극 형성을 위해 1000Å∼5000Å의 산화막(46)을 성장시킨 후 SiGe-HBT의 베이스 영역을 패터닝한 다음, 1×1018∼1×1020cm-3의 붕소(B)가 인시튜 도핑된 20∼100nm 두께의 SiGe 박막(47)을 성장시킨다. 이때, 10nm 정도의 두께는 순수한 실리콘 박막으로 성장시킨다. 여기서, 필드산화막(39b) 상부에는 다결정실리콘층(48)이 성장되어 이를 베이스 전극으로 사용하고, 활성영역상에는 SiGe 박막(47)이 성장된다. 다음, SiGe HBT 이외의 나머지 부분에 형성된 SiGe 박막을 제거한다.Next, 1000 G to 5000 산화 oxide film 46 was grown to form the SiGe base thin film and the base electrode, and then the base region of the SiGe-HBT was patterned, and then boron (B × B) of 1 × 10 18 to 1 × 10 20 cm -3 . Grow an SiGe thin film 47 having an in-situ doped thickness of 20 to 100 nm. At this time, the thickness of about 10nm is grown into a pure silicon thin film. Here, the polysilicon layer 48 is grown on the field oxide film 39b and used as a base electrode, and the SiGe thin film 47 is grown on the active region. Next, the SiGe thin film formed on the remaining portions other than SiGe HBT is removed.
도 3e에 도시된 바와 같이, SiGe-HBT의 에미터 전극 형성을 위한 산화막(49) 성장 과정과 게이트산화막(50) 형성 과정을 진행한다.As shown in FIG. 3E, an oxide film 49 growth process and a gate oxide film 50 formation process for forming an emitter electrode of SiGe-HBT are performed.
먼저, 전면에 1000Å∼5000Å의 산화막(49)을 증착한 후, 습식 또는 건식식각 방법으로 SiGe HBT 이외의 나머지 부분과 에미터 영역으로 예정된 부분의 산화막(49)을 제거한다. 그후 게이트산화막(50)을 형성하기 위해 700℃∼1000℃에서 5∼15nm의 게이트산화막(50)을 형성시킨 다음, nLDMOS와 CMOS를 제외한 나머지 부분의 게이트산화막(50)을 제거한다.First, an oxide film 49 of 1000 kV to 5000 kV is deposited on the entire surface, and then the oxide film 49 of the remaining portion other than SiGe HBT and the portion scheduled for the emitter region is removed by a wet or dry etching method. Thereafter, the gate oxide film 50 of 5 to 15 nm is formed at 700 ° C. to 1000 ° C. to form the gate oxide film 50, and then the gate oxide film 50 is removed except for nLDMOS and CMOS.
도 3f에 도시된 바와 같이, nLDMOS와 CMOS의 게이트전극(51) 및 SiGe HBT의 에미터 전극(52)을 형성한다.As shown in Fig. 3F, gate electrodes 51 of nLDMOS and CMOS and emitter electrodes 52 of SiGe HBT are formed.
먼저, 1×1019∼1×1021cm-3의 농도를 갖는 1000Å∼5000Å의 n형 다결정실리콘층을 증착한 다음, 1000Å∼10000Å의 캡산화막을 증착한다. 마스크 작업을 통하여 캡산화막과 n형 다결정실리콘층을 순서대로 건식식각하여 CMOS의 게이트전극(51), SiGe-HBT의 에미터전극(52), nLDMOS의 게이트전극(53)을 형성한다. 따라서, SiGe-HBT의 에미터전극(52)과 각 게이트전극(51,53)은 그 상부에 캡산화막(51a)을 포함한다.First, an n-type polycrystalline silicon layer of 1000 kPa to 5000 kPa having a concentration of 1 x 10 19 to 1 x 10 21 cm -3 is deposited, and then a cap oxide film of 1000 kPa to 10000 kPa is deposited. Through the mask operation, the cap oxide film and the n-type polycrystalline silicon layer are dry-etched in this order to form a gate electrode 51 of CMOS, an emitter electrode 52 of SiGe-HBT, and a gate electrode 53 of nLDMOS. Accordingly, the emitter electrode 52 and the gate electrodes 51 and 53 of the SiGe-HBT include a cap oxide film 51a thereon.
도 3g에 도시된 바와 같이, nLDMOS 및 nMOS의 nLDD 영역(54a)과 pMOS의 pLDD 영역(54b)을 형성하고, 게이트전극(53) 및 에미터전극(52)의 양측벽에 스페이서(55)를 형성한다.As shown in FIG. 3G, nLDMOS and nMOS nDD regions 54a and pMOS pLDD regions 54b are formed, and spacers 55 are formed on both side walls of the gate electrode 53 and the emitter electrode 52. Form.
먼저, nLDMOS 및 nMOS의 nLDD 영역(54a)을 형성하기 위해 해당부분을 포토작업하여 인(P)을 이온주입하고, pMOS의 pLDD 영역(54b)을 형성하기 위해 역시 해당부분을 포토작업한 후 BF2를 이온주입한다. 그 다음, 스페이서용 산화막을 전면에 도포한 후 마스크없이 건식식각하여 에미터전극(52) 및 게이트전극(53)의 양측벽에 스페이서(55)를 형성한다.First, phosphorus (P) is ion-implanted by photo-working the corresponding portion to form the nLDMOS region 54a of the nLDMOS and nMOS, and photo-working the corresponding portion to form the pLDD region 54b of the pMOS, and then BF Ion is injected 2 . Then, the spacer oxide film is applied to the entire surface and then dry-etched without a mask to form spacers 55 on both side walls of the emitter electrode 52 and the gate electrode 53.
도 3h에 도시된 바와 같이, nLDMOS의 n형 소스영역(56a), p형 소스영역(57a) 및 n형 드레인영역(56b)을 형성하고, nMOS의 n형 소스영역(56c)과 n형 드레인영역(56d), pMOS의 p형 소스영역(57b)과 p형 드레인영역(57c)을 형성한다.As shown in Fig. 3H, an n-type source region 56a, a p-type source region 57a and an n-type drain region 56b of the nLDMOS are formed, and the n-type source region 56c and n-type drain of the nMOS are formed. The region 56d, the p-type source region 57b and the p-type drain region 57c of the pMOS are formed.
먼저, nLDMOS의 소스영역(56a) 및 드레인영역(56b), nMOS의 소스영역(56c)과 드레인영역(56d)을 형성하기 위하여 마스크 작업을 통하여 인(P) 또는 비소(As)를 1×1015∼1×1016cm-3의 도즈와 30KeV∼80KeV의 에너지로 이온주입한다. 이때, 바이폴라 소자의 콜렉터영역(56e)과 SiGe-HBT의 콜렉터영역(56f)도 함께 형성된다.First, in order to form the nLDMOS source region 56a and drain region 56b and the nMOS source region 56c and drain region 56d, phosphorus (P) or arsenic (As) is 1 × 10 through a mask operation. Ion implantation is carried out with a dose of 15 to 1 × 10 16 cm -3 and an energy of 30 KeV to 80 KeV. At this time, the collector region 56e of the bipolar element and the collector region 56f of SiGe-HBT are also formed.
그 다음, nLDMOS의 p형 소스영역(57a)과 바이폴라 소자의 p형 베이스 영역(57d) 및 pMOS의 p형 소스영역(57b), p형 드레인영역(57c)을 형성하기 위해 마스크 작업을 통하여 BF2를 1×1015∼1×1016cm-3의 도즈와 20KeV∼100KeV의 에너지로 이온주입한다. 그리고 800℃∼1000℃에서 10∼60분간 열처리한다.Then, BF is formed through masking to form the p-type source region 57a of the nLDMOS, the p-type base region 57d of the bipolar device, the p-type source region 57b of the pMOS, and the p-type drain region 57c. 2 is ion implanted at a dose of 1 × 10 15 to 1 × 10 16 cm -3 and an energy of 20 KeV to 100 KeV. And heat-process for 10 to 60 minutes at 800 degreeC-1000 degreeC.
도 3i에 도시된 바와 같이, 모든 소자들의 접점(59)을 형성한다.As shown in FIG. 3I, the contacts 59 of all the elements are formed.
먼저, 5000Å∼15000Å의 층간절연막(58)을 도포한 다음, 마스크작업을 통하여 각 소자의 소스영역, 게이트전극, 에미터전극, 드레인영역, 베이스영역, 콜렉터영역을 개방한 후 5000Å∼10000Å의 메탈을 증착하여 접점(59)을 형성한다.First, an interlayer insulating film 58 of 5000 kV to 15000 kV is applied, and then the source region, the gate electrode, the emitter electrode, the drain region, the base region, and the collector region of each element are opened through a mask operation, and then the metal of 5000 kV to 10000 kV is opened. Is deposited to form the contact 59.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 서브마이크론급에서도 100V 이상의 고내압 특성이 가능한 개방형 드레인을 갖는 LDMOS 소자의 구조 및 40GHz 이상의 초고속 스위칭 특성을 갖는 SiGe HBT, 얕은 접합깊이에서도 60V 이상의 고내압특성이 가능한 바이폴라 소자, 고집적이 가능한 서브마이크론급 MOS 소자 등을 부분 SOI 기판을 사용하여 온칩(On-chip)에 구현하므로써 지능형 전력소자에 비해 더욱더 고내압/초고속/저전력 특성을 만족시키는 첨단 지능형 전력소자를 구현할 수 있는 효과가 있다.The present invention described above is a structure of an LDMOS device having an open drain capable of high breakdown voltage characteristics of 100 V or more even in submicron class, SiGe HBT having ultrafast switching characteristics of 40 GHz or more, a bipolar device having a high breakdown voltage property of 60 V or more even at a shallow junction depth, and high integration. By implementing this sub-micron-class MOS device on-chip using a partial SOI board, it is possible to implement advanced intelligent power device that satisfies higher breakdown voltage / ultra-high speed / low power characteristics than the intelligent power device. have.
또한, 본 발명의 지능형 전력소자는 고성능/다기능/소형화 특성이 요구되는 자동차 전자제어 시스템 및 고속 하드디스크드라이버 및 기타 정보통신 시스템에 다양하게 적용할 수 있는 효과가 있다.In addition, the intelligent power device of the present invention has an effect that can be applied to a variety of automotive electronic control system, high-speed hard disk driver and other information communication systems that require high performance / multi-function / miniaturization characteristics.
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| KR100930150B1 (en) * | 2007-09-07 | 2009-12-07 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
| KR100971532B1 (en) * | 2008-05-27 | 2010-07-21 | 삼성전자주식회사 | A semiconductor device haivng a driving transistor |
| CN110660811A (en) * | 2018-06-28 | 2020-01-07 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN111968973A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | BCD semiconductor device |
| US11094599B2 (en) | 2018-06-28 | 2021-08-17 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
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| KR101126933B1 (en) | 2008-09-02 | 2012-03-20 | 주식회사 동부하이텍 | Bipolar junction transistor of poly-emitter type, Bipolar CMOS DMOS device, manufacturing method of bipolar junction transistor of poly-emitter type and manufacturing method of Bipolar CMOS DMOS device |
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| US5374569A (en) * | 1992-09-21 | 1994-12-20 | Siliconix Incorporated | Method for forming a BiCDMOS |
| KR100188121B1 (en) * | 1996-06-27 | 1999-06-01 | 김광호 | Method of manufacturing bcdmos |
| KR100281908B1 (en) * | 1998-11-20 | 2001-02-15 | 김덕중 | Semiconductor device and manufacturing method |
| KR100336502B1 (en) * | 1999-12-10 | 2002-05-15 | 오길록 | The fabrication method of smart power IC technology concluding trench gate MOS power device |
| KR100412539B1 (en) * | 2001-07-24 | 2003-12-31 | 한국전자통신연구원 | BCD device and method of manufacturing the same |
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| KR100930150B1 (en) * | 2007-09-07 | 2009-12-07 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
| KR100971532B1 (en) * | 2008-05-27 | 2010-07-21 | 삼성전자주식회사 | A semiconductor device haivng a driving transistor |
| US8258517B2 (en) | 2008-05-27 | 2012-09-04 | Samsung Electronics Co., Ltd. | Semiconductor device having driving transistors |
| CN110660811A (en) * | 2018-06-28 | 2020-01-07 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| US11094599B2 (en) | 2018-06-28 | 2021-08-17 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| US11152485B2 (en) | 2018-06-28 | 2021-10-19 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| US11152484B2 (en) | 2018-06-28 | 2021-10-19 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| CN111968973A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | BCD semiconductor device |
| CN111968973B (en) * | 2020-08-28 | 2023-09-22 | 电子科技大学 | BCD semiconductor device |
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