JPH11233643A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the dispersion in an element characteristics, to form junction with less leakage currents and to realize an N well-N well isolation characteristic, by previously doping impurity for channel stopper to the base of a trench between N wells different in power voltage. SOLUTION: P-type impurity is injected into a prescribed region on a semiconductor substrate 101, and the pattern of a mask material 104 regulating the prescribed region of area into which p-type impurity is injected as an element separation area is formed. The semiconductor substrate 101 is etched with the mask material 104 as a mask. Then, p-type second impurity areas 105 are formed in the etched regions. Since impurity for channel stopper is previously doped to the base of the trench between the N wells different in power voltage, unnecessary impurity is prevented from being introduced to an active area. Then, dispersion of the element characteristic is suppressed, and junction with less leak current can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a so-called well-in-well method.
-Well) relates to a method for manufacturing a semiconductor device having a structure.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor memory cell having a so-called well-in-well structure, for example,
N wells formed in the p-type semiconductor substrate (regions mostly including N-type impurities, regions in which p-channel transistors and the like are formed) are electrically formed into an NPN structure by the p-type semiconductor substrate. In many cases, desired isolation characteristics between N wells cannot be satisfied only by the impurity concentration of the p-type semiconductor substrate.

In particular, (1) when a low-concentration substrate is used because it does not affect the transistor characteristics and the like,
(2) When the N wells have different potentials to generate a potential difference (internal step-down / step-up, common source-sub connection, etc.)
(3) N-well to increase the degree of integration of the semiconductor chip
In the case where it is desired to reduce the N-well distance or the like, it is difficult to secure the separation characteristics.

In these cases, a method of forming a P well in the last step between the N well and the N well can be considered. That is, for example, well-
In the case of the in-well structure, the impurity region 31 is separated under the P-well 309 to separate the N-well 313 (P-well bottom) and 310 (P-well side).
2 is formed. Hereinafter, this method will be described by taking a conventional method of manufacturing a CMOS integrated circuit having a well-in-well structure as an example.

That is, first, after a silicon oxide film 302 and a silicon nitride film 303 are sequentially laminated on a p-type semiconductor substrate, a resist film 304 is formed on the entire surface, predetermined patterning is performed, and the resist is used as a mask. RIE of silicon oxide film, silicon nitride film and silicon semiconductor substrate
(FIG. 7A).

Next, after the resist film 304 is peeled off, Si
A so-called STI (Shallow Tren) is formed by forming a silicon oxide film 305 so as to fill the trench and polishing it by a CMP (Chemical Mechanical Polishing) method.
ch Isolation) (FIG. 7B). Subsequently, a resist film 306 is formed and predetermined patterning is performed (FIG. 7C), and an n-type impurity is deeply implanted into the NMOS region to form an n-type impurity region 308. A p-type impurity is ion-implanted into the
Is formed (FIG. 8D).

Next, as shown in FIG. 8 (e), after the resist film 306 is peeled off, a resist film 311 is formed and predetermined patterning is performed to remove the NMOS region from the N well-N well. Then, an n-type impurity is ion-implanted into the region to form an n-type impurity region 310. Further, as shown in FIG. 8E, after the resist film 311 is peeled off, a resist film 313 is formed, predetermined patterning is performed, and a p-type impurity is ion-implanted into a region separating the N well-N well. Then, a p-type impurity region 312 is formed.

However, in the above method, the step of forming the additional resist 313 (FIG. 8 (e))
It is necessary to implant a type impurity. In addition, since the p-type impurity region is finally formed in the region separating the N well-N well, especially when the distance between the N well and the N well is shortened, the n type between the N well and the N well is reduced. There is a possibility that the impurity regions come close to each other and the N well-N well separation characteristics become insufficient.

Therefore, in a semiconductor device, particularly in a semiconductor device having a well-in-well structure, there is a need to develop a method of manufacturing a semiconductor device that can satisfy desired isolation characteristics between N wells. .

[0010]

However, FIG.
The well-in-well structure shown in (f) can be separated into N-well and P-well, so that DRAM (Dynamic Random Acc) using different potential N-well and different potential P-well is used.
ess Memory) is frequently used in a mixed Logic process and the like. Further, since the N well is formed separately on the side and bottom of the P well, no N-type impurity is introduced into the P well region, and the P well is formed as compared with the method of simply forming the P well in the N well. Well total impurity concentration (total impurity concentration)
To reduce the junction leakage current,
This is a method suitable for forming a memory cell such as a DRAM.

Therefore, the present invention realizes a well-in-well structure as shown in FIG. 8 (f), without affecting the substrate surface concentration and without adding a masking step. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of realizing N-well-N-well separation characteristics.

[0012]

In order to achieve the above object,
The present invention provides a step of implanting a first conductivity type impurity into a predetermined region on a semiconductor substrate, and a method of forming a mask material defining a predetermined region of the first conductivity type impurity as an element isolation region. Forming a pattern, etching the semiconductor substrate using the mask material as a mask, and forming a second impurity region having the same conductivity type as the first conductivity type impurity in the region where the semiconductor substrate is etched. And a method of manufacturing a semiconductor device.

Further, the present invention provides a step of implanting a first conductivity type impurity into a predetermined region on a semiconductor substrate, and using the predetermined region of the first conductivity type impurity implanted region as an element isolation region. A step of forming a mask material pattern to be defined; a step of forming a resist pattern that defines a predetermined region of the region into which the impurity of the first conductivity type has been implanted as an element isolation region; and defining the resist pattern as the element isolation region. A second region having the same conductivity type as the first conductivity type impurity is formed in a predetermined region.
A method of manufacturing a semiconductor device, comprising the steps of: forming an impurity region of claim 1; and removing the resist and then etching the semiconductor substrate using the mask material as a mask.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming an STI (Shallow Trench Isolation) as an element isolation after forming the second impurity region; Implanting an impurity of a conductivity type opposite to the first conductivity type to form a third impurity region; and implanting an impurity of the same conductivity type as the first conductivity type into the upper layer of the third impurity region. And a step of forming a fourth impurity region.

In the step of forming the third impurity concentration, the impurity of the same conductivity type as that of the first conductivity type is added to the second impurity concentration.
Implanting at a concentration higher than the impurity concentration of the impurity region. The step of forming the second impurity includes the step of forming the second impurity region between the separated third impurity regions. It is preferred that

Further, in the present invention, the step of forming the fourth impurity region includes forming the fourth impurity region in a region surrounded by the third impurity region, and forming the fourth impurity region with the first impurity region. More preferably, it is a step of electrically separating.

Further, in the present invention, preferably,
After the formation of the fourth impurity region, the second and fourth impurity regions are formed.
Forming a fifth impurity region by implanting an impurity of the opposite conductivity type to the first impurity into the impurity region.

Further, in the present invention, preferably, after the formation of the fourth impurity region, a step of further implanting an impurity of the same conductivity type as the fourth impurity into the fourth impurity region is provided.

According to the present invention, in a multiple power supply IC in which an element isolation region is formed by a trench method, an impurity for a channel stopper is previously doped into the bottom of the trench between N wells having different power supply voltages. It is a manufacturing method of an apparatus.

According to the present invention, a semiconductor device having a well-in-well structure having the following characteristics can be manufactured. (1) Since an impurity for a channel stopper is previously doped into the bottom of the trench between N wells having different power supply voltages, unnecessary impurities are not introduced into the active region. Therefore, it is possible to suppress a variation in element characteristics and form a junction with a small leak current.

(2) For example, using a p-type semiconductor substrate doped with a relatively low concentration
Since the separation between the well and the N well is ensured, it is possible to form the different potential N well while realizing high integration. Further, by forming a different potential N well,
Internal step-down and transistor source-sub. Use of a common connection or the like can be realized, and device performance can be improved.

(3) Since the P-well can be separated from the P-type semiconductor substrate, the DRAM memory cell and the well such as the peripheral Logic portion can be completely separated. Therefore, a substrate bias can be applied to the memory cell, carrier injection into the cell can be suppressed, and good holding characteristics can be obtained.

[0023]

Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The embodiment of the invention described below is an example to which the semiconductor manufacturing method of the present invention is applied, and can be applied to the manufacture of other semiconductor devices without departing from the gist of the present invention.

First Embodiment FIG. 3I shows a CM having a well-in-well structure manufactured by a method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing of the manufacturing intermediate of OS integrated circuit. FIG. 3 (i)
In the figure, 101 is a p-type semiconductor substrate, 110 is a fifth impurity region (n-type impurity region), 105 is a second impurity region (p-type impurity region) separating between N wells and N wells, 1
06 is a silicon oxide film formed by a trench method, 109
Indicates a fourth impurity region (p-type impurity region).

Next, the manufacturing route up to FIG. 3 (i) will be described with reference to the drawings. First, for example, 5 × 1
A p-type silicon semiconductor substrate 101 containing a p-type impurity at a concentration of about 0 ¹⁴ / cm ³ is manufactured. In this case, by using a p-type or n-type semiconductor substrate having a relatively low impurity concentration, the body effect (Bodyeffect) can be improved.
ct) The characteristics can be improved.

In the present invention, a boron compound or the like can be used as a p-type impurity, and a compound such as phosphorus or arsenic, which is a Group 5B element of the periodic table, can be used as an n-type impurity. Further, the impurity implantation may be performed by a plurality of ion implantations having different acceleration energies. According to the ion implantation a plurality of times, fine control of the impurity concentration becomes possible.

Next, as shown in FIG.
A silicon oxide film 102 is formed on the
After being formed to a thickness of about 5 nm, the silicon oxide film 10
2, a silicon nitride film 103 is formed with a thickness of, for example, 200 nm. The silicon oxide film is formed by a thermal oxidation method,
The silicon nitride film can be formed by a low pressure CVD method by a VD (Chemical Vapor Deposition) method or the like. The silicon nitride film plays a role as a CMP stopper.

Next, as shown in FIG. 1B, a resist film 104 is formed on the entire surface, and predetermined patterning is performed.
Next, as shown in FIG. 1C, using the resist pattern as a mask, the silicon oxide film 102, the silicon nitride film 103, and the p-type semiconductor substrate 101 are sequentially formed, for example, by, for example,
Etching is performed by RIE (Reactive Ion Etching).

Then, as shown in FIG. 2D, a p-type impurity (boron or the like) is ion-implanted using the resist pattern as a mask to form a second impurity region 1.
05 is formed. The impurity concentration is 10 ¹⁵ to 10 ¹⁸ / cm
^{About 3} is preferable. By forming the impurity region of the second conductivity type in advance, the impurity concentration in the substrate is increased without affecting the vicinity of the silicon surface where a transistor and a junction are formed in a later step. The effect can be obtained. That is, variations in transistor characteristics due to variations in impurity concentration near the surface can be reduced. In addition, since the impurity concentration in the vicinity of the junction decreases, junction leakage can be reduced.

Next, as shown in FIG. 2E, after removing the resist 104, a silicon oxide film 106 is deposited by, for example, a thermal oxidation method, a CVD method, or the like so as to fill the Si trench, and is then subjected to a CMP method. Polished, silicon nitride film 10
3 to remove the so-called STI (Shallow Trench Isola
formation). This method is a shallow trench isolation as an element isolation between adjacent memory cells, and has an isolation width of 0.1 mm.
This is a high breakdown voltage element isolation method of 4 μm or less.

Further, as shown in FIG. 2 (f), a resist film 107 is formed on the entire surface, predetermined patterning is performed, and as shown in FIG. A third conductivity type impurity region 108 is formed by deeply implanting a type impurity, and a p-type impurity is ion-implanted into an upper layer of the third conductivity type impurity region 109 to form a fourth conductivity type impurity region 109. The impurity concentration of the third conductivity type impurity region is 10
It is about ¹⁶ to 10 ¹⁸ / cm ³ . Further, the impurity concentration of the third conductivity type impurity region is at least the second impurity concentration.
Is preferably higher than the impurity concentration. The third conductivity type impurity region is formed by ion-implanting the second conductivity type impurity region, so that it is a complete n-type impurity region (see FIG. 3 (g) and the like).

In the fourth impurity region, the impurity concentration may change in the depth direction in order to set the threshold value of the transistor or to set the channel stopper under the STI to a required concentration. , N-type wells to form buried transistors in the N-well.
(Type) impurity region.

Here, after forming the fourth impurity region by ion implantation, an impurity of the same conductivity type as the fourth impurity may be additionally implanted into the fourth impurity region as a channel stopper. preferable. At this time, the energy of the ion implantation is such that the ions are
06 is sufficient if it can reach the surface of the fourth impurity region 109. The impurity concentration is, for example, 1 ×
It is about 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ .

Next, predetermined patterning is performed, and a fifth conductivity type impurity region 110 is formed using the resist pattern as a mask. At this time, it is also preferable to additionally implant an impurity of the same conductivity type as the fifth impurity into the fifth conductivity type impurity region as a channel stopper. The energy of the ion implantation at this time is sufficient as long as the ions can pass through the silicon oxide film 106 and reach the surface of the fifth impurity region 110. The impurity concentration is, for example, 1
It is about × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ .

Thereafter, the resist 111 is peeled off, and FIG.
The state shown in (i) is obtained. From the state shown in FIG. 3 (i), NMOS transistors are placed on A, and PMOS transistors are placed on B and C.
By forming a transistor and sequentially forming an interlayer insulating film, a contact hole, a wiring layer, and the like, a desired semiconductor device such as a CMOS type DRAM can be manufactured.

As shown in FIG. 3 (i), the semiconductor device (manufactured intermediate) obtained as described above is
Has a structure surrounded by an N-well (fifth conductivity type impurity region). At this time, since the p-type impurity region is formed in advance between the N wells, a semiconductor device having excellent isolation characteristics can be manufactured.

Second Embodiment FIG. 6H shows a manufacturing intermediate of a CMOS integrated circuit having a well-in-well structure manufactured by the same method of manufacturing a semiconductor device of the present invention as in the first embodiment. It is sectional drawing. In FIG. 6H, 201 is a p-type semiconductor substrate, 21
0 is the fifth conductivity type impurity region (n-type impurity region), 20
Reference numeral 5 denotes a second conductivity type impurity region (p-type impurity region) for separating an N well from an N well, which is formed by a trench method.
05 denotes a silicon oxide film, and 209 denotes a fourth conductivity type impurity region (p-type impurity region).

Next, the manufacturing route up to FIG. 6H will be described with reference to the drawings. First, for example, 5 × 10
A p-type silicon semiconductor substrate 201 containing an n-type impurity at a concentration of about ¹⁴ / cm ³ is manufactured. In this case,
By using a p-type or n-type semiconductor substrate having a relatively low impurity concentration, a body effect (Body effect) is obtained.
t) The characteristics can be improved. Also in the present embodiment, a boron compound or the like can be used as the p-type impurity, and a compound such as phosphorus or arsenic, which is a Group 5B element of the periodic table, can be used as the n-type impurity.

Next, as shown in FIG.
A silicon oxide film 202, for example,
After being formed to a thickness of about 5 nm, the silicon oxide film 20 is formed.
2, a silicon nitride film 203 is formed with a thickness of, for example, 200 nm. The silicon oxide film is formed by a thermal oxidation method,
The silicon nitride film can be formed by a low pressure CVD method by a VD (Chemical Vapor Deposition) method or the like. The role of the silicon nitride film as a stopper for CMP is the same as in the first embodiment.

Next, as shown in FIG. 4B, a resist film 204 is formed on the entire surface, and predetermined patterning is performed.
Next, as shown in FIG. 4C, using the resist pattern as a mask, the silicon oxide film 202, the silicon nitride film 203, and the p-type semiconductor substrate 201 are sequentially formed, for example, as follows.
Etching is performed by RIE (Reactive Ion Etching).

Next, a second conductivity type impurity region 205 is formed by ion-implanting a p-type impurity (boron or the like) using the resist pattern as a mask. The impurity concentration is preferably about 10 ¹⁵ to 10 ¹⁸ / cm ³ . The effect of forming the second conductivity type impurity region at this stage is as described in the first embodiment.

Next, after the resist 204 is peeled off, the silicon oxide film 206 is formed by, for example, a thermal oxidation method using the silicon nitride film 203 as a mask so as to fill the Si trench.
It is formed by the D method or the like. Next, the silicon nitride film 203 is removed by polishing by a CMP method, and the so-called STI
(Shallow Trench Isolation) is formed, and FIG.
The state shown in is obtained. In the following steps, a desired semiconductor device can be manufactured in the same manner as in FIG. 2F and later described in the first embodiment (FIGS. 5F to 6H).

As in the first embodiment, after forming the fourth impurity region, a channel stopper is formed.
It is also preferable to additionally implant an impurity of the same conductivity type as the fourth impurity into the fourth impurity region and an impurity of the same conductivity type as the fifth impurity into the fifth impurity region. The energy of the ion implantation at this time is sufficient as long as the ions can pass through the silicon oxide film 106 (206) and reach the surface layer of the fifth impurity region 110 (210). The impurity concentration is, for example, 1 × 10 ¹⁶ to 1 × 10
It is about ¹⁸ / cm ³ .

In the present embodiment, a trench is formed in a Si substrate using silicon nitride as a mask (stopper). According to this method, the influence of carbon contained in the resist can be eliminated. / N
The etching conversion difference at the time of Si etching due to the etching deposit on the side surface of the resist generated at the time of non-doped silicate glass (SG) etching can be eliminated.

The method for manufacturing a semiconductor device according to the present invention
Well-in-well semiconductor device, for example, CMOS
The present invention can be suitably applied to manufacturing of a DRAM of a type.

[0046]

As described above, the present invention particularly provides
A method of manufacturing a semiconductor device having a well-in-well structure, wherein an impurity for a channel stopper is previously doped into the bottom of a trench between N wells having different power supply voltages. According to the present invention, a semiconductor device having the following characteristics can be manufactured.

(1) Since an impurity for a channel stopper is previously doped into the bottom of the trench between N wells having different power supply voltages (when the substrate is a p-type), unnecessary impurities may be introduced into the active region. Absent. Therefore, it is possible to suppress a variation in element characteristics and form a junction with a small leak current.

(2) For example, using a p-type semiconductor substrate doped with a relatively low concentration
Since the separation between the well and the N well is ensured, it is possible to form the different potential N well while realizing high integration. Further, by forming a different potential N-well, internal step-down and transistor Source-Sub. Use of a common connection or the like can be realized, and device performance can be improved.

(3) Since the P-well can be separated from the P-type semiconductor substrate, the DRAM memory cell and the well such as the peripheral Logic portion can be completely separated. Therefore, a substrate bias can be applied to the memory cell, carrier injection into the cell can be suppressed, and good holding characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a state diagram of main steps of a method of manufacturing a semiconductor device according to a first embodiment. FIG. 1A is a diagram in which a silicon oxide film and a silicon nitride film are formed on a p-type semiconductor substrate. FIG. 2B is a diagram in which a predetermined patterning is performed after forming a resist film, and FIG. 2C is a diagram in which a silicon oxide film, a silicon nitride film, and a silicon substrate are etched using the resist as a mask. is there.

FIG. 2 is a state diagram of main steps of a method of manufacturing the semiconductor device according to the first embodiment. FIG. 2D is a diagram in which a p-type impurity is doped from the state shown in FIG. Yes, (e)
FIG. 4 is a view in which an STI is formed, and FIG. 4F is a view in which a resist film is formed from the state shown in FIG.

FIG. 3 is a state diagram of main steps of a method of manufacturing the semiconductor device according to the first embodiment. FIG. 3 (g) shows a third conductivity type impurity region and a fourth conductivity type impurity in an NMOS region. FIG. 5H is a diagram in which a region is formed. FIG. 5H shows a state in which the resist is stripped from the state shown in FIG. And FIG. 7I is a diagram in which a fifth conductive type impurity region is formed by doping with a resist film. FIG.

FIG. 4 is a state diagram of main steps of a method of manufacturing a semiconductor device according to a second embodiment. FIG. 4A is a diagram in which a silicon oxide film and a silicon nitride film are formed on a p-type semiconductor substrate. FIG. 2B is a view showing a state where a predetermined patterning is performed after forming a resist film, and FIG. FIG.

FIG. 5 is a state diagram of main steps of a method of manufacturing a semiconductor device according to a second embodiment.
FIG. 4E is a diagram in which a type impurity is doped, and FIG. 5E is a diagram in which after removing a resist film, a trench is formed in a silicon substrate using a silicon nitride film as a mask to form an STI;
(F) is a diagram in which a third conductive type impurity region and a fourth conductive type impurity region are formed in a region where an NMOS is to be formed by performing a predetermined patterning after forming a resist film.

FIG. 6 is a state diagram of main steps of a method of manufacturing a semiconductor device according to a second embodiment. FIG. 6 (g) shows that after the resist film is peeled off, a resist film is formed again, and FIG. 9 is a diagram in which an n-type impurity is doped by using a resist pattern as a mask after patterning to form a fifth conductivity type impurity region, and (h) is a diagram in which the resist film is removed from the state shown in (g). is there.

FIG. 7 is a conventional CMO having a well-in-well structure.
It is a main process drawing of the manufacturing method of S integrated circuit, (a) is
FIG. 4B is a diagram in which a silicon oxide film and a silicon nitride film are formed on a p-type semiconductor substrate, a resist film is formed, and then a predetermined patterning is performed. FIG. And STI is formed,
FIG. 3C is a diagram in which after a resist film is formed, predetermined patterning is performed, and then an n-type impurity region and a p-type impurity region are formed in a region where an NMOS is to be formed.

FIG. 8 is a CMO having a conventional well-in-well structure.
It is a main process figure of the manufacturing method of S integrated circuit, (d) is
FIG. 4E is a diagram in which after a resist film is formed, a predetermined patterning is performed, and then an n-type impurity is doped. (E) is a diagram in which, after the resist film is formed, a predetermined patterning is performed, FIG. 7 is a diagram in which a region between the second N wells is doped with a p-type impurity, and FIG. 7 (f) is a diagram in which the resist film is removed from the state shown in FIG.

[Explanation of symbols]

101, 201, 301... P-type silicon semiconductor substrate, 1
02, 202, 302, 106, 206, 305: silicon oxide film, 103, 203, 303: silicon nitride film, 104, 107, 204, 207, 304, 30
6,313 ... resist film, 105,205 ... second conductivity type impurity region, 108,308 ... third conductivity type impurity region, 109,309 ... fourth conductivity type impurity region, 11
0, 310, 314... Fifth impurity type impurity region, 312
... p-type impurity region, A, B, C ... MOSFET formation site

Claims (18)

[Claims] A step of implanting an impurity of a first conductivity type into a predetermined region on a semiconductor substrate; and a mask material defining a predetermined region of the region into which the impurity of the first conductivity type is implanted as an element isolation region. Forming a pattern of: a step of etching the semiconductor substrate using the mask material as a mask; and implanting an impurity of the same conductivity type as the first conductivity type impurity into the region where the semiconductor substrate is etched. Forming a second impurity region. 2. A step of implanting a first conductivity type impurity into a predetermined region on a semiconductor substrate, and a mask material defining a predetermined region of the first conductivity type impurity implanted region as an element isolation region. Forming a resist pattern defining a predetermined region of the region into which the impurity of the first conductivity type has been implanted as an element isolation region; and forming a resist pattern defining the element isolation region as a predetermined region. Forming a second impurity region by injecting an impurity of the same conductivity type as the first conductivity type impurity; removing the resist; and etching the semiconductor substrate using the mask material as a mask And a method of manufacturing a semiconductor device. 3. A step of forming an STI (Shallow Trench Isolation) as an element isolation after forming the second impurity region; and forming a conductive type opposite to the first conductive type in a predetermined region of the STI. Forming a third impurity region by implanting an impurity of a third impurity region; and implanting an impurity of the same conductivity type as the first conductivity type into the upper layer of the third impurity region to form a fourth impurity region. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: 4. The step of forming the third impurity concentration comprises:
4. The method of manufacturing a semiconductor device according to claim 3, wherein an impurity of the same conductivity type as the first conductivity type is implanted at a concentration higher than an impurity concentration of the second impurity region. 5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second impurity is a step of forming the second impurity region between the separated third impurity regions. Method. 6. The step of forming the fourth impurity region,
4. The method according to claim 3, wherein the fourth impurity region is formed in a region surrounded by the third impurity region, and is electrically separated from the first impurity region. 5. 7. The method according to claim 1, further comprising: forming the second impurity region after forming the fourth impurity region.
4. The method of manufacturing a semiconductor device according to claim 3, further comprising: implanting an impurity of a conductivity type opposite to the first impurity into the fourth impurity region to form a fifth impurity region. 5. 8. The method according to claim 3, further comprising, after forming the fourth impurity region, implanting an impurity of the same conductivity type as the fourth impurity into the fourth impurity region. Method. 9. The method of manufacturing a semiconductor device according to claim 3, further comprising, after forming the fifth impurity region, implanting an impurity of the same conductivity type as the fifth impurity into the fifth impurity region. Method. 10. After forming the second impurity region,
STI (Shallow Trench Isolation) as element isolation
Forming a third impurity region by implanting an impurity of a conductivity type opposite to a first conductivity type into a predetermined region of the STI; and forming a third impurity region on an upper layer of the third impurity region. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: implanting an impurity having the same conductivity type as the first conductivity type to form a fourth impurity region. 4. 11. The step of forming the third impurity concentration is a step of implanting an impurity of the same conductivity type as the first conductivity type at a concentration higher than the impurity concentration of the second impurity region. A method for manufacturing a semiconductor device according to claim 10. 12. The manufacturing of a semiconductor device according to claim 2, wherein the step of forming the second impurity is a step of forming the second impurity region between the third impurity regions separated from each other. Method. 13. The step of forming the fourth impurity region includes forming the fourth impurity region in a region surrounded by the third impurity region and electrically separating the fourth impurity region from the first impurity region. The method of manufacturing a semiconductor device according to claim 10, wherein: 14. After the formation of the fourth impurity region, a fifth impurity region is formed by implanting an impurity of a conductivity type opposite to that of the first impurity into the second and fourth impurity regions. The method of manufacturing a semiconductor device according to claim 10, further comprising: 15. The manufacturing of a semiconductor device according to claim 10, further comprising, after forming the fourth impurity region, implanting an impurity of the same conductivity type as the fourth impurity into the fourth impurity region. Method. 16. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of implanting an impurity of the same conductivity type as said fifth impurity into said fifth impurity region after forming said fifth impurity region. Method. 17. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor device having a well-in-well structure. 18. The method according to claim 2, wherein the semiconductor device is a semiconductor device having a well-in-well structure.