KR20030056797A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- KR20030056797A KR20030056797A KR1020010087096A KR20010087096A KR20030056797A KR 20030056797 A KR20030056797 A KR 20030056797A KR 1020010087096 A KR1020010087096 A KR 1020010087096A KR 20010087096 A KR20010087096 A KR 20010087096A KR 20030056797 A KR20030056797 A KR 20030056797A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 종래 격리막으로만 이용하던 격리 영역을, 소정 폭을 키워 트렌치형으로 식각하여, 상기 트렌치 내부에 트랜지스터를 형성함으로써 집적도를 향상시킨 반도체 소자의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a semiconductor device in which an integration area is improved by etching a isolation region, which has been used only as a conventional isolation film, by increasing a predetermined width to form a trench in the trench. .
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 형성 방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1은 종래의 반도체 소자 형성 방법을 나타낸 공정 단면도이다.1 is a process sectional view showing a conventional method of forming a semiconductor device.
도 1과 같이, 종래의 반도체 소자는 P형 기판(11)의 활성 영역상에 형성된다.As shown in Fig. 1, a conventional semiconductor element is formed on the active region of the P-type substrate 11.
이 때, 상기 활성 영역은 트랜지스터가 형성되는 영역으로, 트랜지스터와 트랜지스터와의 격리를 위하여, STI 공정으로 트렌치를 형성한 후, 상기 트렌치 내부에 격리 산화막을 채워 격리 산화막(14)을 형성한다.In this case, the active region is a region in which a transistor is formed. In order to isolate the transistor from the transistor, a trench is formed by an STI process and an isolation oxide layer 14 is formed by filling an isolation oxide layer in the trench.
상기 트렌치로 기판(11)의 영역을 구분하여 제 1 영역은 N-웰(12)로, 제 2 영역을 P-웰(13)로 이온 주입 공정을 통해 형성한다.The trench is divided into regions of the substrate 11 to form a first region as an N-well 12 and a second region as an P-well 13 through an ion implantation process.
이어, 제 1, 제 2 영역 각각 N-웰(12)과 P-웰(13)상에, 게이트 산화막, 게이트 전극(15, 16)을 형성한 후, 상기 게이트 전극(15, 16) 양쪽 기판상에 고농도 이온주입(제 1 영역에는 p+이온 주입, 제 2 영역에는 n+ 이온 주입)을 하여 소오스/드레인(17, 18)을 형성한다.Subsequently, after the gate oxide film and the gate electrodes 15 and 16 are formed on the N-well 12 and the P-well 13, respectively, the first and second regions are formed on both substrates of the gate electrodes 15 and 16. High concentration ion implantation (p + ion implantation in the first region and n + ion implantation in the second region) is performed on the phase to form the source / drain 17 and 18.
그러나, 상기와 같은 종래의 반도체 소자의 형성 방법은 다음과 같은 문제점이 있다.However, the conventional method of forming a semiconductor device as described above has the following problems.
즉, 트랜지스터와 트랜지스터간의 격리 방법에는 로코스(LOCOS : LOCal Oxidation of Silicon) 공정 및 STI(Shallow Trench Isolation) 공정이 있으나 칩 크기가 작아짐에 따라 상기의 공정으로 형성한 격리 산화막 주위에 버즈 비크(bird's beak) 현상이 발생하는 등 계면에서의 격리 특성이 악화되어, 고집적 설계에서는 트랜지스터와 트랜지스터간의 기생 저항이 증가하는 문제 때문에 동작불량이 발생할 수 있다.That is, the isolation method between the transistor and the transistor includes a LOCOS (LOCal Oxidation of Silicon) process and a Shallow Trench Isolation (STI) process. Due to the deterioration of isolation characteristics at the interface, such as the occurrence of beaks, and high density design, parasitic resistance between transistors may increase, resulting in malfunction.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 종래 격리막으로만 이용하던 격리 영역을, 소정 폭을 키워 트렌치형으로 식각하여, 상기 트렌치 내부에 트랜지스터를 형성함으로써 집적도를 향상시킨 반도체 소자의 형성 방법을 제공하는 데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the isolation region used as a conventional isolation film is etched into a trench by increasing a predetermined width to form a transistor in the trench, thereby forming a semiconductor device having improved integration. The purpose is to provide a method.
도 1은 종래의 반도체 소자 형성 방법을 나타낸 공정 단면도1 is a cross-sectional view illustrating a conventional method of forming a semiconductor device.
도 2는 본 발명의 반도체 소자 형성 방법을 나타낸 공정 단면도2 is a process cross-sectional view showing a method of forming a semiconductor device of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
21 : 기판 22 : P형 웰21 substrate 22 p-type well
23 : N형 웰 24 : 격리 박막23 N-type well 24: isolation thin film
25 : 폴리 실리콘층 26 : 활성 영역의 게이트 전극25 polysilicon layer 26 gate electrode of active region
27 : 격리 영역의 게이트 전극 28 : 활성 영역의 소오스/드레인27: gate electrode of isolation region 28: source / drain of active region
29 : 격리 영역의 소오스/드레인29 Source / Drain in Quarantine
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 형성 방법은 기판에 트랜지스터가 형성되는 활성 영역과 트랜지스터들간의 격리를 행하는 격리 영역을 정의하는 단계와, 상기 격리 영역의 소정 영역을 트렌치 형으로 식각하는 단계와, 상기 트렌치 내부 표면에 격리 박막을 얇게 증착하는 단계와, 상기 트렌치 내부에 폴리 실리콘층을 채우고 기판 표면을 엔드 포인트로 하여 평탄화하는 단계와, 상기 폴리 실리콘층의 소정 영역 상에 게이트 산화막 및 게이트 전극을 형성하고, 상기 게이트 전극 양측의 폴리 실리콘층에 소오스/드레인을 형성하여 격리 영역 트랜지스터를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a semiconductor device of the present invention for achieving the above object is to define an active region in which a transistor is formed on a substrate and an isolation region for isolating transistors, and to form a predetermined region of the isolation region in a trench type. Etching, thinly depositing an isolation thin film on the inner surface of the trench, filling the polysilicon layer in the trench and planarizing the substrate surface as an endpoint, and gates on a predetermined region of the polysilicon layer And forming an isolation layer transistor by forming an oxide layer and a gate electrode, and forming a source / drain in the polysilicon layers on both sides of the gate electrode.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 형성 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 반도체 소자의 형성 방법을 나타낸 공정 단면도이다.2 is a cross-sectional view illustrating a method of forming a semiconductor device of the present invention.
도 2와 같이, 본 발명의 반도체 소자의 형성 방법은 산화막을 채워 격리 영역으로 이용되던 종래의 STI형 트렌치를 그 내부 표면에 얇게 격리 박막(24)을 증착하고, 이어 상기 트렌치 내부를 폴리 실리콘층(25)으로 채워 상기 폴리실리콘층(25)에 활성 영역과는 별도의 트랜지스터를 형성하는 것을 특징으로 한다.As shown in FIG. 2, in the method of forming a semiconductor device of the present invention, a conventional thin film of an STI trench, which is used as an isolation region by filling an oxide layer, is deposited on the inner surface of the trench, and then the inside of the trench is deposited with a polysilicon layer. Filled with (25) to form a transistor separate from the active region in the polysilicon layer (25).
먼저, P형의 기판(21)에 마스크를 이용한 이온 주입 공정을 진행하여 P형 웰(22)과 N형 웰(23)을 형성한다.First, an ion implantation process using a mask is performed on the P-type substrate 21 to form the P-type well 22 and the N-type well 23.
상기 P형 웰(22)과 N형 웰(23) 영역간, 즉 각 액티브 영역에 생성되는 트랜지스터간의 격리를 위해 소정 영역을 트렌치형으로 제거한다.In order to isolate the region between the P-type well 22 and the N-type well 23, that is, between transistors generated in each active region, a predetermined region is removed in a trench.
이어, 상기 트렌치 표면에 격리 박막(24)을 증착한다.Subsequently, an isolation thin film 24 is deposited on the trench surface.
이어, 상기 격리 박막(24)상에 폴리 실리콘층(25)을 상기 각 웰 표면(22, 23) 표면 높이로 형성한다. 이 때, 상기 상기 폴리 실리콘층(25)은 도핑되지 않은 폴리 실리콘층이다.Next, a polysilicon layer 25 is formed on the isolation thin film 24 at the surface height of each well surface 22 and 23. In this case, the polysilicon layer 25 is an undoped polysilicon layer.
상기 P형 웰(22) 영역 상 및 상기 폴리 실리콘층(25) 상에 각각 게이트 산화막, 게이트 전극(26, 27)을 증착하고, 상기 게이트 전극(27) 양측의 기판(22, 25)에 이온 주입을 진행하여 각 영역에 소오스/드레인(28, 29)을 형성한다.Gate oxide layers and gate electrodes 26 and 27 are deposited on the P-type well 22 and the polysilicon layer 25, respectively, and ions are deposited on the substrates 22 and 25 on both sides of the gate electrode 27. Implantation is performed to form sources / drains 28 and 29 in each region.
상기 격리 박막상에 증착된 폴리 실리콘층(25)에 P형의 고농도 이온을 도핑하여 P형 소오스/드레인(29)을 형성하여 P모스 트랜지스터를 형성하고, 활성 영역인 N웰(22) 상에 N형의 고농도 이온을 도핑하여 N형 소오스/드레인(28)을 형성하여 N모스 트랜지스터를 형성한다.P-type source / drain 29 is formed by doping P-type high concentration ions into the polysilicon layer 25 deposited on the isolation thin film to form a P-MOS transistor, and on the N well 22 which is an active region N-type high concentration ions are doped to form an N-type source / drain 28 to form an N-MOS transistor.
이 때, 격리 영역에 트랜지스터를 형성하는 것은 활성 영역의 트랜지스터를 형성하는 단계와 동일한 단계에서 이루어지며, 이러한 트랜지스터 형성 방법은 일반적인 트랜지스터 제조 공정을 따른다.In this case, forming the transistor in the isolation region is performed at the same stage as forming the transistor in the active region, and this transistor forming method follows a general transistor manufacturing process.
본 발명은 STI 방식을 이용하여 트랜지스터와 트랜지스터간의 격리를 취한후, STI 식각된 격리 영역에 격리 물질 및 도핑되지 않은 폴리 실리콘(Undoped Poly silicon)층을 충분히 증착하고 CMP(Chemical Mechanical Polishing) 공정을 진행하여 격리 영역(field area)에만 폴리 실리콘을 남기게 한다. 이러한 격리 영역의 폴리 실리콘을 이용하여 격리 영역의 트랜지스터를 형성하는 것이다.After the isolation between the transistor and the transistor using the STI method, the present invention sufficiently deposits an isolation material and an undoped poly silicon layer on the STI-etched isolation region and proceeds with a chemical mechanical polishing (CMP) process. This leaves polysilicon only in the field area. By using polysilicon in this isolation region, a transistor in isolation region is formed.
상기와 같은 본 발명의 반도체 소자의 형성 방법은 다음과 같은 효과가 있다.The method of forming the semiconductor device of the present invention as described above has the following effects.
첫째, 기본적으로 STI 방식을 이용하므로 활성 영역(active area)의 트랜지스터간의 격리는 취해지고, 또한, 격리 영역에 폴리 실리콘층을 매립하여 트랜지스터를 구성하므로 회로의 집적도를 높여 수율을 향상시킬 수 있다. 즉, 동일한 면적에 더 많은 트랜지스터를 형성할 수 있다.First, since the STI method is basically used, isolation between transistors in an active area is taken, and a transistor is formed by embedding a polysilicon layer in the isolation area, thereby increasing the degree of integration of the circuit and improving the yield. That is, more transistors can be formed in the same area.
둘째, STI 식각된 격리 영역에 트랜지스터와 활성 영역의 트랜지스터와의 격리 특성을 극대화할 수 있다.Second, the isolation characteristics of the transistors in the STI-etched isolation region and the transistors in the active region can be maximized.
격리 영역에 형성시킨 트랜지스터와 활성 영역에 형성시킨 트랜지스터와의 격리 특성이 향상될 수 있으므로, 기존의 격리 영역과 활성 영역의 계면에 발생하는 기생 성분(parasitic noise)으로 인한 트랜지스터의 동작 불량을 막을 수 있다.The isolation characteristics between the transistor formed in the isolation region and the transistor formed in the active region can be improved, thereby preventing malfunction of the transistor due to parasitic noise occurring at the interface between the existing isolation region and the active region. have.
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