CN109346568A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- CN109346568A CN109346568A CN201811149678.0A CN201811149678A CN109346568A CN 109346568 A CN109346568 A CN 109346568A CN 201811149678 A CN201811149678 A CN 201811149678A CN 109346568 A CN109346568 A CN 109346568A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
The invention discloses a kind of LED epitaxial slices and preparation method thereof, belong to technical field of semiconductors.The LED epitaxial slice includes substrate, n type semiconductor layer, stress release layer, active layer and p type semiconductor layer, and the n type semiconductor layer, the stress release layer, the active layer and the p type semiconductor layer stack gradually over the substrate；The stress release layer includes the multiple composite constructions stacked gradually, and each composite construction includes the first sublayer stacked gradually, the second sublayer, third sublayer and the 4th sublayer；The material of first sublayer uses undoped InGaN, and the material of second sublayer uses undoped aluminium nitride, and the material of the third sublayer uses silicon nitride, and the material of the 4th sublayer uses undoped gallium nitride.The present invention finally improves the photoelectric properties of LED.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and preparation method thereof.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.LED has many advantages, such as that high-efficient, the service life is long, small in size, low in energy consumption, can be applied to indoor and outdoor white-light illuminating, screen
The fields such as display, backlight.In the development of LED industry, gallium nitride (GaN) sill is V-III compound semiconductor
Typical Representative, the photoelectric properties for improving GaN base LED have become the key of semiconductor lighting industry.
Epitaxial wafer is the primary finished product in LED preparation process.Existing GaN base LED epitaxial wafer includes that substrate, N-type are partly led
Body layer, active layer and p type semiconductor layer, n type semiconductor layer, active layer and p type semiconductor layer stack gradually on substrate.Substrate
For providing growing surface for epitaxial material, n type semiconductor layer is used to provide the electronics for carrying out recombination luminescence, p type semiconductor layer
For providing the hole for carrying out recombination luminescence, the radiation recombination that active layer is used to carry out electrons and holes shines.
Active layer includes multiple well layer and multiple barrier layer, and multiple well layer and the alternately laminated setting of multiple barrier layer, barrier layer will be infused
The electrons and holes for entering active layer, which are limited in well layer, carries out recombination luminescence.The material of usual well layer uses the nitridation of high indium component
The material of indium gallium (InGaN), barrier layer uses gallium nitride (GaN).Since the lattice constant of gallium nitride is 3.181, the crystalline substance of indium nitride
Lattice constant is 3.538, therefore there are biggish lattice mismatch between well layer and barrier layer, the stress that lattice mismatch generates will affect electricity
Son and hole cause the luminous efficiency of LED lower in the combined efficiency in space.
It, generally can be before active layer growth, first in N-type semiconductor in order to alleviate the lattice mismatch between well layer and barrier layer
Growth stress releasing layer on layer, i.e. stress release layer are arranged between n type semiconductor layer and active layer.Stress release layer includes handing over
For multiple first sublayers and multiple second sublayers of stacking, the material of the first sublayer uses the InGaN (first of low indium component
Content of the content of indium component lower than indium component in well layer in sublayer), the material of the second sublayer using gallium nitride (the second sublayer
Material is as the material of barrier layer).Lattice Matching is preferable between first sublayer and the second sublayer, while the material of the first sublayer is adopted
With InGaN, growth quality is poor, so that the stress release of multiple first sublayers and multiple alternately laminated formation of second sublayer
Layer can discharge the stress that lattice mismatch generates between well layer and barrier layer in active layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The growth temperature of stress release layer is lower, and the stress release effect of stress release layer is better.But if stress is released
The growth temperature for putting layer is lower, then the carbon impurity that stress release layer introduces during the growth process is more, and carbon is miscellaneous in stress release layer
The content of matter is too high to will appear thyristor effect, at the same lower growth temperature will cause the crystal quality of stress release layer compared with
Difference reduces the antistatic effect of LED.Therefore, in order to avoid there is above-mentioned ill effect, the growth temperature of stress release layer is general
Higher (850 DEG C~870 DEG C), cause the stress release effect of stress release layer limited.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slices and preparation method thereof, are able to solve the prior art and answer
Power discharges the problem of layer growth temperature higher limit stresses releasing effect.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets
Substrate, n type semiconductor layer, stress release layer, active layer and p type semiconductor layer are included, the n type semiconductor layer, the stress are released
Layer, the active layer and the p type semiconductor layer is put to stack gradually over the substrate；The stress release layer includes successively layer
Folded multiple composite constructions, each composite construction include the first sublayer stacked gradually, the second sublayer, third sublayer and
Four sublayers；The material of first sublayer uses undoped InGaN, and the material of second sublayer is using undoped
Aluminium nitride, the material of the third sublayer use silicon nitride, and the material of the 4th sublayer uses undoped gallium nitride.
Optionally, the thickness of second sublayer is less than or equal to 5nm.
Optionally, the thickness of the third sublayer is less than or equal to 2nm.
Optionally, the quantity of the composite construction is 2~20.
Optionally, electron concentration is 10 in the 4th sublayer17cm-3~1019cm-3。
On the other hand, the embodiment of the invention provides a kind of preparation method of LED epitaxial slice, the preparation sides
Method includes:
One substrate is provided；
N type semiconductor layer, stress release layer, active layer and p type semiconductor layer are successively grown over the substrate；
Wherein, the stress release layer includes the multiple composite constructions stacked gradually, each composite construction include according to
The first sublayer, the second sublayer, third sublayer and the 4th sublayer of secondary stacking；The material of first sublayer uses undoped nitrogen
Change indium gallium, the material of second sublayer uses undoped aluminium nitride, and the material of the third sublayer uses silicon nitride, described
The material of 4th sublayer uses undoped gallium nitride.
Optionally, the growth temperature of the stress release layer is less than or equal to the growth temperature of the n type semiconductor layer.
Optionally, the growth temperature of second sublayer, the third sublayer and the 4th sublayer is all larger than or is equal to
The growth temperature of first sublayer described in the growth temperature of first sublayer is less than or equal to the growth temperature of second sublayer,
The growth temperature of first sublayer is less than or equal to the growth temperature of the third sublayer, the growth temperature of first sublayer
Less than or equal to the growth temperature of the 4th sublayer.
Optionally, the preparation method further include:
After each first sublayer growth, stop being passed through into the reaction chamber for growing first sublayer gallium source and
Indium source continues to be passed through ammonia into the reaction chamber for growing first sublayer, and first sublayer stops growing.
Optionally, the dormant duration of the first sublayer is less than or equal to 15s.
Technical solution provided in an embodiment of the present invention has the benefit that
By being sequentially inserted into aln layer and silicon nitride layer between the gallium indium nitride layer and gallium nitride layer of stress release layer,
Silicon atom can form Si-N covalent bond, discharge extra electronics fully in conjunction with the dangling bonds of nitrogen-atoms in silicon nitride layer,
Effectively improve the electron concentration in stress release layer；The potential barrier of aln layer is higher simultaneously, cooperates with gallium nitride layer, will nitrogenize
Silicon layer is clipped in the middle, and can effectively improve current expansion, so that the current expansion of stress release layer entirety is preferable.And stress is released
Put the good current expansion ability of layer can make up stress release layer growth temperature it is low brought by thyristor effect and antistatic
Ability decline, therefore the reduction (being reduced to 820 DEG C from 850 DEG C~870 DEG C) of stress release layer growth temperature may be implemented, it improves
The stress release effect of stress release layer, and then the crystal quality of active layer is improved, the final photoelectric properties for improving LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of stress release layer provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of the preparation method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slices.Fig. 1 is a kind of hair provided in an embodiment of the present invention
The structural schematic diagram of optical diode epitaxial wafer.Referring to Fig. 1, which includes substrate 10, n type semiconductor layer
20, stress release layer 30, active layer 40 and p type semiconductor layer 50, n type semiconductor layer 20, stress release layer 30,40 and of active layer
P type semiconductor layer 50 is sequentially laminated on substrate 10.
Fig. 2 is the structural schematic diagram of stress release layer provided in an embodiment of the present invention.Referring to fig. 2, in the present embodiment, it answers
Power releasing layer 30 includes multiple composite constructions for stacking gradually, and each composite construction includes the first sublayer 31 stacked gradually, the
Two sublayers 32, third sublayer 33 and the 4th sublayer 34.The material of first sublayer 31 uses undoped InGaN, the second sublayer
32 material uses undoped aluminium nitride, and the material of third sublayer 33 uses silicon nitride, and the material of the 4th sublayer 34 is not using
The gallium nitride of doping.
The embodiment of the present invention is by being sequentially inserted into aluminium nitride between the gallium indium nitride layer and gallium nitride layer of stress release layer
Layer and silicon nitride layer, silicon atom can be fully with the dangling bonds of nitrogen-atoms ining conjunction in silicon nitride layer, and formation Si-N covalent bond is released
Extra electronics is put, the electron concentration in stress release layer is effectively improved；The potential barrier of aln layer is higher simultaneously, with gallium nitride
Layer cooperation, silicon nitride layer is clipped in the middle, can effectively improve current expansion, so that the current expansion of stress release layer entirety
Preferably.And the good current expansion ability of stress release layer can make up the low brought thyristor of stress release layer growth temperature
Effect and antistatic effect decline, therefore the reduction that stress release layer growth temperature may be implemented (is reduced from 850 DEG C~870 DEG C
To 820 DEG C), the stress release effect of stress release layer is improved, and then improve the crystal quality of active layer, it is final to improve LED's
Photoelectric properties.In addition, active layer is arranged on the gallium nitride layer in composite construction, growth quality is preferable.
Optionally, the thickness of the first sublayer 31 can be 1nm~5nm, and the effect of preferably 1.5nm, stress release are preferable.
Optionally, the thickness of the second sublayer 32 can be less than or equal to 5nm, avoid influencing since the second sublayer is thicker
In electron injection active layer.
Preferably, the thickness of the second sublayer 32 can be 2nm.
Optionally, the thickness of third sublayer 33 can be to avoid causing since third sublayer is thicker less than or equal to 2nm
The crystal quality of stress release layer is too poor and influences the crystal quality of epitaxial wafer entirety.
Preferably, the thickness of third sublayer 33 can be 1nm.
Optionally, the thickness of the 4th sublayer 34 can be 20nm~60nm, preferably 40nm, proof stress releasing layer entirety
Crystal structure and crystal quality.
Optionally, the quantity of composite construction can be 2~20, preferably 3.
If the quantity of composite construction less than 2, may due to composite construction negligible amounts and can not be released effectively
The stress that lattice mismatch in active layer between well layer and barrier layer generates；It, may if the quantity of composite construction is greater than 20
Since the quantity of composite construction is more, increase the complexity of technique and the cost of production.
Optionally, electron concentration can be 10 in the 4th sublayer 3417cm-3~1019cm-3, preferably 1.8*1018cm-3, answer
The current expansion effect of power releasing layer is preferable.
Optionally, the content of indium component can be less than or equal to 3% in the first sublayer 31, avoid due to indium in the first sublayer
The content of component is higher and influences the crystal quality of epitaxial wafer entirety.
Preferably, the content of indium component can be 1.5% in the first sublayer 31.
Specifically, the material of substrate 10 can use sapphire (main material is aluminum oxide), silicon or silicon carbide.
The material of n type semiconductor layer 20 can use the gallium nitride of n-type doping (such as silicon or germanium).Active layer 40 may include multiple quantum
Trap and multiple quantum are built, and multiple Quantum Well and multiple quantum build alternately laminated setting；The material of Quantum Well can use indium nitride
Gallium (InGaN), such as InxGa1-xN, 0 < x < 1, the material that quantum is built can use gallium nitride.The material of p type semiconductor layer 50 can
Using the gallium nitride of p-type doping (such as magnesium).
Further, the thickness of n type semiconductor layer 20 can be 1 μm~5 μm, preferably 3 μm；N in n type semiconductor layer 20
The doping concentration of type dopant can be 1018cm-3~9*1019cm-3, preferably 1019cm-3.The thickness of Quantum Well can be
2.5nm~3.5nm, preferably 3nm；The thickness that quantum is built can be 9nm~13nm, preferably 11nm；The quantity of Quantum Well with
The quantity that quantum is built is identical, and the quantity that quantum is built can be 10~15, preferably 12.The thickness of p type semiconductor layer 50
It can be 100nm~300nm, preferably 200nm；The doping concentration of P-type dopant can be 10 in p type semiconductor layer 5018/
cm3~1020/cm3, preferably 1019/cm3。
In practical applications, it can be equipped with graphical silicon dioxide layer on substrate 10, on the one hand reduce GaN epitaxy material
On the other hand dislocation density changes the shooting angle of light, improves the extraction efficiency of light.Specifically, it can first be served as a contrast in sapphire
Layer of silicon dioxide material is laid on bottom；Form the photoresist of certain figure on earth silicon material using photoetching technique again；
Then the earth silicon material of not photoresist overlay, the earth silicon material formation figure left are removed using dry etching technology
Shape silicon dioxide layer；Finally remove photoresist.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include buffer layer 61, the setting of buffer layer 61 exists
Between substrate 10 and n type semiconductor layer 20, to alleviate the stress and defect that lattice mismatch generates between substrate material and gallium nitride,
And nuclearing centre is provided for gallium nitride material epitaxial growth.
Specifically, the material of buffer layer 61 can use gallium nitride or aluminium nitride.
Further, the thickness of buffer layer 61 can be 15nm~35nm, preferably 25nm.
Preferably, undoped as shown in Figure 1, the LED epitaxial slice can also include undoped gallium nitride layer 62
Gallium nitride layer 62 is arranged between buffer layer 61 and n type semiconductor layer 20, further to alleviate between substrate material and gallium nitride
The stress and defect that lattice mismatch generates, provide crystal quality preferable growing surface for epitaxial wafer main structure.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy first in patterned substrate, because
This is also referred to as low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again, will form multiple mutually independent three
Island structure is tieed up, referred to as three-dimensional nucleating layer；Then it is carried out between each three-dimensional island structure on all three-dimensional island structures
The cross growth of gallium nitride forms two-dimension plane structure, referred to as two-dimentional retrieving layer；The finally high growth temperature one on two-dimensional growth layer
The thicker gallium nitride of layer, referred to as intrinsic gallium nitride layer.By three-dimensional nucleating layer, two-dimentional retrieving layer and intrinsic gallium nitride in the present embodiment
Layer is referred to as undoped gallium nitride layer.
Further, the thickness of undoped gallium nitride layer 62 can be 1 μm~3 μm, preferably 2 μm.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include electronic barrier layer 71, electronic barrier layer
71 are arranged between active layer 40 and p type semiconductor layer 50, carry out into p type semiconductor layer with hole to avoid electron transition non-
Radiation recombination reduces the luminous efficiency of LED.
Specifically, the material of electronic barrier layer 71 can be using the aluminium gallium nitride alloy (AlGaN) of p-type doping, such as AlyGa1-yN,
0.1 < y < 0.5.
Further, the thickness of electronic barrier layer 71 can be 50nm~150nm, preferably 100nm.
Preferably, as shown in Figure 1, the LED epitaxial slice can also include low temperature P-type layer 72, low temperature P-type layer 72
It is arranged between active layer 40 and electronic barrier layer 71, is caused in active layer to avoid the higher growth temperature of electronic barrier layer
Phosphide atom is precipitated, and influences the luminous efficiency of light emitting diode.
Specifically, the material of low temperature P-type layer 72 can be identical as the material of p type semiconductor layer 50.In the present embodiment,
The material of low temperature P-type layer 72 can be the gallium nitride of p-type doping.
Further, the thickness of low temperature P-type layer 72 can be 10nm~50nm, preferably 30nm；P in low temperature P-type layer 72
The doping concentration of type dopant can be 1018/cm3~1020/cm3, preferably 1019/cm3。
Optionally, as shown in Figure 1, the LED epitaxial slice can also include contact layer 80, contact layer 80 is arranged in P
In type semiconductor layer 50, to form Ohmic contact between the electrode or transparent conductive film that are formed in chip fabrication technique.
Specifically, the material of contact layer 80 can be using the InGaN or gallium nitride of p-type doping.
Further, the thickness of contact layer 80 can be 5nm~300nm, preferably 100nm；P-type is adulterated in contact layer 80
The doping concentration of agent can be 1021/cm3~1022/cm3, preferably 5*1021/cm3。
The embodiment of the invention provides a kind of preparation method of LED epitaxial slice, it is suitable for preparing shown in FIG. 1
LED epitaxial slice.Fig. 3 is a kind of process of the preparation method of LED epitaxial slice provided in an embodiment of the present invention
Figure.Referring to Fig. 3, which includes:
Step 201: a substrate is provided.
Optionally, which may include:
Clean the surface of substrate.
Specifically, the surface for cleaning substrate may include:
Controlled at 1110 DEG C, 8~10 minutes annealings are carried out to substrate in hydrogen atmosphere.
Step 202: successively growing n type semiconductor layer, stress release layer, active layer and p type semiconductor layer on substrate.
In the present embodiment, stress release layer includes the multiple composite constructions stacked gradually, each composite construction include according to
The first sublayer, the second sublayer, third sublayer and the 4th sublayer of secondary stacking；The material of first sublayer uses undoped indium nitride
Gallium, the material of the second sublayer use undoped aluminium nitride, and the material of third sublayer uses silicon nitride, and the material of the 4th sublayer is adopted
With undoped gallium nitride.
Optionally, the growth temperature of stress release layer can be less than or equal to the growth temperature of n type semiconductor layer.Stress is released
The growth temperature for putting layer is lower, is conducive to discharge the stress that the lattice mismatch in active layer between well layer and barrier layer generates, improves
The crystal quality of active layer improves the photoelectric properties of LED.
It should be noted that when at least two layers in the first sublayer, the second sublayer, third sublayer and the 4th sublayer of growth temperature
Degree is different, then the growth temperature that the growth temperature of stress release layer is less than or equal to n type semiconductor layer refers to, the first sublayer, the
The growth temperature of two sublayers, third sublayer and the 4th sublayer be respectively less than or equal to n type semiconductor layer growth temperature, i.e., first son
The growth temperature of layer be respectively less than or equal to n type semiconductor layer growth temperature, the growth temperature of the second sublayer is respectively less than or is equal to N
The growth temperature of type semiconductor layer, the growth temperature of third sublayer be respectively less than or equal to n type semiconductor layer growth temperature, the 4th
The growth temperature of sublayer be respectively less than or equal to n type semiconductor layer growth temperature.
Optionally, the growth temperature of the second sublayer, third sublayer and the 4th sublayer can be all larger than or be equal to the first sublayer
Growth temperature, i.e., the growth temperature of the first sublayer be less than or equal to the second sublayer growth temperature, the growth temperature of the first sublayer
Degree is less than or equal to the growth temperature of third sublayer, and the growth temperature of the first sublayer is less than or equal to the growth temperature of the 4th sublayer
Degree.The growth temperature of first sublayer is lower, and the indium in the first sublayer can be caused to parse to avoid high growth temperature.
Specifically, the growth temperature of the first sublayer can be 820 DEG C~840 DEG C, and the growth temperature of the second sublayer can be
820 DEG C~840 DEG C, the growth temperature of third sublayer can be 820 DEG C~840 DEG C, and the growth temperature of the 4th sublayer can be 820
DEG C~840 DEG C.
Correspondingly, the growth pressure of the first sublayer can be 100torr~500torr, and the growth pressure of the second sublayer can
Think that 100torr~500torr, the growth pressure of third sublayer can be 100torr~500torr, the growth of the 4th sublayer
Temperature can be 100torr~500torr.
Optionally, which can also include:
After the growth of each first sublayer, stops being passed through gallium source and indium source into the reaction chamber of one sublayer of growth regulation, hold
Continue and be passed through ammonia into the reaction chamber of one sublayer of growth regulation, the first sublayer stops growing.
The phosphide atom volatilization for accumulating the first sub-layer surface by interruption, avoids phosphide atom from being diffused into subsequent growth
In semiconductor layer, the crystal quality of the interface of the semiconductor layer of the first sublayer and subsequent growth is improved.
Preferably, the dormant duration of the first sublayer can be less than or equal to 15s, avoid the dormant time longer
And influence the production efficiency of epitaxial wafer entirety；
It is highly preferred that the dormant duration of the first sublayer can be 8s, it is former in the indium for guaranteeing the accumulation of the first sub-layer surface
In the case where sub sufficiently volatilization, the production efficiency of epitaxial wafer entirety is taken into account.
Specifically, which may include:
The first step, controlled at 1050 DEG C~1100 DEG C (preferably 1080 DEG C), pressure is 100torr~500torr
(preferably 300torr), grows n type semiconductor layer on substrate；
Second step, the growth stress releasing layer on n type semiconductor layer；
Third step grows active layer on stress release layer；Wherein, the growth temperature of Quantum Well is 780 DEG C~820 DEG C
(preferably 800 DEG C), pressure are 100torr~500torr (preferably 300torr)；Quantum build growth temperature be 900 DEG C~
950 DEG C (preferably 930 DEG C), pressure is 100torr~500torr (preferably 300torr)；
4th step, controlled at 850 DEG C~1080 DEG C (preferably 960 DEG C), pressure is that 100torr~300torr is (excellent
It is selected as 200torr), the growing P-type semiconductor layer on active layer.
Optionally, before the first step, which can also include:
Buffer layer is formed on the substrate.
Correspondingly, n type semiconductor layer is grown on the buffer layer.
Specifically, buffer layer is formed on the substrate, may include:
Using physical vapour deposition (PVD) (English: Physical Vapor Deposition, abbreviation: PVD), technology is on substrate
Form buffer layer.
Preferably, on substrate after grown buffer layer, which can also include:
Undoped gallium nitride layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on undoped gallium nitride layer.
Specifically, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), pressure be 100torr~500torr (preferably
300torr), undoped gallium nitride layer is grown on the buffer layer.
Optionally, before the 4th step, which can also include:
Electronic barrier layer is grown on active layer.
Correspondingly, p type semiconductor layer is grown on electronic barrier layer.
Specifically, electronic barrier layer is grown on active layer, may include:
Controlled at 850 DEG C~1080 DEG C (preferably 960 DEG C), pressure be 200torr~500torr (preferably
350torr), electronic barrier layer is grown on active layer.
Preferably, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer.
Correspondingly, electronic barrier layer is grown in low temperature P-type layer.
Specifically, the growing low temperature P-type layer on active layer may include:
Controlled at 600 DEG C~850 DEG C (preferably 750 DEG C), pressure be 100torr~600torr (preferably
300torr), the growing low temperature P-type layer on active layer.
Optionally, after the 4th step, which can also include:
Contact layer is grown on p type semiconductor layer.
Specifically, contact layer is grown on p type semiconductor layer, may include:
Controlled at 850 DEG C~1050 DEG C (preferably 950 DEG C), pressure be 100torr~300torr (preferably
200torr), contact layer is grown on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 650 DEG C~850 DEG C (preferably
It is 750 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again
The temperature of epitaxial wafer is reduced to room temperature.
Control temperature, pressure each mean temperature, pressure in the reaction chamber of control growth epitaxial wafer, and specially metal is organic
Compound chemical gaseous phase deposition (English: Metal-organic Chemical Vapor Deposition, referred to as: MOCVD) set
Standby reaction chamber.Using trimethyl gallium or triethyl-gallium as gallium source when realization, high-purity ammonia is as nitrogen source, and trimethyl indium is as indium
Source, for trimethyl aluminium as silicon source, N type dopant selects silane, and P-type dopant selects two luxuriant magnesium.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, n type semiconductor layer, stress release
Layer, active layer and p type semiconductor layer, the n type semiconductor layer, the stress release layer, the active layer and the p-type are partly led
Body layer stacks gradually over the substrate；It is characterized in that, the stress release layer includes the multiple composite constructions stacked gradually,
Each composite construction includes the first sublayer stacked gradually, the second sublayer, third sublayer and the 4th sublayer；First son
The material of layer uses undoped InGaN, and the material of second sublayer uses undoped aluminium nitride, third
The material of layer uses silicon nitride, and the material of the 4th sublayer uses undoped gallium nitride.
2. LED epitaxial slice according to claim 1, which is characterized in that the thickness of second sublayer be less than or
Equal to 5nm.
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that the thickness of the third sublayer is small
In or equal to 2nm.
4. LED epitaxial slice according to claim 1 or 2, which is characterized in that the quantity of the composite construction is 2
It is a~20.
5. LED epitaxial slice according to claim 1 or 2, which is characterized in that electronics is dense in the 4th sublayer
Degree is 1017cm-3~1019cm-3。
6. a kind of preparation method of LED epitaxial slice, which is characterized in that the preparation method includes:
One substrate is provided；
N type semiconductor layer, stress release layer, active layer and p type semiconductor layer are successively grown over the substrate；
Wherein, the stress release layer includes the multiple composite constructions stacked gradually, and each composite construction includes successively layer
Folded the first sublayer, the second sublayer, third sublayer and the 4th sublayer；The material of first sublayer uses undoped indium nitride
Gallium, the material of second sublayer use undoped aluminium nitride, and the material of the third sublayer uses silicon nitride, and the described 4th
The material of sublayer uses undoped gallium nitride.
7. preparation method according to claim 6, which is characterized in that the growth temperature of the stress release layer is less than or waits
In the growth temperature of the n type semiconductor layer.
8. preparation method according to claim 6 or 7, which is characterized in that second sublayer, the third sublayer and institute
The growth temperature for stating the 4th sublayer be all larger than or the growth temperature equal to first sublayer described in the first sublayer growth temperature
Less than or equal to the growth temperature of second sublayer, the growth temperature of first sublayer is less than or equal to the third sublayer
Growth temperature, the growth temperature of first sublayer is less than or equal to the growth temperature of the 4th sublayer.
9. preparation method according to claim 6 or 7, which is characterized in that the preparation method further include:
After each first sublayer growth, stop being passed through gallium source and indium into the reaction chamber for growing first sublayer
Source continues to be passed through ammonia into the reaction chamber for growing first sublayer, and first sublayer stops growing.
10. preparation method according to claim 9, which is characterized in that the dormant duration of the first sublayer is less than
Or it is equal to 15s.
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