CN109065679A - A kind of LED epitaxial slice and its manufacturing method - Google Patents
A kind of LED epitaxial slice and its manufacturing method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
Abstract
The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Epitaxial wafer includes substrate and stacks gradually buffer layer, n type semiconductor layer, active layer and p type semiconductor layer on substrate, active layer includes the multiple composite constructions stacked gradually, each composite construction includes the well layer stacked gradually, cap rock and barrier layer, the material of the well layer is InGaN, the material of the barrier layer is GaN, and the material of the cap rock is BxGa1‑xN, 0 < x < 1.The present invention between InGaN and GaN by being inserted into one layer of BGaN, it can prevent the precipitation of In, simultaneously because the size of B atom is smaller, BGaN can provide tensile stress, improve the lattice mismatch between InGaN and GaN, it reduces due to InGaN and GaN lattice mismatch bring piezoelectric polarization fields, improves the luminous efficiency of LED.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its manufacturing method.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.As a kind of New Solid lighting source efficiently, environmentally friendly, green, LED is widely used in rapidly traffic
The fields such as signal lamp, automobile interior exterior lamp, landscape light in city, cell phone back light source.
Epitaxial wafer is the semiconductive thin film to grow out on the matched monocrystal material of crystal structure.Work is carried out to epitaxial wafer
Skill processing can form chip, be light emitting diode after chip package.Existing LED epitaxial wafer includes substrate, buffer layer, N
Type semiconductor layer, active layer and p type semiconductor layer, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer stack gradually
On substrate.P type semiconductor layer is used to provide the hole for carrying out recombination luminescence, and n type semiconductor layer carries out compound hair for providing
The electronics of light, the radiation recombination that active layer is used to carry out electrons and holes shine, and substrate is used to provide growth table for epitaxial material
Face；The material of substrate generally selects sapphire, and the material of n type semiconductor layer etc. generally selects gallium nitride, sapphire and gallium nitride
For dissimilar materials, there is biggish lattice mismatch between the two, buffer layer is used to alleviate the crystalline substance between substrate and n type semiconductor layer
Lattice mismatch.
Specifically, active layer includes the multiple composite constructions stacked gradually, and each composite construction includes stacking gradually
Well layer, cap rock and barrier layer.Electrons and holes are limited in progress recombination radiation in well layer and shone by barrier layer.The material of well layer uses nitrogen
Change indium gallium, is precipitated since high temperature will cause indium from well layer, the growth temperature of well layer is lower.And the material of barrier layer uses nitrogen
Change gallium, in order to guarantee the crystal quality of barrier layer, the growth temperature of barrier layer is higher.The growth temperature of cap rock and the growth temperature of well layer
It is identical, well layer can be influenced to avoid the high growth temperature of barrier layer, the indium in turn resulted in well layer is precipitated；The material of cap rock is adopted simultaneously
It is preferable with the crystal match degree of barrier layer with gallium nitride.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The material of well layer uses InGaN, and the material of cap rock and barrier layer is all made of gallium nitride, due to the lattice of gallium nitride
Constant is 3.181 angstroms, and the lattice constant of indium nitride is 3.538 angstroms, therefore the lattice of the lattice constant of InGaN and gallium nitride
Had differences between constant, the intersection of InGaN and gallium nitride will form biggish piezoelectric polarization effect, influence electronics and
Hole causes the luminous efficiency of LED lower in the combined efficiency in space.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slice and its manufacturing methods, are able to solve prior art nitrogen
The problem that change indium gallium and gallium nitride crystal lattice mismatch cause the luminous efficiency of LED lower.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets
Include substrate, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer, it is the buffer layer, the n type semiconductor layer, described
Active layer and the p type semiconductor layer stack gradually over the substrate；The active layer include stack gradually it is multiple compound
Structure, each composite construction include the well layer stacked gradually, cap rock and barrier layer, and the material of the well layer is InGaN, described
The material of barrier layer is GaN, and the material of the cap rock is BxGa1-xN, 0 < x < 1.
Optionally, the cap rock with a thickness of 1nm~2nm.
Preferably, the well layer with a thickness of 3nm~8nm.
Preferably, the barrier layer with a thickness of 8nm~15nm.
Optionally, the quantity of the composite construction is 5~10.
Optionally, x is gradually reduced along the stacking direction of the cap rock.
On the other hand, the embodiment of the invention provides a kind of manufacturing method of LED epitaxial slice, the manufacturers
Method includes:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate；
Wherein, the active layer includes the multiple composite constructions stacked gradually, and the composite construction includes stacking gradually
Well layer, cap rock and barrier layer, the material of the well layer are InGaN, and the material of the barrier layer is GaN, and the material of the cap rock is
BxGa1-xN, 0 < x < 1.
Optionally, the growth pressure of the cap rock is less than or equal to 100torr.
Preferably, the growth pressure of the well layer is 150torr~300torr.
Preferably, the growth pressure of the barrier layer is 150torr~300torr.
Technical solution provided in an embodiment of the present invention has the benefit that
By being inserted into one layer of BGaN between InGaN and GaN, the precipitation of In can be prevented, simultaneously because the size of B atom
Smaller, BGaN can provide tensile stress, improve the lattice mismatch between InGaN and GaN, make the interface of InGaN and GaN due to
The reduction of defect and be more clear, reduce due to InGaN and GaN lattice mismatch bring piezoelectric polarization fields, increase electronics and sky
The combined efficiency in cave improves the luminous efficiency of LED.And the forbidden bandwidth of BN is similar with AlN, is inserted between InGaN and GaN
One layer of BGaN, the intersection being equivalent in InGaN and GaN introduce a biggish conduction band band rank, draw high energy band, can effectively prevent
Only electronics overflow further increases the combined efficiency of electrons and holes, improves the luminous efficiency of LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slice, Fig. 1 is a kind of hair provided in an embodiment of the present invention
The structural schematic diagram of optical diode epitaxial wafer, referring to Fig. 1, which includes substrate 1, buffer layer 2, N-type half
Conductor layer 3, active layer 4 and p type semiconductor layer 5, buffer layer 2, n type semiconductor layer 3, active layer 4 and p type semiconductor layer 5 are successively
It is layered on substrate 1.
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention, and referring to fig. 2, active layer 4 includes stacking gradually
Multiple composite constructions 40, each composite construction 40 includes the well layer 41, cap rock 42 and the barrier layer 43 that stack gradually.The material of well layer 41
Material is InGaN, and the material of barrier layer 43 is GaN, and the material of cap rock 42 is BxGa1-xN, 0 < x < 1.
The embodiment of the present invention can prevent the precipitation of In by being inserted into one layer of BGaN between InGaN and GaN, while by
Smaller in the size of B atom, BGaN can provide tensile stress, improve the lattice mismatch between InGaN and GaN, make InGaN and
The interface of GaN due to defect reduction and be more clear, reduce due to InGaN and GaN lattice mismatch bring piezoelectric polarization
, increase the combined efficiency of electrons and holes, improves the luminous efficiency of LED.And the forbidden bandwidth of BN is similar with AlN,
One layer of BGaN is inserted between InGaN and GaN, the intersection being equivalent in InGaN and GaN introduces a biggish conduction band band rank,
Energy band is drawn high, electronics overflow can be effectively prevented, further increases the combined efficiency of electrons and holes, improves the luminous effect of LED
Rate.And the forbidden bandwidth of BN is similar with AlN, and one layer of BGaN is inserted between InGaN and GaN, is equivalent in InGaN and GaN
Intersection introduce a biggish conduction band band rank, draw high energy band, electronics overflow can be effectively prevented, further increase electronics and
The combined efficiency in hole improves the luminous efficiency of LED.
Optionally, the thickness of cap rock 42 can be 1nm~2nm.
If the thickness of cap rock is less than 1nm, cap rock may be caused not have lattice since the thickness of cap rock is too small
The effect matched；If the thickness of cap rock is greater than 2nm, may be caused between well layer and barrier layer greatly very much to the thickness due to cap rock
Energy band it is too high, cap rock will affect carrier and normally migrate, and plays barrier effect to the compound of electrons and holes, reduces LED
Luminous efficiency.
Preferably, the thickness of cap rock 42 can be 1.5nm, and cap rock can be effectively improved the crystalline substance between InGaN and GaN at this time
Lattice mismatch increases the combined efficiency of electrons and holes, improves the luminous efficiency of LED, while it is normal to influence carrier
Migration, the luminous efficiency of LED reaches best.
Preferably, the thickness of well layer 41 can be 3nm~8nm.
If the thickness of well layer is less than 3nm, electronics and sky in well layer may be influenced since the thickness of well layer is too small
The recombination luminescence in cave reduces the luminous efficiency of LED；If the thickness of well layer is greater than 8nm, may be too big due to the thickness of well layer
And cause the lattice mismatch between well layer and barrier layer more serious, need to increase accordingly the thickness of cap rock, the biggish cap rock of thickness is very
It is easy to influence carrier and normally migrate, barrier effect is played to the compound of electrons and holes, reduces the luminous efficiency of LED.
Preferably, the thickness of barrier layer 43 can be 8nm~15nm.
If the thickness of barrier layer is less than 8nm, the crystal of active layer entirety may be caused since the thickness of barrier layer is too small
Quality improvement is poor, and the thickness for needing to increase accordingly cap rock and the thickness for reducing well layer go to improve the crystal matter of active layer
Amount, to influence the recombination luminescence of electrons and holes in well layer, reduces the luminous efficiency of LED；If the thickness of barrier layer is greater than
15nm then may cause the lattice mismatch between well layer and barrier layer more serious, need accordingly to increase since the thickness of barrier layer is too big
The thickness of big cap rock, the biggish cap rock of thickness, which is easy to influence carrier, normally to be migrated, to compound of electrons and holes
To barrier effect, the luminous efficiency of LED is reduced.
Optionally, the quantity of composite construction 40 can be 5~10.
If the quantity of composite construction less than 5, may make electronics and sky since the quantity of composite construction is very little
Cave does not carry out sufficient recombination luminescence, leads to the luminous efficiency for reducing LED；If the quantity of composite construction is greater than 10,
Since the quantity of composite construction is too many distribution of electrons and holes may not be concentrated, the combined efficiencies of electrons and holes compared with
It is low, cause the luminous efficiency of LED lower.
Optionally, x can be gradually reduced along the stacking direction of cap rock 42, and cap rock is shared by the B component in the part of well layer
Ratio it is higher, can defect to be generated in effective compensation InGaN crystal growth, while cap rock Ga group in the part of barrier layer
Ratio shared by point is higher, and the Lattice Matching with GaN crystal may be implemented.
Specifically, the material of substrate 1 can use sapphire.The material of buffer layer 2 can use aluminium nitride or nitridation
Gallium.The material of n type semiconductor layer 3 can use the gallium nitride of n-type doping (such as silicon).The material of p type semiconductor layer 5 can use
P-type adulterates the gallium nitride of (such as magnesium).
Further, the thickness of buffer layer 2 can be 5nm~40nm, preferably 25nm.The thickness of n type semiconductor layer 3 can
Think 1.5 μm~3.5 μm, preferably 2 μm；The doping concentration of N type dopant can be 10 in n type semiconductor layer 319cm-3~
1020cm-3, preferably 1.5*1019cm-3.The thickness of p type semiconductor layer 5 can be 8nm~50nm, preferably 15nm；P-type is partly led
The doping concentration of P-type dopant can be 10 in body layer 519cm-3~8*1020cm-3, preferably 1020cm-3。
Optionally, as shown in Figure 1, the LED epitaxial slice can also include undoped gallium nitride layer 6, undoped with nitrogen
Change gallium layer 6 to be arranged between buffer layer 2 and n type semiconductor layer 3, further to alleviate the crystalline substance between substrate and n type semiconductor layer
Lattice mismatch improves the crystal quality of epitaxial wafer entirety, and then improves the luminous efficiency of LED.
Further, the thickness of undoped gallium nitride layer 6 can be 1 μm~2 μm, preferably 1 μm.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy on substrate first, therefore also referred to as
For low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again will form multiple mutually independent three-dimensional islands
Structure, referred to as three-dimensional nucleating layer；Then gallium nitride is carried out between each three-dimensional island structure on all three-dimensional island structures
Cross growth, form two-dimension plane structure, referred to as two-dimentional retrieving layer；It is finally one layer of high growth temperature thicker on two-dimensional growth layer
Gallium nitride, referred to as high temperature buffer layer.Three-dimensional nucleating layer, two-dimentional retrieving layer and high temperature buffer layer are referred to as not in the present embodiment
Doped gallium nitride layer.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include electronic barrier layer 7, electronic barrier layer 7
It is arranged between active layer 4 and p type semiconductor layer 5, is carried out into p type semiconductor layer with hole to avoid electron transition non-radiative
It is compound, influence the luminous efficiency of LED.
Specifically, the material of electronic barrier layer 7 can be using the aluminium gallium nitride alloy (AlGaN) of p-type doping.
Further, the thickness of electronic barrier layer 7 can be 20nm~100nm, preferably 25nm.
Preferably, as shown in Figure 1, the LED epitaxial slice can also include low temperature P-type layer 8, low temperature P-type layer 8 is set
It sets between active layer 4 and electronic barrier layer 7, to alleviate influence of the p type semiconductor layer high growth temperature to active layer.
Specifically, the material of low temperature P-type layer 8 can be using the gallium nitride of p-type doping.
Further, the thickness of low temperature P-type layer 8 can be 20nm~100nm, preferably 30nm；P-type in low temperature P-type layer 8
The doping concentration of dopant can be 1019cm-3~8*1020cm-3, preferably 1020cm-3。
Optionally, as shown in Figure 1, the LED epitaxial slice can also include p-type contact layer 9, p-type contact layer 9 is set
It sets on p type semiconductor layer 5, realizes between the electrode or transparent conductive film formed in epitaxial wafer and chip fabrication processes
Ohmic contact.
Specifically, the material of p-type contact layer 9 can be using the gallium nitride of p-type doping.
Further, the thickness of p-type contact layer 9 can be 1nm~2nm, preferably 1.5nm；P-type is mixed in p-type contact layer 9
Miscellaneous dose of doping concentration can be 1019cm-3~8*1020cm-3, preferably 3*1020cm-3。
The embodiment of the invention provides a kind of manufacturing method of LED epitaxial slice, it is suitable for manufacturing shown in FIG. 1
LED epitaxial slice.Fig. 3 is a kind of process of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention
Figure, referring to Fig. 3, which includes:
Step 201: a substrate is provided.
Optionally, which may include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), pressure be 200torr~500torr (preferably
350torr), substrate 5 minutes~20 minutes (preferably 12 minutes) are handled in hydrogen atmosphere high temperature；
Nitrogen treatment is carried out to substrate.
Step 202: successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer on substrate.
Wherein, active layer includes the multiple composite constructions stacked gradually, and composite construction includes the well layer stacked gradually, cap rock
And barrier layer, the material of well layer are InGaN, the material of barrier layer is GaN, and the material of cap rock is BxGa1-xN, 0 < x < 1.
Specifically, can be using trimethyl borine, triethyl-gallium as raw material when growing cap rock, nitrogen is carrier gas.
Optionally, the growth pressure of cap rock can be less than or equal to 100torr, improve the growth quality of cap rock, obtain crystalline substance
The preferable cap rock of weight.
Preferably, the growth pressure of cap rock can be 20torr.It is experimentally confirmed that the crystal quality of the cap rock grown at this time reaches
To best.
Preferably, the growth pressure of well layer can be 150torr~300torr, and the uniformity of well layer is preferable.
Preferably, the growth pressure of barrier layer can be 150torr~300torr, and the uniformity of barrier layer is preferable.
Optionally, the growth temperature of cap rock can be identical as the growth temperature of well layer, to be protected using cap rock to well layer
Shield, effectively prevent the high growth temperature of barrier layer that the In in well layer is caused to be precipitated.
Preferably, the growth temperature of well layer can be 700 DEG C~820 DEG C.
If the growth temperature of well layer is lower than 700 DEG C, well layer may be caused since the growth temperature of well layer is too low
Growth quality is too poor, and the well layer of growth quality difference can have negatively influencing to the combined efficiency of electrons and holes, causes the luminous effect of LED
Rate reduces；If the growth temperature of well layer is higher than 820 DEG C, may be caused in well layer since the growth temperature of well layer is too high
Indium is precipitated, and equally can have negatively influencing to the combined efficiency of electrons and holes, the luminous efficiency of LED is caused to reduce.
Correspondingly, the growth temperature of cap rock can be 700 DEG C~820 DEG C, be precipitated with the indium effectivelying prevent in well layer.
Optionally, the growth temperature of barrier layer can be 840 DEG C~900 DEG C.
If the growth temperature of barrier layer is lower than 840 DEG C, barrier layer may be caused since the growth temperature of barrier layer is too low
Growth quality is poor, and the barrier layer of growth quality difference will affect the crystal quality of active layer entirety, in the active layer of crystal quality difference
The combined efficiency of electrons and holes is lower, and the luminous efficiency in turn resulting in LED is lower；If the growth temperature of barrier layer is higher than 900
DEG C, then well layer may be influenced since the growth temperature of barrier layer is too high, the indium in well layer is caused to be precipitated, it equally also can be to electronics
There is negatively influencing with the combined efficiency in hole, causes the luminous efficiency of LED lower.
Specifically, which may include:
The first step, using physical vapour deposition (PVD) (English: Physical Vapor Deposition, abbreviation: PVD) technology
Buffer layer is formed on the substrate；
Second step, controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure is 200torr~300torr
(preferably 250torr), grows n type semiconductor layer on the buffer layer；
Third step grows active layer on n type semiconductor layer；
4th step, controlled at 750 DEG C~1050 DEG C (preferably 980 DEG C), pressure is that 100torr~600torr is (excellent
It is selected as 350torr), the growing P-type semiconductor layer on active layer.
Optionally, before second step, which can also include:
Undoped gallium nitride layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on undoped gallium nitride layer.
Specifically, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 800 DEG C~1180 DEG C (preferably 1040 DEG C), pressure be 120torr~600torr (preferably
360torr), undoped gallium nitride layer is grown on the buffer layer.
Optionally, before the 4th step, which can also include:
Electronic barrier layer is grown on active layer.
Correspondingly, p type semiconductor layer is grown on electronic barrier layer.
Specifically, electronic barrier layer is grown on active layer, may include:
Controlled at 900 DEG C~1000 DEG C (preferably 950 DEG C), pressure be 100torr~600torr (preferably
350torr), electronic barrier layer is grown on active layer.
Preferably, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer.
Correspondingly, electronic barrier layer is grown in low temperature P-type layer.
Specifically, the growing low temperature P-type layer on active layer may include:
Controlled at 700 DEG C~900 DEG C (preferably 800 DEG C), pressure be 150torr~250torr (preferably
200torr), the growing low temperature P-type layer on active layer.
Optionally, after the 4th step, which can also include:
The growing P-type contact layer on p type semiconductor layer.
Specifically, the growing P-type contact layer on p type semiconductor layer may include:
Controlled at 700 DEG C~800 DEG C (preferably 750 DEG C), pressure be 300torr~600torr (preferably
450torr), the growing P-type contact layer on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 500 DEG C~900 DEG C (preferably
It is 800 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again
The temperature of epitaxial wafer is reduced to room temperature, terminates epitaxy technique growth.
Control temperature, pressure each mean temperature, pressure, such as model in the reaction chamber of control growth epitaxial wafer
Metallo-organic compound chemical gaseous phase deposition (the English: Metal Organic Chemical Vapor of VeecoK465i C4
Deposition, referred to as: MOCVD) temperature, the pressure in equipment.With high-purity hydrogen or high pure nitrogen or hydrogen when realization
The mixed gas of gas and nitrogen is as carrier gas, and high-purity ammonia is as nitrogen source, trimethyl gallium or triethyl-gallium as gallium source, trimethyl
Indium is as indium source, and trimethyl aluminium is as silicon source, and silane is as N type dopant, and two luxuriant magnesium are as P-type dopant.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, buffer layer, n type semiconductor layer, has
Active layer and p type semiconductor layer, the buffer layer, the n type semiconductor layer, the active layer and the p type semiconductor layer are successively
Stacking is over the substrate；The active layer includes the multiple composite constructions stacked gradually, each composite construction include according to
Well layer, cap rock and the barrier layer of secondary stacking, the material of the well layer are InGaN, and the material of the barrier layer is GaN, which is characterized in that
The material of the cap rock is BxGa1-xN, 0 < x < 1.
2. LED epitaxial slice according to claim 1, which is characterized in that the cap rock with a thickness of 1nm~
2nm。
3. LED epitaxial slice according to claim 2, which is characterized in that the well layer with a thickness of 3nm~
8nm。
4. LED epitaxial slice according to claim 2 or 3, which is characterized in that the barrier layer with a thickness of 8nm~
15nm。
5. described in any item LED epitaxial slices according to claim 1~3, which is characterized in that the composite construction
Quantity is 5~10.
6. described in any item LED epitaxial slices according to claim 1~3, which is characterized in that layer of the x along the cap rock
Folded direction is gradually reduced.
7. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate；
Wherein, the active layer includes the multiple composite constructions stacked gradually, the composite construction include the well layer stacked gradually,
Cap rock and barrier layer, the material of the well layer are InGaN, and the material of the barrier layer is GaN, and the material of the cap rock is BxGa1-xN,
0 < x < 1.
8. manufacturing method according to claim 7, which is characterized in that the growth pressure of the cap rock is less than or equal to
100torr。
9. manufacturing method according to claim 8, which is characterized in that the growth pressure of the well layer be 150torr~
300torr。
10. manufacturing method according to claim 8 or claim 9, which is characterized in that the growth pressure of the barrier layer is 150torr
~300torr.
Priority Applications (1)
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| CN116581210A (en) * | 2023-07-10 | 2023-08-11 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
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| CN111900237A (en) * | 2020-08-13 | 2020-11-06 | 厦门乾照光电股份有限公司 | Ultraviolet LED chip and manufacturing method thereof |
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