CN103337573B - The epitaxial wafer of semiconductor light-emitting-diode and manufacture method thereof - Google Patents
The epitaxial wafer of semiconductor light-emitting-diode and manufacture method thereof Download PDFInfo
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Abstract
The invention discloses the epitaxial wafer of a kind of semiconductor light-emitting-diode, relate to technical field of semiconductors.This epitaxial wafer includes substrate and successively at low temperature buffer layer, high temperature buffer layer, recombination N-type layer, compound multiple quantum well layer and the recombination P-type layer of Grown.This compound multiple quantum well layer includes the first multiple quantum well layer and the second multiple quantum well layer grown on the first multiple quantum well layer.This first multiple quantum well layer is multicycle structure, and each cycle includes potential well layer and the barrier layer grown on potential well layer, and the barrier layer in this first multiple quantum well layer each cycle is respectively doped with Si.The Si of the barrier layer doping of epitaxial wafer the first multiple quantum well layer of the present invention can suppress the surface of barrier layer to form spiral island structure, and therefore the surface characteristic of barrier layer is good, and crystal mass is improved.The present invention discloses a kind of method manufacturing semiconductor light-emitting-diode epitaxial wafer.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to epitaxial wafer and the manufacture thereof of a kind of semiconductor light-emitting-diode
Method.
Background technology
With gallium nitride (GaN), indium nitride (InN), the aluminium nitride (AlN) group III-nitride as representative and their alloy
Indium gallium nitrogen (InGaN), the physics good because of it and chemical property, it is widely used in light emitting diode.
LED epitaxial slice includes substrate and the low temperature buffer layer being sequentially laminated on substrate, high temperature buffer layer, answers
Close N-type layer, compound multiple quantum well layer and recombination P-type layer.Wherein it is combined multiple quantum well layer and includes the first multiple quantum well layer and stacking
The second multiple quantum well layer on the first multiple quantum well layer, this first multiple quantum well layer and this second multiple quantum well layer are by alternately
The potential well layer (InGaN layer) of stacking and barrier layer (GaN layer) composition, wherein, the first multiple quantum well layer plays the effect of release stress,
The crystal mass making the second multiple quantum well layer is more preferable, and luminous efficiency is high.When making the first multiple quantum well layer, due to potential well layer
Need low-temperature epitaxy, and barrier layer needs high growth temperature, therefore among the process from low-temperature transformation to high temperature, potential well layer can be caused
Decompose.It has been proposed that grown at low temperature gallium nitride (GaN) cap rock protection potential well layer, and then improve the growth temperature of barrier layer.
During realizing the present invention, inventor finds that prior art at least there is problems in that
When making the first multiple quantum well layer, by the growth temperature of the barrier layer that the method for growth GaN cap rock improves, still
Less than the temperature needed for normal growth barrier layer so that when barrier layer grows at low temperatures, surface forms spiral island structure, causes
The surface characteristic making the barrier layer of the first multiple quantum well layer is poor, and then causes the crystal mass of the second multiple quantum well layer poor, luminous
Efficiency is low.
Summary of the invention
It is an object of the invention to provide epitaxial wafer and the manufacture method thereof of a kind of semiconductor light-emitting-diode, be avoided that first
The surface of the barrier layer of multiple quantum well layer forms spiral island structure, and the surface of the barrier layer improving the first multiple quantum well layer is special
Property, it is ensured that the crystal mass of the second multiple quantum well layer and luminous efficiency.
To achieve these goals, on the one hand, embodiments provide the extension of a kind of semiconductor light-emitting-diode
Sheet, the low temperature buffer layer including substrate and grown the most over the substrate, high temperature buffer layer, recombination N-type layer, compound Multiple-quantum
Well layer and recombination P-type layer, described compound multiple quantum well layer includes the first multiple quantum well layer and on described first multiple quantum well layer
Second multiple quantum well layer of growth, described first multiple quantum well layer is multicycle structure, and each cycle includes potential well layer and in institute
Stating the barrier layer of growth on potential well layer, periodicity is 4, and the growth temperature of the described potential well layer in each cycle is 780 DEG C, Mei Yizhou
The growth pressure of the described potential well layer of phase is 200Torr, and V/III mol ratio of the described potential well layer in each cycle is 4500, often
The thickness of the described potential well layer in one cycle is 2.5nm；The barrier layer in described first multiple quantum well layer each cycle respectively doped with
The Effective Doping concentration of Si, Si is 2 × 1017/cm3, the growth temperature of the described barrier layer in each cycle is 900 DEG C, Mei Yizhou
The growth pressure of the described barrier layer of phase is 200Torr, and V/III mol ratio of the described barrier layer in each cycle is 4500, often
The thickness of the described barrier layer in one cycle is 12nm.
In one embodiment of the invention, in described first multiple quantum well layer, described Si is entrained in described barrier layer
The position away from described potential well layer.
In another embodiment of the invention, 10%～the 90% of described barrier layer thickness is doped with described Si.
On the other hand, embodiments provide a kind of method manufacturing semiconductor light-emitting-diode epitaxial wafer, including:
One substrate is provided；
The most successively low temperature growth buffer layer, high temperature buffer layer, recombination N-type layer, compound multiple quantum well layer and
Recombination P-type layer, wherein, described compound multiple quantum well layer includes the first multiple quantum well layer and life on described first multiple quantum well layer
The second long multiple quantum well layer, described first multiple quantum well layer is multicycle structure, and each cycle includes potential well layer and described
The barrier layer of growth on potential well layer,
Wherein, periodicity is 4, and the growth temperature of the described potential well layer in each cycle is 780 DEG C, the described gesture in each cycle
The growth pressure of well layer is 200Torr, and V/III mol ratio of the described potential well layer in each cycle is 4500, the institute in each cycle
The thickness stating potential well layer is 2.5nm；When growing the barrier layer in described first multiple quantum well layer each cycle, in described barrier layer
The Effective Doping concentration of doping Si, Si is 2 × 1017/cm3, the growth temperature of the described barrier layer in each cycle is 900 DEG C, often
The growth pressure of the described barrier layer in one cycle is 200Torr, and V/III mol ratio of the described barrier layer in each cycle is
4500, the thickness of the described barrier layer in each cycle is 12nm.
In one embodiment of the invention, in described first multiple quantum well layer, described Si is entrained in described barrier layer
The position away from described potential well layer.
In another embodiment of the invention, 10%～the 90% of described barrier layer thickness is doped with described Si.
The technical scheme that the embodiment of the present invention provides has the benefit that
When the barrier layer of the first multiple quantum well layer grows at low temperatures, the Si of barrier layer doping can suppress the table of barrier layer
Face forms spiral island structure, and therefore the surface characteristic of barrier layer is good, and this is further such that be layered on the first multiple quantum well layer
The crystal mass of the second multiple quantum well layer good, luminous efficiency is high.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
The structural representation of the epitaxial wafer of the semiconductor light-emitting-diode that Fig. 1 provides for the embodiment of the present invention；
Fig. 2 is the detailed construction schematic diagram of compound multiple quantum well layer in epitaxial wafer shown in Fig. 1；
The flow chart of the method manufacturing semiconductor light-emitting-diode epitaxial wafer that Fig. 3 provides for the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
Present embodiments providing the epitaxial wafer of a kind of semiconductor light-emitting-diode, participate in Fig. 1, this epitaxial wafer includes substrate 1
With the low temperature buffer layer 2 stacked gradually on substrate 1, high temperature buffer layer 3, recombination N-type layer, compound multiple quantum well layer and compound P
Type layer.This compound multiple quantum well layer includes the first multiple quantum well layer 8 and the second Multiple-quantum grown on the first multiple quantum well layer 8
Well layer 9.In conjunction with Fig. 2, the first multiple quantum well layer 8 is multicycle structure, and each cycle includes potential well layer b1 and on potential well layer b1
The barrier layer a1 of growth.The barrier layer a1 in each cycle of the first multiple quantum well layer 8 is respectively doped with Si, Fig. 2 bend region
Represent the part of the Si that adulterates in barrier layer a1.
Further, in the first multiple quantum well layer 8, Si is entrained in the position away from potential well layer b1 of barrier layer a1.
The advantage of technique scheme is: undope Si in the position near potential well layer, has been avoided that Si is diffused into potential well
Non-radiative recombination is formed in Ceng.Further, 10%～the 90% of barrier layer thickness is doped with Si, Si such doping thickness ratio
Example can either suppress dislocation, is unlikely to again Si and is diffused in trap.
Further, the Effective Doping concentration of Si is 5 × 1016～1 × 1019/cm3, such Effective Doping concentration can
Enough suppress dislocation, how high be unlikely to again doping content, bring extra defect.
Further, the thickness of barrier layer is 10～15nm, and such scope can be good at limiting carrier at well region
Compound, and serve the effect improving SQW crystal mass.
Further, the periodicity of the first multiple quantum well layer is 2～6, and such periodicity had both served raising crystal matter
The effect of amount, is unlikely to again periodicity too much, and causes the SQW crystal mass grown below to decline.
As shown from the above technical solution, when the barrier layer of the first multiple quantum well layer grows at low temperatures, barrier layer doping
Si can suppress the surface of barrier layer to form spiral island structure, and therefore the surface characteristic of barrier layer is good, and this is further such that layer
The crystal mass of the second multiple quantum well layer being stacked on the first multiple quantum well layer is good, luminous efficiency is high.
It addition, barrier layer doping Si mono-aspect can reduce the point defect density of barrier layer, thus can improve at low temperature
The crystal mass of the barrier layer of lower growth, can effectively shield polarization field simultaneously.
Embodiment two
Present embodiments providing a kind of method manufacturing semiconductor light-emitting-diode epitaxial wafer, the method utilizes Thomas
Swan (AIXTRON subsidiary) CCS MOCVD system is implemented, and the method is with high-purity hydrogen (H2) or nitrogen (N2) as carrying
Gas, with trimethyl gallium (TMGa) or triethyl-gallium (TEGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia
(NH3) respectively as Ga, Al, In and N source, with silane (SiH4), two cyclopentadienyl magnesium (Cp2Mg) respectively as N, P-type dopant.
Specifically, with reference to Fig. 3, and combining Fig. 1 and Fig. 2, the present embodiment manufactures the side of semiconductor light-emitting-diode epitaxial wafer
Method comprises the steps:
Step S1 a, it is provided that substrate 1 also carries out warm wash and nitrogen treatment to substrate 1: by substrate 1 at 1050～1200 DEG C
In temperature range, (such as 1180 DEG C), the surface of pure hydrogen atmosphere interior-heat cleaning substrate 1, be then cooled to 630 DEG C by substrate 1,
Carrying out nitrogen treatment at such a temperature, in the present embodiment, substrate 1 is to be suitable for gallium nitride and other semiconductor epitaxial Material growth
Material, such as gallium nitride single crystal, sapphire, monocrystal silicon, single-crystal silicon carbide etc.；
Step S2, on substrate 1 low temperature growth buffer layer 2: after substrate 1 processes, drop to 500 DEG C～650 DEG C at a temperature of inciting somebody to action
(at such as 630 DEG C), in one layer of low temperature buffer layer of substrate 1 superficial growth 2 (this low temperature buffer layer 2 adulterate GaN), this growth course
In, growth pressure is 300～760Torr (such as growth pressure is 400Torr), and V/III mol ratio is 600～3000 (such as
V/III mol ratio is 900), wherein the thickness of low temperature buffer layer 2 is 20～30nm (such as thickness is 25nm)；
Step S3, grows high temperature buffer layer 3: after low temperature buffer layer 2 growth terminates, stop being passed through on low temperature buffer layer 2
TMGa (trimethyl gallium), is increased to 1000～1200 DEG C (being such as increased to 1170 DEG C), to low temperature buffer layer by the temperature of substrate 1
2 carry out thermal anneal process, and the thermal annealing time is 5～10 minutes (such as 5 minutes), after thermal anneal process, temperature are regulated extremely
1000～1200 DEG C (such as regulating to 1180 DEG C), low temperature buffer layer 2 grows one layer of high temperature buffer layer 3 (this high-temperature buffer
Layer 3 undopes GaN), in this growth course, growth pressure is 100～600Torr (such as growth pressure is 200Torr), V/
III mol ratio is 300～3000 (such as V/III mol ratio is 1500), and wherein the thickness of high temperature buffer layer 3 is 0.8～2 μm (examples
If thickness is 1.2 μm)；
Step S4, grows the first N-type layer 4: after high temperature buffer layer 3 growth terminates, at high-temperature buffer on high temperature buffer layer 3
Growing one layer of first N-type layer 4 on layer 3, in this growth course, growth pressure is that 100～600Torr (such as growth pressure is
150Torr), V/III mol ratio is 300～3000 (such as V/III mol ratio is 1800), and growth temperature is 1000～1200 DEG C
(such as growth temperature is 1180 DEG C), wherein the thickness of the first N-type layer 4 is at 0.2～1 μm (such as thickness is 0.8 μm), a N
Type layer 4 is doped with SiH4, and doping content is from 1 × 1017/cm3Change to 5 × 1018/cm3；
Step S5, the first N-type layer 4 grows second N-type layer 5: the first N-type layer 4 growth terminate after, in the first N-type layer 4
One layer of second N-type layer 5 of upper growth, in this growth course, growth pressure is that 100～600Torr (such as growth pressure is
150Torr), V/III mol ratio is 300～3000 (such as V/III mol ratio is 1800), and growth temperature is 1000 DEG C～1200
DEG C (such as growth temperature is 1180 DEG C), wherein the thickness of the second N-type layer 5 is 1.2～3.5 μm (such as thickness is 3.5 μm),
Two N-type layer 5 are doped with SiH4, and doping content is stable；
Step S6, after in the second N-type layer 5, the growth of growth regulation three N-type layer 6: the second N-type layer 5 terminates, in the second N-type layer 5
One layer of the 3rd N-type layer 6 of upper growth, in this growth course, growth pressure is that 100～600Torr (such as growth pressure is
150Torr), V/III mol ratio is 300～3000 (such as V/III mol ratio is 2800), and growth temperature is 1000～1200 DEG C
(such as growth temperature is 1180 DEG C), wherein the thickness of the 3rd N-type layer 6 is 10～100nm (such as thickness is 20nm), the 3rd N
Type layer 6 is doped with SiH4, and doping content is stable, and doping content is less than the mean concentration of the first N-type layer 4, less than the second N-type layer 5
Doping content, far below the doping content of the 4th N-type layer 7, its purpose is to improve the mobility of carrier；
Step S7, after in the 3rd N-type layer 6, the growth of growth regulation four N-type layer 7: the three N-type layer 6 terminates, in the 3rd N-type layer 6
One layer of the 4th N-type layer 7 of upper growth, in this growth course, growth pressure is that 100～600Torr (such as growth pressure is
150Torr), V/III mol ratio is 300～3000 (such as V/III mol ratio is 2800)；Growth temperature is 1000～1200 DEG C
(such as growth temperature is 1180 DEG C), wherein the thickness of the 4th N-type layer 7 is 10～50nm (such as thickness is 10nm), the 4th N-type
Layer 7 is doped with SiH4, and doping content is stable, and doping content is higher than the doping content of the second N-type layer 5, and the 4th N-type layer 7 is whole
The region that individual N-type regional concentration is the highest, its purpose is to obtain higher carrier concentration；
Step S8, after in the 4th N-type layer 7, one layer of first MQW (MQW) layer 8:N type layer 7 growth of growth terminates,
Growing one layer of first multiple quantum well layer 8 in N-type layer 7, the first multiple quantum well layer 8 is multicycle structure, and periodicity is 2～6 (such as
Periodicity is 4), each cycle includes potential well layer b1 (InaGa1-aN shell, 0 ＜ a ＜ 1) and the barrier layer that is layered on potential well layer b1
(the most each cycle includes In to (GaN layer) a10.3Ga0.7N shell and GaN layer), the growth technique of each of which periodic potential well layer b1
Condition is: growth temperature is 720～850 DEG C (such as growth temperature is 780 DEG C), and growth pressure is 100～500Torr (such as
Growth pressure is 200Torr), V/III mol ratio is 300～5000 (such as V/III mol ratio is 4500), each cycle potential well
The thickness of layer b1 is 2～3nm (such as thickness is 2.5nm)；The barrier layer a1 in each cycle is entrained in gesture doped with Si, Si respectively
The position away from potential well layer b1 of barrier layer a1.Specifically, the 10% of barrier layer thickness～90% (such as 50%) is doped with Si, Si
Effective Doping concentration be 5 × 1016～1 × 1019/cm3(such as Effective Doping concentration is 2 × 1017/cm3, it should be noted that
Effective Doping concentration refers to the maximum impurity concentration activated, and " activates " impurity being will be mixed in Si by certain means here
Ionization, forms the process of conductive mechanism), the part of the Si that adulterates in Fig. 2 bend region representation barrier layer a1., each periodic potential
The growth technique condition of barrier layer a1 is: growth temperature is 820～950 DEG C (such as growth temperature is 900 DEG C), and growth pressure is
100～500Torr (such as growth pressure is 200Torr), V/III mol ratio is that 300～5000 (such as V/III mol ratio is
4500), the thickness of each periodic potential barrier layer a1 is 10～15nm (such as thickness is 12nm)；
Step S9, grows one layer of second MQW (MQW) layer 9: the first multiple quantum well layer on the first multiple quantum well layer 8
After 8 growths terminate, growing one layer of second multiple quantum well layer 9 on the first multiple quantum well layer 8, this second multiple quantum well layer 9 is many
Periodic structure, periodicity is 3～6 (such as periodicity is 5), and each cycle includes potential well layer b2 (InbGa1-bN shell, 0 ＜ b ＜ 1)
(the most each cycle includes In with barrier layer (GaN) a2 being layered on potential well layer b20.3Ga0.7N shell and GaN layer).The most every
The growth technique condition of one periodic potential well layer b2 is: growth temperature is 720～820 DEG C (such as growth temperature is 780 DEG C), growth
Pressure is 100～500Torr (such as growth pressure is 200Torr), and V/III mol ratio is that 300～5000 (such as V/III rubs
Your ratio is 4500), the thickness of each periodic potential well layer b2 is 2～3nm (such as thickness is 2.5nm)；Each periodic potential barrier layer a2
Growth technique condition be: growth temperature is 820～920 DEG C (such as growth temperature is 900 DEG C), growth pressure be 100～
500Torr (such as growth pressure is 200Torr), V/III mol ratio is 300～5000 (such as V/III mol ratio is 4500),
The gross thickness of each periodic potential barrier layer a2 is 10～15nm (such as thickness is 12nm), and wherein, barrier layer a2 undopes；Step
S10, after on the second multiple quantum well layer 9, one layer of first P-type layer 10: the second multiple quantum well layer 9 growth of growth terminates, more than second
Growing one layer of first P-type layer 10 on quantum well layer 9, this first P-type layer 10 is AlxGa1-xN material, 0 ＜ x ＜ 1, plays electronics resistance
The effect of gear, in the growth course of the first P-type layer 10, growth temperature is 950～1080 DEG C (such as temperature is 1020 DEG C), growth
Pressure is 50～500Torr (such as growth pressure is 300Torr), and V/III mol ratio is that 1000～20000 (such as V/III rubs
Your ratio is 12000), wherein the thickness of the first P-type layer 10 is 10～200nm (such as growth thickness is 20nm), this first P-type layer
The energy gap of 10 is 4～5.5eV, P-type layer 10 doped with Mg (magnesium), P-type layer 10 doped with two cyclopentadienyls magnesium (Cp2Mg), doping
In Mg and the first P-type layer 10, the mol ratio of Ga is that 1/100～1/4 (such as mol ratio is: Mg/Ga=1/4)；
Step S11, grows after the growth of one layer of second P-type layer 11: the first P-type layer 10 terminates in the first P-type layer 10, the
Growing one layer of second P-type layer 11 in one P-type layer 10, this second P-type layer 11 is GaN material, the growth course of the second P-type layer 11
In, growth pressure 200Torr, V/III mol ratio 8000, growth temperature is 850～1050 DEG C (such as growth temperatures 1000 DEG C),
Wherein the thickness of the second P-type layer 11 is 100～800nm (such as thickness is 0.4 μm), and the second P-type layer 11 is doped with two cyclopentadienyl magnesium
(Cp2Mg), in the Mg of doping and the second P-type layer 11, the mol ratio of Ga is that 1/100～1/4 (such as mol ratio is: 1/80)；
Step S12, grows after the growth of one layer of the 3rd P-type layer 12: the second P-type layer 11 terminates in the second P-type layer 11, the
Growing one layer of the 3rd P-type layer 12 in two P-type layer 11, the 3rd P-type layer 12 is GaN material, is contact layer, the 3rd P-type layer 12
In growth course, growth pressure is 100～760Torr (such as growth pressure is 200Torr), V/III mol ratio be 1000～
20000 (such as V/III mol ratios 10000), growth temperature is (such as growth temperature is 1050 DEG C) between 850～1050 DEG C,
Wherein the thickness of the 3rd P-type layer 12 is 5～20nm (such as thickness is 15nm), and the 3rd P-type layer 10 is doped with two cyclopentadienyl magnesium
(Cp2Mg), in the Mg of doping and the 3rd P-type layer 12, the mol ratio of Ga is that 1/100～1/4 (such as mol ratio is: Mg/Ga=1/
50)；
Step S13, later stage process: after the 3rd P-type layer 12 growth terminates, the temperature of reaction chamber is down to 650～850 DEG C
(being such as down to 800 DEG C), carries out making annealing treatment 5～15min (such as processing 10min) in pure nitrogen gas atmosphere, is then down to room temperature,
So far, the epitaxial wafer of semiconductor light-emitting-diode completes.
It should be noted that after the epitaxial wafer of semiconductor light-emitting-diode completes, the 3rd P-type layer 12 grows one
Layer transparency conducting layer (ITO) 13, welds a P electrode 14 on transparency conducting layer 13, welds a N electricity in the second N-type layer 5
Pole 15, such semiconductor light-emitting-diode completes.Semiconductor light-emitting-diode is through over cleaning, deposition, photoetching and etching etc.
After semiconducter process processing procedure, the LED chip being divided into size to be 11 × 11mil.Test through LED chip, test electricity
Stream 20mA, single little chip optical output power is 11.5mW or 11.0mW.And traditional epitaxial growth regime, identical chips processing procedure
The output of single little chip light be 10.2mW.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (6)
1. an epitaxial wafer for semiconductor light-emitting-diode, including substrate and the low temperature buffer that grows the most over the substrate
Layer, high temperature buffer layer, recombination N-type layer, compound multiple quantum well layer and recombination P-type layer, described compound multiple quantum well layer includes first
Multiple quantum well layer and the second multiple quantum well layer grown on described first multiple quantum well layer, described first multiple quantum well layer is many
Periodic structure, each cycle include potential well layer and on described potential well layer growth barrier layer, it is characterised in that periodicity is 4,
The growth temperature of the described potential well layer in each cycle is 780 DEG C, and the growth pressure of the described potential well layer in each cycle is
200Torr, V/III mol ratio of the described potential well layer in each cycle is 4500, and the thickness of the described potential well layer in each cycle is
2.5nm；The barrier layer in described first multiple quantum well layer each cycle Effective Doping concentration doped with Si, Si respectively is 2 ×
1017/cm3, the growth temperature of the described barrier layer in each cycle is 900 DEG C, the growth pressure of the described barrier layer in each cycle
For 200Torr, V/III mol ratio of the described barrier layer in each cycle is 4500, the thickness of the described barrier layer in each cycle
For 12nm.
2. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 1, it is characterised in that at described first MQW
In Ceng, described Si is entrained in the position away from described potential well layer of described barrier layer.
3. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 2, it is characterised in that described barrier layer thickness
10%～90% doped with described Si.
4. the method manufacturing semiconductor light-emitting-diode epitaxial wafer, including:
One substrate is provided；
Low temperature growth buffer layer, high temperature buffer layer, recombination N-type layer, compound multiple quantum well layer and compound P the most successively
Type layer, wherein, described compound multiple quantum well layer includes the first multiple quantum well layer and growth on described first multiple quantum well layer
Second multiple quantum well layer, described first multiple quantum well layer is multicycle structure, and each cycle includes potential well layer and in described potential well
The barrier layer of growth on layer,
It is characterized in that, periodicity is 4, and the growth temperature of the described potential well layer in each cycle is 780 DEG C, each cycle described
The growth pressure of potential well layer is 200Torr, and V/III mol ratio of the described potential well layer in each cycle is 4500, each cycle
The thickness of described potential well layer is 2.5nm；When growing the barrier layer in described first multiple quantum well layer each cycle, at described barrier layer
The Effective Doping concentration of middle doping Si, Si is 2 × 1017/cm3, the growth temperature of the described barrier layer in each cycle is 900 DEG C,
The growth pressure of the described barrier layer in each cycle is 200Torr, and V/III mol ratio of the described barrier layer in each cycle is
4500, the thickness of the described barrier layer in each cycle is 12nm.
5. the method manufacturing semiconductor light-emitting-diode epitaxial wafer as claimed in claim 4, it is characterised in that described first
In multiple quantum well layer, described Si is entrained in the position away from described potential well layer of described barrier layer.
6. the method manufacturing semiconductor light-emitting-diode epitaxial wafer as claimed in claim 5, it is characterised in that described barrier layer
10%～the 90% of thickness is doped with described Si.
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| CN108735864B (en) * | 2018-05-28 | 2019-08-23 | 华灿光电（浙江）有限公司 | A kind of preparation method of LED epitaxial slice |
| JP6729644B2 (en) * | 2018-08-08 | 2020-07-22 | 日亜化学工業株式会社 | Nitride semiconductor light emitting device |
| JP6968122B2 (en) | 2019-06-06 | 2021-11-17 | 日機装株式会社 | Nitride semiconductor light emitting device |
| CN110718612B (en) * | 2019-08-30 | 2021-08-06 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and manufacturing method thereof |
| CN110854246B (en) * | 2019-11-15 | 2021-07-30 | 芜湖德豪润达光电科技有限公司 | Light emitting diode and light emitting diode manufacturing method |
| JP7194720B2 (en) * | 2020-10-30 | 2022-12-22 | 日機装株式会社 | Nitride semiconductor light emitting device |
| JP7260807B2 (en) * | 2020-12-24 | 2023-04-19 | 日亜化学工業株式会社 | Nitride semiconductor light emitting device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521258A (en) * | 2009-03-27 | 2009-09-02 | 武汉华灿光电有限公司 | Method for improving LED external quantum efficiency |
| CN102157657A (en) * | 2011-01-26 | 2011-08-17 | 中山大学 | GaN-based light emitting diode and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476567B1 (en) * | 2003-09-26 | 2005-03-17 | 삼성전기주식회사 | Nitride semiconductor device |
| CN100547819C (en) * | 2006-08-15 | 2009-10-07 | 中国科学院物理研究所 | The gallium nitride LED chip of hypopolarization effect is with epitaxial material and method for making |
| CN101859825A (en) * | 2009-04-07 | 2010-10-13 | 山东璨圆光电科技有限公司 | Multi-layer quantum well nitride light-emitting diode with carrier providing layer |
| KR20120022280A (en) * | 2010-09-01 | 2012-03-12 | 삼성엘이디 주식회사 | Nitride semiconductor light emitting device |
| CN103035791B (en) * | 2012-12-14 | 2015-12-09 | 华灿光电股份有限公司 | A kind of epitaxial wafer of light-emitting diode and manufacture method thereof |
-
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521258A (en) * | 2009-03-27 | 2009-09-02 | 武汉华灿光电有限公司 | Method for improving LED external quantum efficiency |
| CN102157657A (en) * | 2011-01-26 | 2011-08-17 | 中山大学 | GaN-based light emitting diode and preparation method thereof |
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