CN108461592B - A kind of LED epitaxial slice and its manufacturing method - Google Patents
A kind of LED epitaxial slice and its manufacturing method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Epitaxial wafer includes the insert layer being sequentially laminated on multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer, p-type contact layer；Insert layer is AlN layers, low temperature P-type layer is the AlGaN/GaN superlattice structure for mixing Mg or the AlGaN/InGaN superlattice structure for mixing Mg, AlN layers match with low temperature P-type layer, the effect of the electronic barrier layer of a part can be shared, the thickness of electronic barrier layer is thinned, to reduce the barrier effect to hole, more holes can improve the interior quantum luminous efficiency of LED in multiple quantum well layer and electronics recombination luminescence.Insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer overall thickness be 40~100nm, the thickness of P-type layer is thinned, and improves the outer quantum luminous efficiency of LED.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its manufacturing method.
Background technique
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.As
A kind of efficient, environmentally friendly, green New Solid lighting source, is widely applied rapidly, such as traffic lights, automobile
Inside and outside lamp, landscape light in city, cell phone back light source etc..
Epitaxial wafer is the main composition part in LED, and existing GaN base LED epitaxial wafer includes substrate and is arranged in substrate
On GaN base epitaxial layer, GaN base epitaxial layer include stack gradually buffer layer on substrate, undoped GaN layer, N-type layer,
Multiple quantum well layer, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer.Wherein, insert layer is
AlGaN layer, low temperature P-type layer be InGaN layer, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer
Overall thickness is about 130~180nm.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Since in existing LED epitaxial wafer, electronic barrier layer is commonly designed thicker (generally reaching 50nm), thicker electricity
Sub- barrier layer will lead to the polarization and stress of storeroom, while can generate a high valence band and hinder hole to multiple quantum wells
Layer migration reduces the interior quantum luminous efficiency of LED so as to cause the reduction of Carrier recombination luminous efficiency.In addition, insert layer,
Low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer overall thickness be about 130~180nm, i.e., entire P-type layer
Thickness is thicker, reduces the outer quantum luminous efficiency of LED, then the luminous efficiency of LED is low.
Summary of the invention
In order to solve the problems, such as that the interior quantum luminous efficiency of LED in the prior art and outer quantum luminous efficiency are lower, this hair
Bright embodiment provides a kind of LED epitaxial slice and its manufacturing method.The technical solution is as follows:
On the one hand, the present invention provides a kind of LED epitaxial slice, the LED epitaxial slice include substrate,
And stack gradually buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P over the substrate
Type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer,
The low temperature P-type layer is the AlGaN/InGaN superlattices knot mixed the AlGaN/GaN superlattice structure of Mg or mix Mg
Structure, the doping concentration of Mg is greater than or equal to 1*10 in the low temperature P-type layer20cm-3；The insert layer is AlN layers, AlN layers described
With a thickness of 2~10nm, the insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer overall thickness
For 40~100nm.
Further, the low temperature P-type layer with a thickness of 10~30nm.
Further, the periodicity of the AlGaN/GaN superlattice structure or the AlGaN/InGaN superlattice structure is equal
For N, 4≤N≤10.
Further, the thickness of AlGaN sublayer and GaN sublayer is 1~3nm in the AlGaN/GaN superlattice structure,
Alternatively, the thickness of AlGaN sublayer and InGaN sublayer is 1~3nm in the AlGaN/InGaN superlattice structure.
On the other hand, the present invention provides a kind of manufacturing methods of LED epitaxial slice, which is characterized in that the system
The method of making includes:
One substrate is provided；
Successively grown buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature over the substrate
P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, the low temperature P-type layer are to mix the AlGaN/GaN superlattices knot of Mg
Structure or the AlGaN/InGaN superlattice structure for mixing Mg, the doping concentration of Mg is greater than or equal to 1*10 in the low temperature P-type layer20cm-3；The insert layer is AlN layers, described AlN layers with a thickness of 2~10nm, the insert layer, low temperature P-type layer, electronic barrier layer,
High temperature P-type layer and the overall thickness of p-type contact layer are 40~100nm.
Further, the growth temperature of the low temperature P-type layer is 700~800 DEG C.
Further, the low temperature P-type layer with a thickness of 10~30nm.
Further, the growth temperature of the insert layer is 800~900 DEG C.
Technical solution provided in an embodiment of the present invention has the benefit that
By between multiple quantum well layer and P-type layer be arranged a relatively thin AlN layer, AlN layers be capable of forming it is one higher
Potential barrier energy level, stop the migration of electronics, low temperature P-type layer is AlGaN/GaN the or AlGaN/InGaN superlattices knot of heavily doped Mg
Structure can reduce the influence of stress caused by lattice mismatch using AlGaN/GaN superlattice structure, while AlGaN/GaN is super
Lattice structure, which can serve as buffer layer, reduces the lattice mismatch that the high electronic barrier layer of subsequent growth Al component generates, and reduces heterogeneous
Band offsets caused by junction interface.And low temperature P-type layer is heavily doped Mg layers, the doping concentration of Mg is greater than or equal to 1*1020cm-3,
The main offer layer in hole is provided.And for AlGaN/InGaN superlattice structure, due to AlGaN/InGaN superlattices knot
The crystal lattice mismatch of structure is bigger, therefore can produce certain two-dimensional electron gas, preferably provides hole, then more holes
The interior quantum luminous efficiency of LED can be improved in multiple quantum well layer and electronics recombination luminescence.And pass through AlN layers and low temperature p-type
Layer matches, and can form more conduction levels and stop electronics, share the effect of the electronic barrier layer of a part, so as to be thinned
The thickness of electronic barrier layer, and then the polarization and stress of storeroom are reduced, the electronic barrier layer of high Al contents is reduced in valence
With the Valence-band Offsets that heterojunction boundary generates, hole is allowed preferably to inject active area, the interior quantum for further improving LED shines
Efficiency.Meanwhile insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer overall thickness be 40~
100nm, with the overall thickness of traditional insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer be 130~
180nm is compared, and is thinned the thickness of P-type layer, improves the outer quantum luminous efficiency of LED, to improve the luminous effect of LED
Rate.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of method flow diagram of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
The embodiment of the invention provides a kind of light emitting diode, Fig. 1 is a kind of light-emitting diodes provided in an embodiment of the present invention
The structural schematic diagram of pipe epitaxial wafer, as shown in Figure 1, the light emitting diode includes substrate 1 and is sequentially laminated on substrate 1
Buffer layer 2, undoped GaN layer 3, N-type layer 4, multiple quantum well layer 5, insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature
P-type layer 9, p-type contact layer 10.
Low temperature P-type layer 7 is the AlGaN/GaN superlattice structure for mixing Mg or the AlGaN/InGaN superlattice structure for mixing Mg, low
The doping concentration of Mg is greater than or equal to 1*10 in warm P-type layer 720cm-3.Insert layer 6 be AlN layers, insert layer 6, low temperature P-type layer 7,
The overall thickness of electronic barrier layer 8, high temperature P-type layer 9 and p-type contact layer 10 is 40~100nm.
For the embodiment of the present invention by the way that a relatively thin AlN layer is arranged between multiple quantum well layer and P-type layer, AlN layers can
A higher potential barrier energy level is formed, the migration of electronics is stopped, low temperature P-type layer is the AlGaN/GaN or AlGaN/ of heavily doped Mg
InGaN superlattice structure can reduce the influence of stress caused by lattice mismatch using AlGaN/GaN superlattice structure, together
When AlGaN/GaN superlattice structure can serve as buffer layer and reduce the lattice that the high electronic barrier layer of subsequent growth Al component generates
Mismatch reduces band offsets caused by heterojunction boundary.And low temperature P-type layer be heavily doped Mg layers, the doping concentration of Mg be greater than or
Equal to 1*1020cm-3, the main offer layer in hole is provided.And for AlGaN/InGaN superlattice structure, due to AlGaN/
The crystal lattice mismatch of InGaN superlattice structure is bigger, therefore can produce certain two-dimensional electron gas, preferably provides empty
Cave, then more holes can improve the interior quantum luminous efficiency of LED in multiple quantum well layer and electronics recombination luminescence.And it is logical
It crosses AlN layers and low temperature P-type layer matches, more conduction levels can be formed and stop electronics, share the electronic barrier layer of a part
Effect so as to which the thickness of electronic barrier layer is thinned, and then reduces the polarization and stress of storeroom, reduces high Al contents
The Valence-band Offsets that are generated in valence band heterojunction boundary of electronic barrier layer, allow hole preferably to inject active area, further increase
The interior quantum luminous efficiency of LED.Further, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact
The overall thickness of layer is 40~100nm, is contacted with traditional insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type
The overall thickness of layer is that 130~180nm is compared, and is thinned the thickness of P-type layer, the outer quantum luminous efficiency of LED is improved, to mention
The high luminous efficiency of LED.
Further, low temperature P-type layer 7 with a thickness of 10~30nm.If the thickness of low temperature P-type layer 7 is greater than 30nm, can make
Thickness at low temperature P-type layer is blocked up, causes the integral thickness of epitaxial wafer larger, reduces the luminous efficiency of LED, and can waste material
Material increases growth time.If the thickness of low temperature P-type layer 7 is less than 10nm, blocking electronics can not be played, electronic barrier layer is thinned
Effect.
Further, when low temperature P-type layer 7 is AlGaN/GaN superlattice structure, the week of AlGaN/GaN superlattice structure
Issue is N, 4≤N≤10.If the value of N is excessive, the integral thickness that will lead to low temperature P-type layer 7 can be excessive, then epitaxial wafer is whole
Body thickness is larger, reduces the luminous efficiency of LED, and can waste material, increases growth time, if the value of N is too small, low temperature P
Type layer can not play the role of blocking electronics, and electronic barrier layer is thinned.
Optionally, the thickness of AlGaN sublayer and GaN sublayer is 1~3nm in AlGaN/GaN superlattice structure.AlGaN
Sublayer is identical convenient for practical growth with the thickness of GaN sublayer, if the thickness of AlGaN sublayer and GaN sublayer is excessive, will lead to outer
The integral thickness for prolonging piece is larger, reduces the luminous efficiency of LED, and can waste material, increase growth time, if AlGaN sublayer and
The thickness of GaN sublayer is too small, then low temperature P-type layer can not play the role of blocking electronics, and electronic barrier layer is thinned.
Preferably, the thickness of AlGaN sublayer and GaN sublayer is 1.8nm, N=6 in AlGaN/GaN superlattice structure, low
Warm P-type layer 7 with a thickness of 21.6nm, insert layer 6 with a thickness of 4mm.Low temperature P-type layer and insert layer cooperate at this time, to electronics
Blocking effect is best.
Further, when low temperature P-type layer 7 is AlGaN/InGaN superlattice structure, AlGaN/InGaN superlattice structure
Periodicity be N, 4≤N≤10.If the value of N is excessive, the integral thickness that will lead to low temperature P-type layer 7 can be excessive, then epitaxial wafer
Integral thickness it is larger, reduce the luminous efficiency of LED, and material can be wasted, increase growth time, it is low if the value of N is too small
Warm P-type layer can not play the role of blocking electronics, and electronic barrier layer is thinned.
Optionally, the thickness of AlGaN sublayer and InGaN sublayer is 1~3nm in AlGaN/InGaN superlattice structure.
AlGaN sublayer is identical convenient for practical growth with the thickness of InGaN sublayer, if the thickness of AlGaN sublayer and InGaN sublayer is excessive,
The integral thickness that then will lead to epitaxial wafer is larger, reduces the luminous efficiency of LED, and can waste material, increases growth time, if
The thickness of AlGaN sublayer and InGaN sublayer is too small, then low temperature P-type layer can not play blocking electronics, and the work of electronic barrier layer is thinned
With.
Preferably, the thickness of AlGaN sublayer and InGaN sublayer is 1.8nm, N=in AlGaN/InGaN superlattice structure
6, low temperature P-type layer 7 with a thickness of 21.6nm, insert layer 6 with a thickness of 4mm.Low temperature P-type layer and insert layer cooperate at this time, to electricity
The blocking effect of son is best.
Optionally, electronic barrier layer 8 is AlGaN layer or AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, AlGaN/
One of InAlN superlattice structure.
In the present embodiment, insert layer 6 with a thickness of 2~10nm, low temperature P-type layer 7 with a thickness of 10~30nm, electronics resistance
Barrier 8 with a thickness of 10~40nm, high temperature P-type layer 9 with a thickness of 8~15nm, p-type contact layer 10 with a thickness of 2~5nm, then
Insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature P-type layer 9 and p-type contact layer 10 overall thickness be 40~100nm.
Preferably, insert layer 6 with a thickness of 4nm, the overall thickness of low temperature P-type layer 7 is 21.6nm, the thickness of electronic barrier layer 8
Degree is 25nm, high temperature P-type layer 9 with a thickness of 10nm, p-type contact layer 10 with a thickness of 2.5nm, then insert layer 6, low temperature P-type layer
7, the overall thickness of electronic barrier layer 8, high temperature P-type layer 9 and p-type contact layer 10 is 63.1nm, and the light-out effect of LED is good at this time.
It should be noted that for the Light-Emitting Diode of positive assembling structure, when insert layer 6, low temperature P-type layer 7, electronics resistance
When the overall thickness of barrier 8, high temperature P-type layer 9 and p-type contact layer 10 is 80~90nm, the light-out effect of light emitting diode is best.
For the light emitting diode of inverted structure, when insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature p-type
When the overall thickness of layer 9 and p-type contact layer 10 is 60~70nm, the light-out effect of light emitting diode is best.
In the present embodiment, substrate 1 can be Sapphire Substrate, and buffer layer 2 can be AlN layers, and N-type layer 4 can be GaN
Layer, multiple quantum well layer 5 include InGaN quantum well layer and GaN quantum barrier layer.
Embodiment two
The embodiment of the invention provides a kind of manufacturing methods of LED epitaxial slice, provide suitable for embodiment one
LED epitaxial slice, Fig. 2 are a kind of methods of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention
Flow chart, as shown in Fig. 2, the manufacturing method includes:
Step 201 pre-processes substrate.
Optionally, substrate is sapphire, with a thickness of 630~650um.
In the present embodiment, using Veeco K465i or C4 MOCVD (Metal Organic Chemical Vapor
Deposition, metallo-organic compound chemical gaseous phase deposition) equipment realize LED growing method.Using high-purity H2(hydrogen)
Or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carrier gas, high-purity N H3As the source N, trimethyl gallium (TMGa)
And triethyl-gallium (TEGa) is used as gallium source, trimethyl indium (TMIn) is used as indium source, and silane (SiH4) is used as N type dopant, front three
Base aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as P-type dopant.Chamber pressure is 100~600torr.
Specifically, which includes:
In a hydrogen atmosphere, 5~6min of high-temperature process substrate.Wherein, reaction chamber temperature is 1000~1100 DEG C, reaction chamber
Pressure is controlled in 200~500torr.
Step 202, on substrate grown buffer layer.
Specifically, buffer growth is on sapphire face.
Specifically, Sapphire Substrate is sputtered at PVD (Physical Vapor Deposition, physical vapor deposition)
The AlN buffer layer of one layer of 5~40nm thickness of sputtering in furnace.
Step 203 grows undoped GaN layer on the buffer layer.
After buffer growth, there is the substrate of AlN buffer layer to be put into MOCVD device sputtering, room temperature will be reacted
Degree is increased to 1040 °, and growth thickness is the GaN layer that the high temperature of 1um undopes.
Step 204 grows N-type layer in undoped GaN layer.
In the present embodiment, N-type layer is to mix the GaN layer of Si, with a thickness of 2um.When growing N-type layer, reaction chamber temperature is
1000~1100 DEG C, chamber pressure is controlled in 200~300torr.
Step 205 grows multiple quantum well layer in N-type layer.
It in the present embodiment, can first growth stress releasing layer before growth multiple quantum well layer.
Specifically, stress release layer includes the InGaN well layer and GaN barrier layer of 3 period alternating growths, wherein InGaN trap
Layer with a thickness of 2nm, growth temperature is 850~900 DEG C, growth pressure 250torr.GaN barrier layer with a thickness of 30~50nm,
Growth temperature is 850~900 DEG C, growth pressure 250torr.
Stress release layer further includes the InGaN well layer and GaN barrier layer of 6 period alternating growths, wherein the thickness of InGaN well layer
Degree is 2nm, and growth temperature is 800~850 DEG C, growth pressure 250torr.GaN barrier layer with a thickness of 10~20nm, growth temperature
Degree is 800~850 DEG C, growth pressure 250torr.
Specifically, multiple quantum well layer is grown after having grown stress release layer, multiple quantum well layer includes 8~10 periods
The InGaN quantum well layer and GaN quantum barrier layer of alternating growth, wherein InGaN quantum well layer with a thickness of 2.5nm, growth temperature
It is 780~820 DEG C, growth pressure 250torr.GaN quantum barrier layer with a thickness of 12nm, growth temperature is 780~820 DEG C,
Growth pressure is 250torr.
Due to including InGaN quantum well layer and GaN quantum barrier layer in multiple quantum well layer, high component is grown in GaN material
InGaN quantum well layer, higher lattice mismatch can be faced, so that the crystal quality of multiple quantum well layer is influenced, by growing
Growth stress releasing layer before multiple quantum well layer can make lattice relaxation to the relatively more suitable high component InGaN quantum well layer of growth
State.
Step 206 grows insert layer on multiple quantum well layer.
In the present embodiment, insert layer be AlN layers, AlN layers with a thickness of 4nm.Growth temperature is 800~900 DEG C, growth
Pressure is 150~250torr.AlN layers are capable of forming a higher potential barrier energy level, stop the migration of electronics.
Step 207, the growing low temperature P-type layer in insert layer.
It specifically, is 700~800 DEG C in growth temperature, growth pressure is growing low temperature P under conditions of 50~600torr
Type layer, low temperature P-type layer are to mix the AlGaN/GaN superlattice structure of Mg, and the doping concentration of Mg is 1*10 in low temperature P-type layer20cm-3。
Wherein, the periodicity of AlGaN/GaN superlattice structure is 6, with a thickness of 21.6nm.
Specifically, when growing the AlGaN/GaN superlattice structure in each period, comprising:
Growth thickness is the AlGaN sublayer of 1.8nm, and growth time 30s, growth thickness is the GaN sublayer of 1.8nm, raw
It is for a long time 30s.The growth conditions and growth thickness of AlGaN sublayer and GaN sublayer are all the same, and it is super can to save AlGaN/GaN
The growth time of lattice structure.
Step 208 grows electronic barrier layer in low temperature P-type layer.
In the present embodiment, electronic barrier layer is the AlGaN layer for mixing Mg, and the doping concentration of Mg is less than 1*1019cm-3, electronics
Barrier layer with a thickness of 25nm.Growth temperature is 900~1000 DEG C, and growth pressure is 100~600torr.
Step 209 grows high temperature P-type layer on electronic barrier layer.
In the present embodiment, high temperature P-type layer is the GaN layer of heavy doping Mg, and the doping concentration of Mg is greater than or equal to 1*
1020cm-3, high temperature P-type layer with a thickness of 10nm.Growth temperature is 960-980 DEG C, and growth pressure is 100~600torr.
Step 210, the growing P-type contact layer in high temperature P-type layer.
In the present embodiment, p-type contact layer is the GaN layer of heavy doping Mg, and the doping concentration of Mg is greater than or equal to 4*
1020cm-3, p-type contact layer is with a thickness of 2.5nm.Growth temperature is 700~800 DEG C, and growth pressure is 300~600torr.
After the growth for terminating LED epitaxial slice, the temperature of reaction chamber is down to 600-900 DEG C, in PN2Gas
Atmosphere carries out annealing 10-30min, is then gradually decreased to room temperature, then, through over cleaning, deposition, lithography and etching following process
The chip of single 9*27mil is made in technique.
It is found after test, it is existing using LED chip made of manufacturing method provided in an embodiment of the present invention and use
LED chip made of technology is compared, and luminous efficiency improves 1%.
Embodiment three
The embodiment of the invention provides a kind of manufacturing methods of LED epitaxial slice, in manufacture provided in this embodiment
Method and the manufacturing method in embodiment two are essentially identical, the difference is that, in the present embodiment, low temperature P-type layer is
AlGaN/InGaN superlattice structure, the periodicity of AlGaN/InGaN superlattice structure is 6, with a thickness of 21.6nm.
Specifically, when growing the AlGaN/InGaN superlattice structure in each period, comprising:
Growth thickness is the AlGaN sublayer of 1.8nm, and growth time 30s, growth thickness is the InGaN sublayer of 1.8nm,
Growth time is 30s.
The growth of AlGaN/GaN superlattice structure in the growth conditions and embodiment two of AlGaN/InGaN superlattice structure
Condition is identical, and details are not described herein by the present invention.
After the growth for terminating LED epitaxial slice, the temperature of reaction chamber is down to 600-900 DEG C, in PN2Gas
Atmosphere carries out annealing 10-30min, is then gradually decreased to room temperature, then, through over cleaning, deposition, lithography and etching following process
The chip of single 9*27mil is made in technique.
It is found after test, it is existing using LED chip made of manufacturing method provided in an embodiment of the present invention and use
LED chip made of technology is compared, and luminous efficiency improves 1%.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate and is sequentially laminated on the lining
Buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P on bottom
Type layer and p-type contact layer, which is characterized in that
The low temperature P-type layer is the AlGaN/GaN superlattice structure for mixing Mg or the AlGaN/InGaN superlattice structure for mixing Mg, institute
The doping concentration for stating Mg in low temperature P-type layer is greater than or equal to 1*1020cm-3；The insert layer is AlN layers, AlN layers of the thickness
Degree is 2~10nm, the insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer overall thickness be 40
~100nm.
2. LED epitaxial slice according to claim 1, which is characterized in that the low temperature P-type layer with a thickness of 10
~30nm.
3. LED epitaxial slice according to claim 2, which is characterized in that the AlGaN/GaN superlattice structure
Or the periodicity of the AlGaN/InGaN superlattice structure is N, 4≤N≤10.
4. described in any item LED epitaxial slices according to claim 1~3, which is characterized in that the AlGaN/GaN is super
The thickness of AlGaN sublayer and GaN sublayer is 1~3nm in lattice structure, alternatively, in the AlGaN/InGaN superlattice structure
The thickness of AlGaN sublayer and InGaN sublayer is 1~3nm.
5. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes:
One substrate is provided；
Successively grown buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature p-type over the substrate
Layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, the low temperature P-type layer be mix Mg AlGaN/GaN superlattice structure or
The AlGaN/InGaN superlattice structure of Mg is mixed, the doping concentration of Mg is greater than or equal to 1*10 in the low temperature P-type layer20cm-3；Institute
State insert layer be AlN layers, described AlN layers with a thickness of 2~10nm, the insert layer, low temperature P-type layer, electronic barrier layer, high temperature
P-type layer and the overall thickness of p-type contact layer are 40~100nm.
6. manufacturing method according to claim 5, which is characterized in that the growth temperature of the low temperature P-type layer be 700~
800℃。
7. manufacturing method according to claim 5 or 6, which is characterized in that the low temperature P-type layer with a thickness of 10~
30nm。
8. manufacturing method according to claim 5 or 6, which is characterized in that the growth temperature of the insert layer be 800~
900℃。
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| CN112259651B (en) * | 2020-10-21 | 2022-02-01 | 厦门乾照光电股份有限公司 | LED chip with P-type insertion layer and manufacturing method |
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| CN114613889A (en) * | 2022-03-24 | 2022-06-10 | 淮安澳洋顺昌光电技术有限公司 | GaN-based LED epitaxial structure capable of improving antistatic capacity |
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