CN108281519A - A kind of LED epitaxial slice and its manufacturing method - Google Patents
A kind of LED epitaxial slice and its manufacturing method Download PDFInfo
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- CN108281519A CN108281519A CN201810089267.0A CN201810089267A CN108281519A CN 108281519 A CN108281519 A CN 108281519A CN 201810089267 A CN201810089267 A CN 201810089267A CN 108281519 A CN108281519 A CN 108281519A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Epitaxial wafer includes electronic barrier layer, and electronic barrier layer is the superlattice structure for including N number of period, and the superlattice structure in each period includes InxGa1‑xN layers and AlyGa1‑yN layers, InxGa1‑xN layers grow at 900~950 DEG C, can improve the efficiency of lattice quality and the electrons and holes recombination luminescence in multiple quantum well layer of multiple quantum well layer, while the presence of In reduces the activation energy of Mg, improves the hole concentration of P-type layer.AlyGa1‑yN layers grow at 950~980 DEG C, improve AlyGa1‑yN layers of barrier height, blocking electronics overflow is to P-type layer, and the content of Al is continuously decreased or gradually risen, and blocking electronics overflow can improve the luminous efficiency of diode to P-type layer while reducing the barrier effect for hole.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of LED epitaxial slice and its manufacturing method.
Background technology
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.With
LED component based on GaN base is used as a kind of efficient, environmentally friendly, green New Solid lighting source, is widely obtained rapidly
To application, such as traffic lights, outdoor full color display screen, landscape light in city, automobile interior exterior lamp, cell phone back light source.
GaN base LED epitaxial wafer is the primary structure of GaN base LED component, and the structure of GaN base LED epitaxial wafer includes：Substrate,
And buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, high temperature P-type layer and the p-type being stacked on substrate connect
Contact layer.The main reason for causing GaN base LED component luminous efficiency relatively low is that GaN base LED epitaxial wafer internal quantum efficiency is relatively low, and
The main reason for causing internal quantum efficiency low include：The electronics that the injection efficiency in hole is low and multiple quantum well layer overflows enters
With hole non-radiative recombination occurs for P-type layer.P-type layer and hole hair are entered in order to solve the electronics that above-mentioned multiple quantum well layer overflows
The low problem of LED component luminous efficiency caused by raw non-radiative recombination, GaN base LED epitaxial wafer can also include being arranged in volume
Electronic barrier layer between sub- well layer and P-type layer stops that the electronics that multiple quantum well layer overflows enters p-type by electronic barrier layer
Layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems：
Electronic barrier layer in traditional GaN base LED epitaxial wafer is the AlGaN layer of high growth temperature, Al in electronic barrier layer
The higher epitaxial wafer crystal quality that can cause to grow of content it is poor, while the potential barrier of the higher then electronic barrier layer of content of Al is high
Degree is high, can stop the injection in hole, smaller to the effect for promoting internal quantum efficiency；And since electronic barrier layer is at 980 DEG C
At a high temperature of grow, high temperature can destroy the crystal quality of multiple quantum well layer, to influence the performance of LED epitaxial wafer.
Invention content
The higher internal quantum efficiency for causing LED of content in order to solve Al in electronic barrier layer in the prior art is low, and
Electronic barrier layer grows the problem of destroying multiple quantum well layer at high temperature, and an embodiment of the present invention provides a kind of light emitting diodes
Epitaxial wafer and its manufacturing method.The technical solution is as follows：
On the one hand, the present invention provides a kind of LED epitaxial slice, the LED epitaxial slice include substrate,
And buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, the electronic blocking being cascading over the substrate
Layer, high temperature P-type layer and p-type contact layer,
The electronic barrier layer is the superlattice structure for including N number of period, and the superlattice structure in each period includes close
The In of the multiple quantum well layerxGa1-xN layers and the Al far from the multiple quantum well layeryGa1-yN layers, 0.1≤x≤0.2,0≤y≤
0.2, the InxGa1-xThe content of In is less than the content of In in the multiple quantum well layer, the Al in N layersyGa1-yAl in N layers
Content is continuously decreased or is gradually risen, the InxGa1-xN layers grow at 900~950 DEG C, the AlyGa1-yN layers
It is grown at 950~980 DEG C, 5≤N≤12.
Further, the thickness of the electronic barrier layer is 30~72nm.
Further, the InxGa1-xN layers of thickness is 2.5~3nm, the AlyGa1-yN layers of thickness be 2.5~
3nm。
Further, the InxGa1-xN layers grow at 900 DEG C, the AlyGa1-yN layers grown at 970 DEG C and
At.
Further, the InxGa1-xN layers and the AlyGa1-yMixed with Mg, the In in N layersxGa1-xN layers and described
AlyGa1-yThe doping concentration of Mg is 1 × 10 in N layers17~1 × 1018cm-3。
On the other hand, the present invention provides a kind of manufacturing method of LED epitaxial slice, the manufacturing method includes：
One substrate is provided；
Over the substrate successively grown buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, electronic barrier layer,
High temperature P-type layer and p-type contact layer；
Wherein, the electronic barrier layer is grown, including：Grow the super crystalline substance in N number of period successively on the multiple quantum well layer
Lattice structure, 5≤N≤12；Wherein, the superlattice structure in each period is grown in the following way：
Under conditions of growth temperature is 900~950 DEG C, In is grownxGa1-xN layers, 0.1≤x≤0.2, the InxGa1-xN
The content of In is less than the content of In in the multiple quantum well layer in layer；
Under conditions of growth temperature is 950~980 DEG C, in the InxGa1-xAl is grown on N layersyGa1-yN layers, 0≤y≤
0.2, the AlyGa1-yThe content of Al is continuously decreased or is gradually risen in N layers.
Further, the InxGa1-xN layers and the AlyGa1-yN layers of growth pressure is 100~200torr.
Further, the InxGa1-xN layers of growth temperature is 900 DEG C, the AlyGa1-yN layers of growth temperature is 970
℃。
Further, described to grow the electronic barrier layer, further include：
Growing the InxGa1-xN layers and the AlyGa1-yMg, the In are mixed at N layersxGa1-xN layers and described
AlyGa1-yThe doping concentration of Mg is 1 × 10 in N layers17~1 × 1018cm-3。
Further, the thickness of the electronic barrier layer is 30~72nm.
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is：
Include the electronic barrier layer of the superlattice structure in N number of period by setting, the superlattice structure in each period includes
Close to the In of multiple quantum well layerxGa1-xN layers and the Al far from multiple quantum well layeryGa1-yN layers, 0.1≤x≤0.2,0≤y≤0.2.
Wherein, InxGa1-xThe content of In is less than the content of In in multiple quantum well layer in N layers, ensures InxGa1-xBarrier height in N layers is high
In the barrier height of multiple quantum well layer, to stop that electronics is migrated to high temperature P-type layer so that more electronics are in multiple quantum wells strata
Collection.InxGa1-xContain In in N layers, the contact interface lattice of electronic barrier layer and multiple quantum well layer can be made to match, simultaneously
In can reduce the activation energy of Mg in electronic barrier layer, improve the activation capacity of Mg, to which the hole for improving P-type layer is dense
Degree.AlyGa1-yThe content of Al is continuously decreased or is gradually risen in N layers, then AlyGa1-yN layers of barrier height continuously decreases or gradually
It increases, can stop electronics overflow to P-type layer while reducing the barrier effect for hole so that electrons and holes are more preferable
Ground is limited in multiple quantum well layer and carries out radiation recombination.InxGa1-xN layers grow at 900~950 DEG C, and in the prior art
Electronic barrier layer is grown at 980 DEG C into comparing, and growth temperature is relatively low, can be improved in traditional LED structure since electronics hinders
Barrier growth temperature is excessively high, the problem of destroying the crystal of multiple quantum well layer, raw simultaneously to improve the lattice quality of multiple quantum well layer
Long temperature is relatively low, it is possible to reduce the precipitation of In in multiple quantum well layer, In contents increase in the potential well layer of multiple quantum well layer, then potential well
The energy gap of layer narrows, and the energy gap of barrier layer is wide, therefore the potential barrier of potential well layer and barrier layer is high in multiple quantum well layer
Degree difference becomes larger, and the depth of multiple quantum well layer increases, and improves the efficiency of electrons and holes recombination luminescence in multiple quantum well layer.Together
When AlyGa1-yN layers grow at 950~980 DEG C, and growth temperature is compared with InxGa1-xN floor heights, are conducive to AlyGa1-yIn N layers
The incorporation of Al, and due to AlyGa1-yThe N layers of In that low temperature is equipped between multiple quantum well layerxGa1-xN layers, multiple quantum wells is not interfered with
The lattice quality of layer.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
An embodiment of the present invention provides a kind of LED epitaxial slice, Fig. 1 is a kind of hair provided in an embodiment of the present invention
The structural schematic diagram of optical diode epitaxial wafer, as shown in Figure 1, the gallium nitride based light emitting diode includes substrate 1 and layer successively
It is stacked in buffer layer 2 on substrate 1, undoped GaN layer 3, N-type layer 4, multiple quantum well layer 5, electronic barrier layer 6, high temperature P-type layer 7
With p-type contact layer 8.
Wherein, electronic barrier layer 6 is the superlattice structure for including N number of period, and the superlattice structure in each period includes leaning on
The In of nearly multiple quantum well layerxGa1-xThe Al of N layers 61 and separate multiple quantum well layer 5yGa1-yN layers 62,0.1≤x≤0.2,0≤y≤
0.2, InxGa1-xThe content of In is less than the content of In in multiple quantum well layer 5, Al in N layers 61yGa1-yThe content of Al is gradual in N layers 62
It reduces or gradually rises, InxGa1-xN layers 61 are grown at 900~950 DEG C, AlyGa1-yN layers 62 are raw at 950~980 DEG C
Length forms, 5≤N≤12.
The embodiment of the present invention by setting include N number of period superlattice structure electronic barrier layer, each period surpass
Lattice structure includes the In close to multiple quantum well layerxGa1-xN layers and the Al far from multiple quantum well layeryGa1-yN layers, 0.1≤x≤
0.2,0≤y≤0.2.Wherein, InxGa1-xThe content of In is less than the content of In in multiple quantum well layer in N layers, ensures InxGa1-xN layers
In barrier height be higher than multiple quantum well layer barrier height, with stop electronics to high temperature P-type layer migrate so that more electronics
Assemble in multiple quantum well layer.InxGa1-xContain In in N layers, can make the contact interface of electronic barrier layer and multiple quantum well layer
Lattice matches, while In can reduce the activation energy of Mg in electronic barrier layer, improves the activation capacity of Mg, to improve
The hole concentration of P-type layer.AlyGa1-yThe content of Al is continuously decreased or is gradually risen in N layers, then AlyGa1-yN layers of barrier height
It continuously decreases or gradually rises, can stop electronics overflow to P-type layer while reducing the barrier effect for hole so that
Electrons and holes are preferably limited in multiple quantum well layer and carry out radiation recombination.InxGa1-xN layers grown at 900~950 DEG C and
At compared with electronic barrier layer in the prior art grows at 980 DEG C and forms, growth temperature is relatively low, can improve traditional LED junction
Since electronic blocking layer growth temperature is excessively high in structure, the problem of destroying the crystal of multiple quantum well layer, to improve multiple quantum well layer
Lattice quality, while growth temperature is relatively low, it is possible to reduce the precipitation of In in multiple quantum well layer, In in the potential well layer of multiple quantum well layer
Content increases, then the energy gap of potential well layer narrows, and the energy gap of barrier layer is wide, thus in multiple quantum well layer potential well layer and
The barrier height difference of barrier layer becomes larger, and the depth of multiple quantum well layer increases, and it is multiple in multiple quantum well layer to improve electrons and holes
Close luminous efficiency.Al simultaneouslyyGa1-yN layers grow at 950~980 DEG C, and growth temperature is compared with InxGa1-xN floor heights, have
Conducive to AlyGa1-yThe incorporation of Al in N layers, and due to AlyGa1-yThe N layers of In that low temperature is equipped between multiple quantum well layerxGa1-xN layers,
The lattice quality of multiple quantum well layer is not interfered with.
Preferably, x=0.1, i.e. InxGa1-xThe content of In is 0.1 in N layers 61.If the too high levels of In, grow
The lattice quality of electronic barrier layer 6 is poor, if the content of In is too low, InxGa1-xLattice between N layers 61 and multiple quantum well layer 5
Mismatch is big.
Wherein, InxGa1-xThe content that the content of In is less than In in multiple quantum well layer 6 in N layers 61 refers to InxGa1-xN layers 61
The content of middle In is less than the average content of In in multiple quantum well layer 5.
Preferably, 7≤N≤12.If the value of N is more than 12, the thickness of electronic barrier layer 6 can be caused thicker, then epitaxial wafer
Integral thickness it is larger, the luminous efficiency of LED can be reduced, and material can be wasted, increase growth time.If the value of N is less than 7,
Then electronic barrier layer 6 can not play the role of stopping that electronics is spilled over to P-type layer.
Further, the thickness of electronic barrier layer 6 is 30~72nm.If the thickness of electronic barrier layer 6 is less than 30nm, electricity
Sub- barrier layer 6 cannot play the role of stopping that electronics is spilled over to P-type layer, if the thickness of electronic barrier layer 6 is more than 72nm, cause
The integral thickness of epitaxial wafer is larger, can reduce the luminous efficiency of LED, and can waste material, increases growth time.
Further, InxGa1-xThe thickness of N layers 61 is 2~5nm, AlyGa1-yThe thickness of N layers 62 is 2~5nm.
Optionally, InxGa1-xThe thickness and Al of N layers 61yGa1-yThe thickness of N layers 62 is identical.
Preferably, the thickness of electronic barrier layer 6 is 50nm, wherein InxGa1-xThe thickness of N layers 61 is 5nm, AlyGa1-yN layers
62 thickness is 5nm, N=5.The recombination luminescence of electrons and holes is efficient at this time, and the luminous efficiency of LED is good.
Preferably, InxGa1-xN layers 61 are grown at 900 DEG C.If InxGa1-xThe growth temperature of N layers 61 is higher than 900
DEG C, then the crystal quality of multiple quantum well layer 5 can be destroyed, if InxGa1-xThe growth temperature of N layers 61 is less than 900 DEG C, then grows out
InxGa1-xThe crystal quality of N layers 61 is poor.
Preferably, AlyGa1-yN layers 62 are grown at 970 DEG C.If AlyGa1-yThe growth temperature of N layers 62 is higher than 970
DEG C, then the crystal quality of the electronic barrier layer 6 grown can be influenced, if InxGa1-xThe growth temperature of N layers 61 is less than 970 DEG C, then
It is unfavorable for AlyGa1-yThe incorporation of Al, Al in N layers 62yGa1-yThe potential barrier of N layers 62 reduces, and reduces AlyGa1-y62 pairs of electronics of N layers
Barrier effect.
Further, InxGa1-xN layers 61 and AlyGa1-yMixed with Mg, In in N layers 62xGa1-xN layers 61 and AlyGa1-yN layers
The doping concentration of Mg is 1 × 10 in 6217~1 × 1018cm-3.Mg is mixed in electronic barrier layer 6 can improve the concentration in hole,
To improve the recombination luminescence efficiency of electronics and hole.
Wherein, InxGa1-xN layers 61 and AlyGa1-yThe doping concentration of Mg can be identical or different in N layers 62.
Optionally, high temperature P-type layer 7 is to mix the GaN layer of Mg, and the doping concentration of Mg is 1 × 10 in high temperature P-type layer 719~1 ×
1020cm-3, the thickness of high temperature P-type layer 7 is 20~30nm.
Optionally, buffer layer 2 is GaN layer, and the thickness of buffer layer is 20~30nm.
Optionally, the thickness of undoped GaN layer 3 is 1~2 μm.
Optionally, the thickness of N-type layer 4 is 1~5 μm, and N-type layer 4 be to mix the GaN layer of Si, the doping concentration of Si can for 1 ×
1018~1 × 1019cm-3。
Optionally, multiple quantum well layer 5 is the superlattice structure for including InGaN potential well layers and GaN barrier layers, multiple quantum well layer
5 periodicity is 8~10.Wherein, the thickness of every layer of InGaN potential well layer is 2~5nm, the thickness of every layer of GaN barrier layer is 10~
30nm。
Optionally, p-type contact layer 9 is the GaN layer for mixing Mg, and the doping concentration of Mg is 1 × 10 in p-type contact layer 919~1 ×
1020cm-3, the thickness of p-type contact layer 9 is 5~300nm.
Embodiment two
An embodiment of the present invention provides a kind of manufacturing method of LED epitaxial slice, it is suitable for what embodiment one provided
A kind of LED epitaxial slice, Fig. 2 are a kind of manufacturing methods of LED epitaxial slice provided in an embodiment of the present invention
Flow chart, as shown in Fig. 2, the manufacturing method includes：
Step 201 provides a substrate.
Specifically, substrate is sapphire, and thickness is 630-650 μm.
In the present embodiment, using Veeco K465i or C4MOCVD (Metal Organic Chemical Vapor
Deposition, metallo-organic compound chemical gaseous phase deposition) equipment realize LED growing method.Using high-purity H2(hydrogen)
Or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carrier gas, high-purity N H3As the sources N, trimethyl gallium (TMGa)
And triethyl-gallium (TEGa) is used as gallium source, trimethyl indium that indium source, silane (SiH4) is used as within (T minutes) to be used as N type dopant, front three
Base aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as P-type dopant.Chamber pressure is 100-600torr.
Specifically, which includes：
In a hydrogen atmosphere, high-temperature process Sapphire Substrate 5-20 minutes.Wherein, reaction chamber temperature is 1000-1200 DEG C,
Chamber pressure control carries out nitrogen treatment in 200-500torr, to Sapphire Substrate.
Step 202, on substrate grown buffer layer.
Specifically, after the completion of Sapphire Substrate high-temperature process, in Grown on Sapphire Substrates GaN buffer layers, GaN is slow
The thickness for rushing layer is 20~30nm, and growth temperature can be 500-700 DEG C.
Further, after having grown GaN buffer layers, reaction chamber temperature is increased to 1000-1100 DEG C, will be coated with buffer layer
Sapphire Substrate makes annealing treatment 10-15 minutes.
Step 203 grows undoped GaN layer on the buffer layer.
In the present embodiment, the thickness of undoped GaN layer is 1~2 μm.When growing undoped GaN layer, room temperature is reacted
Degree is 900~1200 DEG C, and chamber pressure is controlled in 100~500torr.
Step 204 grows N-type layer in undoped GaN layer.
In the present embodiment, N-type layer is to mix the GaN layer of Si, and thickness is 1~5 μm.When growing N-type layer, reaction chamber temperature is
900~1200 DEG C, chamber pressure is controlled in 100~500torr.Wherein, the doping concentration of Si is 1 × 1018~1 × 1019cm-3。
Step 205：Multiple quantum well layer is grown in N-type layer.
Multiple quantum well layer is the superlattice structure for including InGaN potential well layers and GaN barrier layers, the periodicity of multiple quantum well layer
It is 8~10.Wherein, the growth temperature of InGaN potential well layers is 720~800 DEG C, and growth pressure is 100~500Torr, thickness 2
The growth temperature of~5nm, GaN barrier layer is 850~950 DEG C, and growth pressure is 100~500Torr, and thickness is 10~30nm.
Step 206：Electronic barrier layer is grown on multiple quantum well layer.
Optionally, electronic barrier layer is the superlattice structure for including N number of period, and the superlattice structure in each period includes leaning on
The In of nearly multiple quantum well layerxGa1-xN layers and the Al far from multiple quantum well layeryGa1-yN layers, InxGa1-xN layers are InxGa1-xN layers,
0.1≤x≤0.2,0≤y≤0.2, InxGa1-xThe content of In is less than the content of In in multiple quantum well layer, Al in N layersyGa1-yN layers
The content of middle Al is continuously decreased or is gradually risen, InxGa1-xN layers of growth temperature is 900~950 DEG C, AlyGa1-yN layers of growth
Temperature is 950~980 DEG C, 5≤N≤12.
Preferably, x=0.1, i.e. InxGa1-xThe content of In is 0.1 in N layers.If the too high levels of In, the electricity grown
The lattice quality on sub- barrier layer is poor, if the content of In is too low, InxGa1-xThe N layers of lattice mismatch between multiple quantum well layer is big.
Wherein, InxGa1-xThe content of In is less than the average content of In in multiple quantum well layer in N layers.
Preferably, 7≤N≤12.If the value of N is more than 12, the thickness of electronic barrier layer can be caused thicker, then epitaxial wafer
Integral thickness is larger, can reduce the luminous efficiency of LED, and can waste material, increases growth time.If the value of N is less than 7,
Electronic barrier layer can not play the role of stopping that electronics is spilled over to P-type layer.
Further, the thickness of electronic barrier layer is 30~72nm.If the thickness of electronic barrier layer is less than 30nm, electronics
Barrier layer cannot play the role of stopping that electronics is spilled over to P-type layer, if the thickness of electronic barrier layer is more than 72nm, lead to extension
The integral thickness of piece is larger, can reduce the luminous efficiency of LED, and can waste material, increases growth time.
Further, InxGa1-xN layers of thickness is 2~5nm, AlyGa1-yN layers of thickness is 2~5nm.
Optionally, InxGa1-xN layers of thickness and AlyGa1-yN layers of thickness is identical.
Preferably, the thickness of electronic barrier layer is 50nm, wherein InxGa1-xN layers of thickness is 5nm, AlyGa1-yN layers
Thickness is 5nm, N=5.The recombination luminescence efficiency highest of electrons and holes, the luminous efficiency of LED are best at this time.
Preferably, InxGa1-xN layers grow at 900 DEG C.If InxGa1-xN layers of growth temperature is higher than 900 DEG C, then
The crystal quality of multiple quantum well layer can be destroyed, if InxGa1-xN layers of growth temperature is less than 900 DEG C, then the In to grow outxGa1- xN layers of crystal quality is poor.
Preferably, AlyGa1-yN layers grow at 970 DEG C.If AlyGa1-yN layers of growth temperature is higher than 970 DEG C, then
The crystal quality of the electronic barrier layer grown can be influenced, if InxGa1-xN layers of growth temperature is less than 970 DEG C, then is unfavorable for
AlyGa1-yThe incorporation of Al, Al in N layersyGa1-yN layers of potential barrier reduces, and reduces AlyGa1-yThe N layers of barrier effect to electronics.
Further, InxGa1-xN layers and AlyGa1-yN layers of growth pressure is 100~250torr, wherein InxGa1-xN
Layer and AlyGa1-yN layers of growth pressure is equal, then saves growth without switching growth pressure in electronic barrier layer growth course
Time.
Further, step 206 further includes：
In growth InxGa1-xN layers and AlyGa1-yMg, In are mixed at N layersxGa1-xN layers and AlyGa1-yThe doping of Mg in N layers
Concentration is 1 × 1017~1 × 1018cm-3, to improve the recombination luminescence efficiency of electronics and hole.
Step 207 grows high temperature P-type layer on electronic barrier layer.
Optionally, high temperature P-type layer is to mix the GaN layer of Mg, and the doping concentration of Mg is 1 × 10 in high temperature P-type layer19~1 ×
1020cm-3, growth temperature is 900~1000 DEG C, growth pressure 100-300Torr, and thickness is 100~800nm.
Step 208, the growing P-type contact layer in high temperature P-type layer.
Optionally, p-type contact layer is the GaN layer for mixing Mg, and the doping concentration of Mg is 1 × 10 in p-type contact layer19~1 ×
1020cm-3, growth temperature is 850~1050 DEG C, and growth pressure is 100~300Torr, and thickness is 5~300nm.
After the growth for terminating LED epitaxial slice, temperature in MOCVD device is reduced to 650~850 DEG C,
Annealing is carried out 5~15 minutes to the LED epitaxial slice under nitrogen atmosphere.Then, temperature is gradually decreased to room temperature.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate and is cascading in institute
State buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, electronic barrier layer, high temperature P-type layer and the p-type contact on substrate
Layer, which is characterized in that
The electronic barrier layer is the superlattice structure for including N number of period, and the superlattice structure in each period includes close to described
The In of multiple quantum well layerxGa1-xN layers and the Al far from the multiple quantum well layeryGa1-yN layers, 0.1≤x≤0.2,0≤y≤0.2,
The InxGa1-xThe content of In is less than the content of In in the multiple quantum well layer, the Al in N layersyGa1-yThe content of Al in N layers
It continuously decreases or gradually rises, the InxGa1-xN layers grow at 900~950 DEG C, the AlyGa1-yN layers 950~
It is grown at 980 DEG C, 5≤N≤12.
2. LED epitaxial slice according to claim 1, which is characterized in that the thickness of the electronic barrier layer is 30
~72nm.
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that the InxGa1-xN layers of thickness is
2.5~3nm, the AlyGa1-yN layers of thickness is 2.5~3nm.
4. LED epitaxial slice according to claim 1 or 2, which is characterized in that the InxGa1-xN layers at 900 DEG C
Under grow, the AlyGa1-yN layers grow at 970 DEG C.
5. LED epitaxial slice according to claim 1 or 2, which is characterized in that the InxGa1-xN layers and described
AlyGa1-yMixed with Mg, the In in N layersxGa1-xN layers and the AlyGa1-yThe doping concentration of Mg is 1 × 10 in N layers17~1
×1018cm-3。
6. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes：
One substrate is provided；
Grown buffer layer, undoped GaN layer, N-type layer, multiple quantum well layer, electronic barrier layer, high temperature successively over the substrate
P-type layer and p-type contact layer；
Wherein, the electronic barrier layer is grown, including：Grow the superlattices knot in N number of period successively on the multiple quantum well layer
Structure, 5≤N≤12；Wherein, the superlattice structure in each period is grown in the following way：
Under conditions of growth temperature is 900~950 DEG C, In is grownxGa1-xN layers, 0.1≤x≤0.2, the InxGa1-xIn N layers
The content of In is less than the content of In in the multiple quantum well layer；
Under conditions of growth temperature is 950~980 DEG C, in the InxGa1-xAl is grown on N layersyGa1-yN layers, 0≤y≤0.2,
The AlyGa1-yThe content of Al is continuously decreased or is gradually risen in N layers.
7. manufacturing method according to claim 6, which is characterized in that the InxGa1-xN layers and the AlyGa1-yN layers
Growth pressure is 100~250torr.
8. the manufacturing method described according to claim 6 or 7, which is characterized in that the InxGa1-xN layers of growth temperature is 900
DEG C, the AlyGa1-yN layers of growth temperature is 970 DEG C.
9. the manufacturing method described according to claim 6 or 7, which is characterized in that the growth electronic barrier layer also wraps
It includes：
Growing the InxGa1-xN layers and the AlyGa1-yMg, the In are mixed at N layersxGa1-xN layers and the AlyGa1-yN layers
The doping concentration of middle Mg is 1 × 1017~1 × 1018cm-3。
10. the manufacturing method described according to claim 6 or 7, which is characterized in that the thickness of the electronic barrier layer be 30~
72nm。
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| CN111599902A (en) * | 2020-06-23 | 2020-08-28 | 东南大学 | Light-emitting diode with hole injection structure electron barrier layer |
| CN115132892A (en) * | 2021-12-30 | 2022-09-30 | 淮安澳洋顺昌光电技术有限公司 | Light emitting diode epitaxial structure and light emitting diode |
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