CN108198921B - A kind of gallium nitride based LED epitaxial slice and its manufacturing method - Google Patents
A kind of gallium nitride based LED epitaxial slice and its manufacturing method Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 59
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 62
- 230000003247 decreasing effect Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 12
- 229910021478 group 5 element Inorganic materials 0.000 description 11
- 230000008569 process Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 239000011777 magnesium Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a kind of gallium nitride based LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Electronic barrier layer in epitaxial wafer includes the first sublayer being stacked in low temperature P-type layer, the second sublayer, third sublayer and the 4th sublayer, and the first sublayer is InxGa1‑xN layers, 0 < x < 1, the second sublayer is GaN layer, and third sublayer is AlyGa1‑yN layers, 0 < y < 1,4th sublayer is AlN layers, wherein the content of the In in the first sublayer is gradually decreased from the side close to low temperature P-type layer to the side far from low temperature P-type layer, and the content of the first In in sublayer is less than the content of the In in multiple quantum well layer, the content of Al gradually rises from the side close to low temperature P-type layer to the side far from low temperature P-type layer in third sublayer.Then the barrier height of electronic barrier layer entirety gradually increases, and electronic barrier layer increases obvious, to be finally transferred in multiple quantum well layer hole concentration increase in low barrier region Two-Dimensional Hole air tightness, substantially increases the luminous efficiency of LED chip.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of gallium nitride based LED epitaxial slice and its manufacture
Method.
Background technique
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.As
A kind of efficient, environmentally friendly, green New Solid lighting source, is widely applied rapidly, such as traffic lights, automobile
Inside and outside lamp, landscape light in city, cell phone back light source etc., improving chip light emitting efficiency is the target that LED is constantly pursued.
LED epitaxial wafer is the important component in LED, and existing GaN-based LED epitaxial wafer includes substrate and setting
Epitaxial layer on substrate, epitaxial layer include be cascading low temperature buffer layer on substrate, high temperature buffer layer, N-type layer,
Multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, the electronics generated in N-type layer and P-type layer
The hole of middle generation is migrated to multiple quantum well layer under the action of electric field force, and radiation recombination hair occurs in multiple quantum well layer
Light.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
With the increase of gallium nitride based LED operating current, current density is increased with it, under this high current density, note
Enter the electronics in multiple quantum well layer also to increase therewith, leads to that part electronics fails and hole is compound in multiple quantum well layer and migrate
Into p-type GaN carrier layer, the degree of electronics spill and leakage is caused to increase, the antistatic effect of LED is deteriorated, luminous efficiency decline.
Summary of the invention
LED is under high current density in order to solve in the prior art, the low problem of luminous efficiency, and the embodiment of the present invention provides
A kind of gallium nitride based LED epitaxial slice and its manufacturing method.The technical solution is as follows:
On the one hand, the present invention provides a kind of gallium nitride based LED epitaxial slice, two poles of gallium nitride base light emitting
Pipe epitaxial wafer includes substrate and the low temperature buffer layer over the substrate of being cascading, high temperature buffer layer, N-type layer, shallow
Well layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, which is characterized in that
The electronic barrier layer includes the first sublayer, the second sublayer, third being stacked in the low temperature P-type layer
Layer and the 4th sublayer, first sublayer are InxGa1-xN layers, 0 < x < 1, second sublayer is GaN layer, the third sublayer
For AlyGa1-yN layers, 0 < y < 1, the 4th sublayer is AlN layers, wherein the content of the In in first sublayer is from close to described
The side of low temperature P-type layer is gradually decreased to the side far from the low temperature P-type layer, and the content of the In in first sublayer is small
The content of In in the multiple quantum well layer, the content of Al is from the side close to the low temperature P-type layer in the third sublayer
It is gradually risen to the side far from the low temperature P-type layer.
Further, the electronic barrier layer with a thickness of 17-50nm.
Further, first sublayer with a thickness of 1~10nm, second sublayer with a thickness of 10~20nm, institute
State third sublayer with a thickness of 5~15nm, the 4th sublayer with a thickness of 1~5nm.
Further, 0.3≤x≤0.5,0.1≤y≤0.3.
On the other hand, the present invention provides a kind of manufacturing method of gallium nitride based LED epitaxial slice, the manufactures
Method includes:
One substrate is provided；
Successively growing low temperature buffer layer, high temperature buffer layer, N-type layer, shallow well layer, multiple quantum well layer, low temperature p-type on substrate
Layer, P-type electron barrier layer, high temperature P-type layer and p-type contact layer, the electronic barrier layer include being stacked in the low temperature p-type
The first sublayer, the second sublayer, third sublayer and the 4th sublayer on layer, first sublayer are InxGa1-xN layers, 0 < x < 1, institute
Stating the second sublayer is GaN layer, and the third sublayer is AlyGa1-yN layers, 0 < y < 1, the 4th sublayer is AlN layers, wherein described
The content of In in first sublayer is gradually dropped from the side close to the low temperature P-type layer to the side far from the low temperature P-type layer
It is low, and the content of the In in first sublayer is less than the content of the In in the multiple quantum well layer, Al in the third sublayer
Content gradually risen from the side close to the low temperature P-type layer to far from the side of the low temperature P-type layer.
Further, the electronic barrier layer with a thickness of 17-50nm.
Further, first sublayer with a thickness of 1~10nm, second sublayer with a thickness of 10~20nm, institute
State third sublayer with a thickness of 5~15nm, the 4th sublayer with a thickness of 1~5nm.
Further, the growth pressure of the electronic barrier layer is 50~230torr.
Further, the growth temperature of the electronic barrier layer is 850~1000 DEG C, the growth temperature of the 4th sublayer
It is 20~40 DEG C higher than the growth temperature of the third sublayer, the growth of the growth temperature of the third sublayer than second sublayer
Temperature is 20~40 DEG C high, and the growth temperature of second sublayer is 20~40 DEG C higher than the growth temperature of first sublayer.
Further, the first sublayer temperature is 850~870 DEG C, and the second sublayer temperature is 880~900 DEG C, institute
920~940 DEG C of third sublayer temperature is stated, the 4th sublayer temperature is 950~1000 DEG C.
Technical solution provided in an embodiment of the present invention has the benefit that
By growing electronic barrier layer in low temperature P-type layer, electronic barrier layer is made of four sublayers, and four sublayers include
First sublayer, the second sublayer, third sublayer and the 4th sublayer, wherein the first sublayer is InxGa1-xN layers, 0 < x < 1, the first sublayer
In the content of In gradually decreased from the side close to low temperature P-type layer to far from the side of low temperature P-type layer, prevent in the first sublayer
In spread to high temperature P-type layer, lower the luminous efficiency of light emitting diode, and the content of the In in the first sublayer is less than Multiple-quantum
The content of In in well layer guarantees that the barrier height in the first sublayer is higher than the barrier height of multiple quantum well layer, to stop electronics
It is migrated to high temperature P-type layer, so that more electronics are assembled in multiple quantum well layer.Second sublayer is GaN layer, In can be prevented to height
It is spread in warm P-type layer, to improve the luminous efficiency of light emitting diode.Third sublayer is AlyGa1-yN layers, 0 < y < 1, third
The content of Al gradually rises from the side close to low temperature P-type layer to the side far from low temperature P-type layer in layer, so that third sublayer
Barrier height close to the side of multiple quantum well layer is lower than the barrier height of the side of the close high temperature P-type layer of third sublayer, then
Electronics can assembled in multiple quantum well layer, substantially increase combined efficiency of the electrons and holes in multiple quantum well layer, improve
The luminous efficiency of LED chip.4th sublayer is AlN layers, and AlN layers of barrier height is higher, and electronics can be stopped to high temperature P-type layer
It is mobile, combined efficiency of the electrons and holes in multiple quantum well layer is further improved, the luminous efficiency of LED chip is improved.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of process of the preparation method of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention
Figure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
The embodiment of the invention provides a kind of gallium nitride based LED epitaxial slice, Fig. 1 is that the embodiment of the present invention provides
A kind of gallium nitride based LED epitaxial slice structural schematic diagram, as shown in Figure 1, the gallium nitride based light emitting diode includes
Substrate 1 and the low temperature buffer layer 2 being sequentially laminated on substrate 1, high temperature buffer layer 3, N-type layer 4, shallow well layer 5, multiple quantum wells
Layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature P-type layer 9 and p-type contact layer 10.
Wherein, electronic barrier layer 8 includes being stacked the first sublayer 81 in low temperature P-type layer 7, the second sublayer 82, the
Three sublayers 83 and the 4th sublayer 84, the first sublayer 81 are InxGa1-xN layers, 0 < x < 1, the second sublayer 82 is GaN layer, third sublayer
83 be AlyGa1-yN layers, 0 < y < 1, the 4th sublayer 84 is AlN layers, wherein the content of the In in the first sublayer 81 is from close to low temperature P
The side of type layer is gradually decreased to the side far from low temperature P-type layer, and the content of the In in the first sublayer 81 is less than multiple quantum wells
The content of In in layer 6, the content of Al is from the side close to low temperature P-type layer to one far from low temperature P-type layer in third sublayer 83
Side gradually rises.
The embodiment of the present invention is made of by growing electronic barrier layer, electronic barrier layer in low temperature P-type layer four sublayers,
Four sublayers include the first sublayer, the second sublayer, third sublayer and the 4th sublayer, wherein the first sublayer is InxGa1-xN layers, 0 <
The content of x < 1, the In in the first sublayer are gradually decreased from the side close to low temperature P-type layer to the side far from low temperature P-type layer, are prevented
Only the In in the first sublayer is spread to high temperature P-type layer, lower the luminous efficiency of light emitting diode, and the In in the first sublayer contains
Amount is less than the content of the In in multiple quantum well layer, guarantees that the barrier height in the first sublayer is higher than the potential barrier height of multiple quantum well layer
Degree, to stop electronics to migrate to high temperature P-type layer, so that more electronics are assembled in multiple quantum well layer.Second sublayer is GaN layer,
It can prevent In from spreading into high temperature P-type layer, to improve the luminous efficiency of light emitting diode.Third sublayer is AlyGa1-y N
Layer, 0 < y < 1, the content of Al gradually rises from the side close to low temperature P-type layer to the side far from low temperature P-type layer in third sublayer
Height, so that the barrier height of the side of the close multiple quantum well layer of third sublayer is lower than the close high temperature P-type layer of third sublayer
The barrier height of side, then electronics can assembled in multiple quantum well layer, substantially increase electrons and holes in multiple quantum well layer
Combined efficiency, improve the luminous efficiency of LED chip.4th sublayer is AlN layers, and AlN layers of barrier height is higher, can hinder
It is mobile to high temperature P-type layer to keep off electronics, further improves combined efficiency of the electrons and holes in multiple quantum well layer, improves
The luminous efficiency of LED chip.
Further, electronic barrier layer 8 with a thickness of 17~50nm.
Preferably, the first sublayer 81 with a thickness of 1~10nm, the second sublayer 82 with a thickness of 10~20nm, third sublayer
83 with a thickness of 5~15nm, the 4th sublayer 84 with a thickness of 1~5nm.The thickness of first sublayer 81 is arranged it is relatively thin, can be with
It prevents the half-breadth of diode excessive, by the relatively thin of the thickness setting of the 4th sublayer 84, prevents the 4th sublayer 84 from can stop hole
Injection.
Preferably, 0.3≤x≤0.5,0.1≤y≤0.3, the illumination effect of diode is best at this time.
Optionally, substrate 1 can be Sapphire Substrate.
Optionally, low temperature buffer layer 2 can be GaN layer, with a thickness of 2~8nm.
Optionally, high temperature buffer layer 3 can be the GaN layer to undope, with a thickness of 1~2um.N-type layer 4 can be to mix Si's
GaN layer, with a thickness of 1.5~3.5um.
Optionally, shallow well layer 5 be include InaGa1-aThe superlattice structure of N (0 < a < 0.1) potential well layer and GaN barrier layer, shallowly
The periodicity of well layer 5 is 5~20.Wherein every layer of InaGa1-aN (0 < a < 0.1) potential well layer with a thickness of 1~4nm, every layer of GaN gesture
Barrier layer with a thickness of 10~30nm.
Optionally, multiple quantum well layer 6 be include InbGa1-bThe superlattices of N (0.2 <b < 0.5) potential well layer and GaN barrier layer
Structure, the periodicity of multiple quantum well layer 6 are 6~15.Wherein, every layer of InbGa1-bN (0.2 <b < 0.5) potential well layer with a thickness of 2~
5nm, every layer of GaN barrier layer with a thickness of 5~15nm.
Optionally, low temperature P-type layer 7 is the GaN layer with a thickness of 30~120nm, and high temperature P-type layer 9 is with a thickness of 50~150nm
GaN layer.
Optionally, p-type contact layer 10 with a thickness of 3~10nm.
Embodiment two
The embodiment of the invention provides a kind of manufacturing methods of gallium nitride based LED epitaxial slice, are suitable for embodiment
A kind of one gallium nitride based LED epitaxial slice provided, Fig. 2 is a kind of gallium nitride base light emitting provided in an embodiment of the present invention
The flow chart of the preparation method of diode epitaxial slice, as shown in Fig. 2, the manufacturing method includes:
Step 201 pre-processes substrate.
Optionally, substrate is sapphire, with a thickness of 630~650um.
In the present embodiment, using Veeco K465i or C4MOCVD (Metal Organic Chemical Vapor
Deposition, metallo-organic compound chemical gaseous phase deposition) equipment realize LED growing method.Using high-purity H2(hydrogen)
Or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carrier gas, high-purity N H3As the source N, trimethyl gallium (TMGa)
And triethyl-gallium (TEGa) is used as gallium source, trimethyl indium (TMIn) is used as indium source, and silane (SiH4) is used as N type dopant, front three
Base aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as P-type dopant.Chamber pressure is 100~600torr.
Specifically, which includes:
In a hydrogen atmosphere, 5~20min of high-temperature process substrate.Wherein, reaction chamber temperature is 1000~1200 DEG C, reaction
Chamber pressure control carries out nitrogen treatment in 200~500torr, to substrate.
Step 202, on substrate growing low temperature buffer layer.
Specifically, after the completion of Sapphire Substrate high-temperature process, reaction chamber temperature is dropped to 500~650 DEG C, growth thickness
For the low temperature buffer layer of 2~8nm.
When growing low temperature buffer layer, growth temperature can be 1000~1100 DEG C, and growth pressure is 50~200torr, raw
In growth process, the molar flow ratio of group-v element and group iii elements is 50~300, and growth revolving speed is 200~600r/min.
Step 203 grows high temperature buffer layer on low temperature buffer layer.
In the present embodiment, high temperature buffer layer is the GaN layer to undope, with a thickness of 1~2um.When growing high temperature buffer layer,
Reaction chamber temperature is 1000~1200 DEG C, and chamber pressure controls the group-v element and three in 100~500torr, growth course
The molar flow ratio of race's element is 200~3000.
Step 204 grows N-type layer on high temperature buffer layer.
In the present embodiment, N-type layer is to mix the GaN layer of Si, with a thickness of 1.5~3.5um.When growing N-type layer, room temperature is reacted
Degree is 950~1150 DEG C, and chamber pressure controls in 100~400torr, growth course, group-v element and group iii elements
Molar flow ratio is 400~5000.
Step 205: shallow well layer is grown in N-type layer.
In the present embodiment, shallow well layer be include InaGa1-aThe superlattices knot of N (0 < a < 0.1) potential well layer and GaN barrier layer
Structure, the periodicity of shallow well layer are 5~20, wherein InaGa1-aThe growth temperature of N potential well layer is 750~850 DEG C, and growth pressure is
100~500Torr, with a thickness of 1~4nm, in growth course, the molar flow ratio of group-v element and group iii elements is 500~
10000.The growth temperature of GaN barrier layer is 850~950 DEG C, and growth pressure is 100~500Torr, with a thickness of 10~30nm,
In growth course, the molar flow ratio of group-v element and group iii elements is 500~10000.
Step 206: growing multiple quantum well layer on shallow well layer.
Multiple quantum well layer be include InbGa1-bThe superlattice structure of N (0.2 <b < 0.5) potential well layer and GaN barrier layer, volume
The periodicity of sub- well layer is 6~15.Wherein, InbGa1-bThe growth temperature of N potential well layer is 700~850 DEG C, growth pressure 100
~500Torr, with a thickness of 2~5nm, in growth course, the molar flow ratio of group-v element and group iii elements is 2000~
The growth temperature of 20000, GaN barrier layers is 850~950 DEG C, and growth pressure is 100~500Torr, raw with a thickness of 5~15nm
In growth process, the molar flow ratio of group-v element and group iii elements is 2000~20000.
Step 207: the growing low temperature P-type layer on multiple quantum well layer.
Optionally, low temperature P-type layer is GaN layer, and growth temperature is 700~800 DEG C, and growth pressure is 100~600Torr,
Growth time is 3~15min, and growth thickness is 30~120nm, in growth course, the molar flow of group-v element and group iii elements
Amount is than being 1000~4000.
Step 208, the growing P-type electronic barrier layer in low temperature P-type layer.
Optionally, electronic barrier layer includes the first sublayer, the second sublayer, third being stacked in low temperature P-type layer
Layer and the 4th sublayer, the first sublayer are InxGa1-xN layers, 0 < x < 0.3, the second sublayer is GaN layer, and third sublayer is AlyGa1-y N
Layer, 0 < y < 0.1, the 4th sublayer are AlN layer, wherein the content of the In in the first sublayer is from the side of close low temperature P-type layer to remote
Side from low temperature P-type layer gradually decreases, and the content of the In in the first sublayer is less than the content of the In in multiple quantum well layer, the
The content of Al gradually rises from the side close to low temperature P-type layer to the side far from low temperature P-type layer in three sublayers.
Specifically, when growing electronic barrier layer, electronic barrier layer with a thickness of 17~50nm.Wherein, first sublayer
With a thickness of 1~10nm, the second sublayer with a thickness of 10~20nm, third sublayer with a thickness of 5~15nm, the thickness of the 4th sublayer
For 1~5nm.
Further, the growth temperature of electronic barrier layer is 850~1000 DEG C.
Preferably, the growth temperature of electronic barrier layer is 850~980 DEG C.
It is highly preferred that the growth temperature of electronic barrier layer is 860~970 DEG C, the electronic barrier layer to grow out at this time
Blocking effect is best.
Wherein, the growth temperature of the 4th sublayer is 20~40 DEG C higher than the growth temperature of third sublayer, the growth of third sublayer
Temperature is 20~40 DEG C higher than the growth temperature of the second sublayer, and the growth temperature of the second sublayer is higher than the growth temperature of the first sublayer by 20
~40 DEG C.It should be noted that each sublayer is during the growth process, growth temperature is remained unchanged.
Preferably, 850~870 DEG C of the growth temperature of the first sublayer, the growth temperature of the second sublayer are 880~900 DEG C, the
The growth temperature of three sublayers is 920~940 DEG C, and the growth temperature of the 4th sublayer is 950~1000 DEG C.
Further, the growth pressure of electronic barrier layer is 50~300Torr.
Preferably, the growth pressure of electronic barrier layer is 100~250Torr.
It is highly preferred that the growth pressure of electronic barrier layer is 100~200Torr, the electronic barrier layer to grow out at this time
Blocking effect it is best.
Wherein, the growth pressure of the first sublayer, the second sublayer, third sublayer and the 4th sublayer is all the same.
Further, the growth time of electronic barrier layer is 4~15min, in growth course, group-v element and group iii elements
Molar flow ratio be 1000~10000.
Step 209 grows high temperature P-type layer on electronic barrier layer.
Optionally, high temperature P-type layer is GaN layer, and growth temperature is 900~1050 DEG C, and growth pressure is 100~500Torr,
Growth time is 10~20min, with a thickness of 50~150nm, in growth course, and the molar flow ratio of group-v element and group iii elements
It is 500~4000.
Step 210, the growing P-type contact layer in high temperature P-type layer.
Optionally, p-type contact layer is the GaN layer of heavily doped Mg, and the growth temperature of p-type contact layer is 700~850 DEG C, growth
Pressure is 100~500Torr, and growth time is 0.5~5min, with a thickness of 3~10nm, in growth course, and group-v element and three
The molar flow ratio of race's element is 10000~20000.
After the growth for terminating gallium nitride based LED epitaxial slice, the temperature of reaction chamber is down to 600~900
DEG C, in PN2Atmosphere carries out 10~30min of annealing, is then gradually decreased to room temperature, then, through over cleaning, deposition, photoetching and
The chip of single 9*27mil is made in etching subsequent machining technology.
Embodiment three
The embodiment of the invention provides a kind of manufacturing methods of gallium nitride based LED epitaxial slice, in the present embodiment
In, electronic barrier layer includes the first sublayer, the second sublayer, third sublayer and the 4th sublayer, and the first sublayer is InxGa1-xN layers,
0.3≤x≤0.5, the second sublayer are GaN layer, and third sublayer is AlyGa1-yN layers, 0.1≤y≤0.3, the 4th sublayer is AlN
Layer, wherein the content of the In in the first sublayer is gradually dropped from the side close to low temperature P-type layer to the side far from low temperature P-type layer
Low, and the content of the In in the first sublayer is less than the content of the In in multiple quantum well layer, the content of Al is from close in third sublayer
The side of low temperature P-type layer gradually rises to the side far from low temperature P-type layer.
After the growth for terminating gallium nitride based LED epitaxial slice, the temperature of reaction chamber is down to 600~900
DEG C, in PN2Atmosphere carries out 10~30min of annealing, is then gradually decreased to room temperature, then, through over cleaning, deposition, photoetching and
The chip of single 9*27mil is made in etching subsequent machining technology.
It is found after XRD (X-ray diffraction, X-ray diffraction method) test, it is provided in an embodiment of the present invention
For LED chip compared with the LED chip provided in embodiment two, the luminous efficiency of LED improves 1.5%.
Example IV
The embodiment of the invention provides a kind of manufacturing methods of gallium nitride based LED epitaxial slice, in the present embodiment
In, electronic barrier layer includes the first sublayer, the second sublayer, third sublayer and the 4th sublayer, and the first sublayer is InxGa1-xN layers,
0.5 < x < 0.8, the second sublayer are GaN layer, and third sublayer is AlyGa1-yN layers, 0.3 < y < 0.5, the 4th sublayer is AlN layers,
In the content of In in the first sublayer gradually decreased from the side close to low temperature P-type layer to the side far from low temperature P-type layer, and the
The content of In in one sublayer is less than the content of the In in multiple quantum well layer, and the content of Al is from close to low temperature p-type in third sublayer
The side of layer gradually rises to the side far from low temperature P-type layer.
After the growth for terminating gallium nitride based LED epitaxial slice, the temperature of reaction chamber is down to 600~900
DEG C, in PN2Atmosphere carries out 10~30min of annealing, is then gradually decreased to room temperature, then, through over cleaning, deposition, photoetching and
The chip of single 9*27mil is made in etching subsequent machining technology.
It finds after XRD is tested, is provided in the luminous efficiency and embodiment three of LED chip provided in an embodiment of the present invention
The luminous efficiency of LED chip compare, reduce 0.6%.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of gallium nitride based LED epitaxial slice, the gallium nitride based LED epitaxial slice include substrate and
Low temperature buffer layer, high temperature buffer layer, N-type layer, shallow well layer, multiple quantum well layer, the low temperature P being cascading over the substrate
Type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, which is characterized in that
The electronic barrier layer include the first sublayer being stacked in the low temperature P-type layer, the second sublayer, third sublayer and
4th sublayer, first sublayer are InxGa1-xN layers, 0 < x < 1, second sublayer is GaN layer, and the third sublayer is
AlyGa1-yN layers, 0 < y < 1, the 4th sublayer is AlN layers, wherein the content of the In in first sublayer is from close to described low
The side of warm P-type layer is gradually decreased to the side far from the low temperature P-type layer, and the content of the In in first sublayer is less than
The content of In in the multiple quantum well layer, in the third sublayer content of Al from the side close to the low temperature P-type layer to
Side far from the low temperature P-type layer gradually rises.
2. gallium nitride based LED epitaxial slice according to claim 1, which is characterized in that the electronic barrier layer
With a thickness of 17~50nm.
3. gallium nitride based LED epitaxial slice according to claim 1 or 2, which is characterized in that first sublayer
With a thickness of 1~10nm, second sublayer with a thickness of 10~20nm, the third sublayer with a thickness of 5~15nm, it is described
4th sublayer with a thickness of 1~5nm.
4. gallium nitride based LED epitaxial slice according to claim 1 or 2, which is characterized in that 0.3≤x≤0.5,
0.1≤y≤0.3。
5. a kind of manufacturing method of gallium nitride based LED epitaxial slice, the manufacturing method include:
One substrate is provided；
On substrate successively growing low temperature buffer layer, high temperature buffer layer, N-type layer, shallow well layer, multiple quantum well layer, low temperature P-type layer,
Electronic barrier layer, high temperature P-type layer and p-type contact layer；
It is characterized in that, the electronic barrier layer includes the first sublayer being stacked in the low temperature P-type layer, the second son
Layer, third sublayer and the 4th sublayer, first sublayer are InxGa1-xN layers, 0 < x < 1, second sublayer is GaN layer, described
Third sublayer is AlyGa1-yN layers, 0 < y < 1, the 4th sublayer be AlN layers, wherein the content of the In in first sublayer from
It is gradually decreased close to the side of the low temperature P-type layer to the side far from the low temperature P-type layer, and the In in first sublayer
Content be less than the content of the In in the multiple quantum well layer, the content of Al is from close to the low temperature p-type in the third sublayer
The side of layer gradually rises to the side far from the low temperature P-type layer.
6. manufacturing method according to claim 5, which is characterized in that the electronic barrier layer with a thickness of 17~50nm.
7. manufacturing method according to claim 6, which is characterized in that first sublayer with a thickness of 1~10nm, it is described
Second sublayer with a thickness of 10~20nm, the third sublayer with a thickness of 5~15nm, the 4th sublayer with a thickness of 1~
5nm。
8. manufacturing method according to claim 6 or 7, which is characterized in that the growth pressure of the electronic barrier layer is 50
~230torr.
9. manufacturing method according to claim 6 or 7, which is characterized in that the growth temperature of the electronic barrier layer is 850
~1000 DEG C, the growth temperature of the 4th sublayer is 20~40 DEG C higher than the growth temperature of the third sublayer, third
The growth temperature of layer is 20~40 DEG C higher than the growth temperature of second sublayer, and the growth temperature of second sublayer is than described the
The growth temperature of one sublayer is 20~40 DEG C high.
10. manufacturing method according to claim 9, which is characterized in that the first sublayer temperature is 850~870 DEG C, institute
State the second sublayer temperature be 880~900 DEG C, described 920~940 DEG C of third sublayer temperature, the 4th sublayer temperature be 950~
1000℃。
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| CN110137319A (en) * | 2019-05-21 | 2019-08-16 | 芜湖德豪润达光电科技有限公司 | LED epitaxial structure and preparation method thereof |
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