CN108831974A - A kind of LED epitaxial slice and its manufacturing method - Google Patents
A kind of LED epitaxial slice and its manufacturing method Download PDFInfo
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- CN108831974A CN108831974A CN201810395843.4A CN201810395843A CN108831974A CN 108831974 A CN108831974 A CN 108831974A CN 201810395843 A CN201810395843 A CN 201810395843A CN 108831974 A CN108831974 A CN 108831974A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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Abstract
The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Including substrate, buffer layer, undoped GaN layer, N-type layer, active layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer, electronic barrier layer is the Al for including N number of periodxGa1‑xN/AlN/GaN/InyGa1‑ yN superlattice structure, N are positive integer more than or equal to 2, electronic barrier layer with a thickness of 10~25nm.Compared with electronic barrier layer of the existing thickness greater than 50nm, the thickness of electronic barrier layer provided by the invention greatly reduces, and then reduce the polarization and stress of storeroom, reduce the Valence-band Offsets that electronic barrier layer is generated in valence band heterojunction boundary, hole is enabled preferably to inject active layer, then the concentration in hole increases, and more holes can improve the luminous efficiency of LED in active layer with electronics recombination luminescence.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its manufacturing method.
Background technique
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.As
A kind of efficient, environmentally friendly, green New Solid lighting source, is widely applied rapidly, such as traffic lights, automobile
Inside and outside lamp, landscape light in city, cell phone back light source etc..
Epitaxial wafer is the main composition part in LED, and existing GaN base LED epitaxial wafer includes substrate and is arranged in substrate
On GaN base epitaxial layer, GaN base epitaxial layer includes buffer layer, undoped GaN layer, the N-type layer (N stacked gradually on substrate
Type area), active layer, electronic barrier layer, high temperature P-type layer (p type island region) and p-type contact layer.The electronics and p type island region that N-type region provides mention
The hole of confession is in active layer recombination luminescence.Wherein electronic barrier layer is usually AlGaN layer or the AlGaN/InGaN in multiple periods super
The thickness of lattice structure, electronic barrier layer is greater than 50nm.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems：
In existing LED epitaxial wafer, electronic barrier layer is designed thicker (typically larger than 50nm), thicker electronic barrier layer
It will lead to the polarization and stress of storeroom, while a high valence band can be generated, hole is hindered to migrate to active layer, therefore N
The concentration in hole of the concentration than providing in p type island region for the electronics that type area provides is high, and the mobility ratio hole of electronics is many fastly, causes
The recombination luminescence efficiency of electrons and holes reduces, so that the luminous efficiency of LED reduces.
Summary of the invention
In order to solve the problem of that electronic barrier layer is designed thicker so that the luminous efficiency of LED reduces, originally in the prior art
Inventive embodiments provide a kind of LED epitaxial slice and its manufacturing method.The technical solution is as follows：
On the one hand, the present invention provides a kind of LED epitaxial slice, the LED epitaxial slice includes substrate,
And buffer layer, undoped GaN layer, N-type layer, active layer, low temperature P-type layer, the electronics stacked gradually over the substrate hinders
Barrier, high temperature P-type layer and p-type contact layer, the low temperature P-type layer are GaN layer,
The electronic barrier layer is the Al for including N number of periodxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<
x<0.15,0.2<y<0.4, N is positive integer more than or equal to 2, the electronic barrier layer with a thickness of 10~25nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yEach Al in N superlattice structurexGa1-xN sublayer
With a thickness of 0.5~1.5nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each AlN sublayer in N superlattice structure
For 0.5~1.5nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each GaN sublayer in N superlattice structure
For 1~2nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yEach In in N superlattice structureyGa1-yN sublayer
With a thickness of 1~2nm.
Further, 2≤N≤5.
Further, x=0.1, y=0.38.
On the other hand, the embodiment of the invention provides a kind of manufacturing method of LED epitaxial slice, the manufacturers
Method includes：
One substrate is provided；
Successively grown buffer layer, undoped GaN layer, N-type layer, active layer and low temperature P-type layer over the substrate, it is described
Low temperature P-type layer is GaN layer；
Electronic barrier layer is grown in the low temperature P-type layer, the electronic barrier layer is the Al for including N number of periodxGa1- xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15,0.2<y<0.4, N is the positive integer more than or equal to 2, described
Electronic barrier layer with a thickness of 10~25nm；
High temperature P-type layer and p-type contact layer are grown on the electronic barrier layer.
Further, the growth temperature of the electronic barrier layer is 850~1080 DEG C.
Further, the growth pressure of the electronic barrier layer is 200~500Torr.
Technical solution bring beneficial effect provided in an embodiment of the present invention is：
Electronic barrier layer is arranged to include N number of period AlxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure,
In, since low temperature P-type layer is GaN layer, and the AlN layer in electronic barrier layer and low temperature p-type GaN layer lattice mismatch, therefore be arranged
AlxGa1-xN can reduce the lattice mismatch of electronic barrier layer Yu low temperature P-type layer as buffer layer.AlN layers are capable of forming one
Higher potential barrier energy level, stops the migration of electronics, simultaneously because the AlN layers of crystal lattice mismatch between GaN layer is big, therefore
AlN layers can produce certain two-dimensional electron gas between GaN layer, to provide more holes, and improve the migration of carrier
Rate.InyGa1-yThe N layers of generation that can be enhanced two-dimensional electron gas, further provide more holes, improve moving for carrier
Move rate.And the electronic blocking with a thickness of 10~25nm, with existing thickness greater than 50nm of the electronic barrier layer in the present invention
Layer is compared, and thickness greatly reduces, and then reduces the polarization and stress of storeroom, reduces the electronic blocking of high Al contents
The Valence-band Offsets that layer is generated in valence band heterojunction boundary, enable hole preferably to inject active layer, then the concentration in hole increases
Add, more holes can improve the luminous efficiency of LED in active layer with electronics recombination luminescence.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of method flow diagram of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slice, Fig. 1 is a kind of hair provided in an embodiment of the present invention
The structural schematic diagram of optical diode epitaxial wafer as shown in Figure 1, LED epitaxial slice includes substrate 1, and is sequentially laminated on
Buffer layer 2, undoped GaN layer 3 on substrate 1, N-type layer 4, active layer 5, low temperature P-type layer 6, electronic barrier layer 7, high temperature p-type
Layer 8 and p-type contact layer 9, low temperature P-type layer 6 are GaN layer.
Wherein, electronic barrier layer 7 is the Al for including N number of periodxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure,
0.05<x<0.15,0.2<y<0.4, N is positive integer more than or equal to 2, electronic barrier layer 7 with a thickness of 10~25nm.
By electronic barrier layer is arranged to include N number of period AlxGa1-xN/AlN/GaN/InyGa1-yN superlattices knot
Structure, wherein since low temperature P-type layer is GaN layer, and the AlN layer in electronic barrier layer and low temperature p-type GaN layer lattice mismatch, therefore
Al is setxGa1-xN can reduce the lattice mismatch of electronic barrier layer Yu low temperature P-type layer as buffer layer.AlN layers are capable of forming
One higher potential barrier energy level, stops the migration of electronics, simultaneously because the AlN layers of crystal lattice mismatch between GaN layer is big, because
This AlN layers can produce certain two-dimensional electron gas between GaN layer, to provide more holes, and improve moving for carrier
Move rate.InyGa1-yThe N layers of generation that can be enhanced two-dimensional electron gas, further provide more holes, improve carrier
Migration rate.And the electronics resistance with a thickness of 10~25nm, with existing thickness greater than 50nm of the electronic barrier layer in the present invention
Barrier is compared, and thickness greatly reduces, and then reduces the polarization and stress of storeroom, reduces the electronics resistance of high Al contents
The Valence-band Offsets that barrier is generated in valence band heterojunction boundary enable hole preferably to inject active layer, then the concentration in hole
Increase, more holes can improve the luminous efficiency of LED in active layer with electronics recombination luminescence.
Preferably, x=0.1, y=0.38.The luminous efficiency of LED is best at this time.
Specifically, in each Al of electronic barrier layer 7xGa1-xN/AlN/GaN/InyGa1-yInclude in N superlattice structure
AlxGa1-xN sublayer 71, AlN sublayer 72, GaN sublayer 73 and InyGa1-yN sublayer 74.
Further, each AlxGa1-xN sublayer 71 with a thickness of 0.5~1.5nm.If each AlxGa1-xThe thickness of N sublayer 71
Degree is less than 0.5nm, then the effect for reducing the lattice mismatch of electronic barrier layer 7 and low temperature P-type layer 6 is not had, if each AlxGa1- xThe thickness of N sublayer 71 is greater than 1.5nm, and it will cause wastes, and the thickness for also resulting in electronic barrier layer 7 is blocked up, influence LED's
Luminous efficiency.
Preferably, each AlxGa1-xN sublayer 71 with a thickness of 1nm.Can play at this time reduce electronic barrier layer 7 with it is low
The effect of lattice mismatch between warm P-type layer 6, and can guarantee that the thickness of electronic barrier layer 7 will not be blocked up, it causes to waste.
Further, each AlN sublayer 72 with a thickness of 0.5~1.5nm.If the thickness of each AlN sublayer 72 is less than
0.5nm does not have the effect for stopping electronics then.If the thickness of each AlN sublayer 72 is greater than 1.5nm, it will cause wastes, can also
Cause the thickness of electronic barrier layer 7 blocked up, influences the luminous efficiency of LED.
Preferably, each AlN sublayer 72 with a thickness of 1nm.It can play the role of stopping electronics at this time and guarantee
The thickness of electronic barrier layer 7 will not be blocked up, causes to waste.
Further, each GaN sublayer 73 with a thickness of 1~2nm.If the thickness of each GaN sublayer 73 is less than 1nm,
Certain two-dimensional electron gas can not be generated, to provide more holes, improves the migration rate of carrier, if each GaN sublayer
73 thickness is greater than 2nm, and it will cause wastes, and the thickness for also resulting in electronic barrier layer 7 is blocked up, influence the luminous efficiency of LED.
Preferably, each GaN sublayer 73 with a thickness of 1nm.At this time certain Two-dimensional electron can be generated with AlN sublayer 72
Gas improves the migration rate of carrier to provide more holes, and can guarantee that the thickness of electronic barrier layer 7 will not be blocked up,
It causes to waste.
Further, each InyGa1-yN sublayer 74 with a thickness of 1~2nm.If each InyGa1-yThe thickness of N sublayer 74 is small
In 1nm, then it can not enhance the generation of two-dimensional electron gas, if each InyGa1-yThe thickness of N sublayer 74 is greater than 2nm, and it will cause waves
Take, the thickness for also resulting in electronic barrier layer 7 is blocked up, influences the luminous efficiency of LED.
Preferably, each InyGa1-yN sublayer 74 with a thickness of 2nm.AlN sublayer 72 and GaN sublayer 73 can be helped at this time
Between generate more two-dimensional electron gas, it is further provided improve the migration rate of carrier, and can guarantee in more holes
The thickness of electronic barrier layer 7 will not be blocked up, causes to waste.
Wherein, 2≤N≤5.If N, less than 2, the thickness that will lead to electronic barrier layer 7 is excessively thin, blocking electronics can not be played,
Increase hole, improves the effect of the migration rate of carrier.If N is greater than 5, the thickness that will lead to electronic barrier layer 7 is blocked up, drop
The luminous efficiency of low LED.
Optionally, substrate 1 can be the Sapphire Substrate of (0001) crystal orientation.
Optionally, buffer layer 2 can be GaN layer, and thickness can be 15~35nm.
Optionally, the thickness of undoped GaN layer 3 can be 1~5um.
Optionally, N-type layer 4 can be to mix the GaN layer of Si, and wherein the doping concentration range of Si is 1018cm-3~1019cm-3；
The thickness of N-type layer 4 can be 1~5um.
Optionally, active layer 5 can be by the In in 5~11 periodsxGa1-x52 superlattice structure of N well layer 51 and GaN barrier layer
Composition, wherein every layer of InxGa1-xThe thickness of N well layer 51 can be 2~3nm, the thickness of every layer of GaN barrier layer 52 can for 9~
20nm。
Optionally, high temperature P-type layer 8 can be GaN layer, and thickness can be 20~50nm.
Optionally, p-type contact layer 9 can be GaN layer, and thickness can be 5~300nm.
Embodiment two
The embodiment of the invention provides a kind of manufacturing methods of LED epitaxial slice, provide for manufacturing embodiment one
LED epitaxial slice, Fig. 2 is a kind of side of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention
Method flow chart, as shown in Fig. 2, the manufacturing method includes：
Step 201 provides a substrate.
Optionally, substrate is the Al of (0001) crystal orientation2O3Sapphire Substrate.
Specifically, which includes：
In a hydrogen atmosphere, high-temperature process substrate 8min.Wherein, reaction chamber temperature is 1000~1200 DEG C, reacts chamber pressure
Power is controlled in 200~500torr.
Step 202, on substrate grown buffer layer.
Specifically, buffer layer is GaN layer, with a thickness of 15~35nm.Reaction chamber temperature is 400~600 DEG C, chamber pressure
Control is in 400~600torr.
Further, step 202 further includes：
Control chamber pressure it is constant, temperature is increased to 1000 DEG C~1200 DEG C, to buffering carry out in-situ annealing processing 5~
10min。
Step 203 grows undoped GaN layer on the buffer layer.
In the present embodiment, undoped GaN layer is with a thickness of 1~5um.When growing undoped GaN layer, reaction chamber temperature
It is 1000~1100 DEG C, chamber pressure is controlled in 100~500torr.
Step 204 grows N-type layer in undoped GaN layer.
In the present embodiment, N-type layer is to mix the GaN layer of Si, and Si doping concentration is 1018cm-3~1019cm-3Between, thickness
For 1~5um.When growing N-type layer, reaction chamber temperature is 1000~1200 DEG C, and chamber pressure is controlled in 100~500torr.
Step 205 grows active layer in N-type layer.
Active layer can be the In for including 5~11 periodsxGa1-xN well layer and GaN barrier layer superlattice structure, 0≤x≤1.
Wherein, every layer of InxGa1-xN well layer with a thickness of 2~3nm, every layer of GaN barrier layer with a thickness of 9~20nm.
Specifically, when growing active layer, chamber pressure is controlled in 100~500torr.Grow InxGa1-xWhen N well layer,
Reaction chamber temperature is 720~829 DEG C.When growing GaN barrier layer, reaction chamber temperature is 850~959 DEG C.
Step 206, the growing low temperature P-type layer on active layer.
In the present embodiment, low temperature P-type layer is GaN layer, with a thickness of 20~100nm.When growing high temperature P-type layer, reaction chamber
Temperature is 700~900 DEG C, and chamber pressure is controlled in 100~300torr.
Step 207 grows electronic barrier layer in low temperature P-type layer.
Specifically, electronic barrier layer is the Al for including N number of periodxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure,
0.05<x<0.15,0.2<y<0.4, N is the positive integer more than or equal to 2.
Preferably, x=0.1, y=0.38.The luminous efficiency of LED is best at this time.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yEach Al in N superlattice structurexGa1-xThe thickness of N sublayer
For 0.5~1.5nm.If each AlxGa1-xThe thickness of N sublayer is less than 0.5nm, then not having reduces electronic barrier layer and low temperature P
The effect of the lattice mismatch of type layer, if each AlxGa1-xThe thickness of N sublayer is greater than 1.5nm, and it will cause wastes, also result in
The thickness of electronic barrier layer is blocked up, influences the luminous efficiency of LED.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yEach AlN sublayer with a thickness of 0.5 in N superlattice structure
~1.5nm.If the thickness of each AlN sublayer is less than 0.5nm, the effect for stopping electronics is not had.If the thickness of each AlN sublayer
Degree is greater than 1.5nm, and it will cause wastes, and the thickness for also resulting in electronic barrier layer is blocked up, influence the luminous efficiency of LED.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yIn N superlattice structure each GaN sublayer with a thickness of 1~
2nm.If the thickness of each GaN sublayer is less than 1nm, certain two-dimensional electron gas can not be generated, to provide more holes, is mentioned
The migration rate of high carrier, if the thickness of each GaN sublayer is greater than 2nm, it will cause wastes, also result in electronic barrier layer
Thickness it is blocked up, influence the luminous efficiency of LED.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yEach In in N superlattice structureyGa1-yThe thickness of N sublayer
For 1~2nm.If each InyGa1-yThe thickness of N sublayer is less than 1nm, then can not enhance the generation of two-dimensional electron gas, if each
InyGa1-yThe thickness of N sublayer is greater than 2nm, and it will cause wastes, and the thickness for also resulting in electronic barrier layer is blocked up, influence LED's
Luminous efficiency.
Wherein, 2≤N≤5.If N, less than 2, the thickness that will lead to electronic barrier layer is excessively thin, blocking electronics can not be played,
Increase hole, improves the effect of the migration rate of carrier.If N is greater than 5, the thickness that will lead to electronic barrier layer is blocked up, drop
The luminous efficiency of low LED.
In the present embodiment, each AlxGa1-xN sublayer with a thickness of 1nm, each AlN sublayer with a thickness of 1nm, each
GaN sublayer with a thickness of 1nm, each InyGa1-yN sublayer with a thickness of 2nm, 2≤N≤5, electronic barrier layer 6 with a thickness of 10
~25nm.
Step 208 grows high temperature P-type layer on electronic barrier layer.
In the present embodiment, high temperature P-type layer is GaN layer, with a thickness of 20~50nm.When growing high temperature P-type layer, room temperature is reacted
Degree is 850~1080 DEG C, and chamber pressure is controlled in 100~300torr.
Step 209, the growing P-type contact layer in high temperature P-type layer.
In the present embodiment, p-type contact layer is GaN layer, with a thickness of 5~300nm.When growing P-type layer, reaction chamber temperature is
850~1050 DEG C, chamber pressure is controlled in 100~300torr.
After epitaxial wafer is grown, reaction chamber temperature is reduced to 650 DEG C~850 DEG C, by epitaxial wafer in nitrogen atmosphere
5~15min is made annealing treatment, is then down to room temperature, epitaxial growth terminates.
After the growth for terminating above-mentioned LED epitaxial slice, the temperature of reaction chamber is down to 600~900 DEG C,
PN2Atmosphere carries out 10~30min of annealing, is then gradually decreased to room temperature, then, after over cleaning, deposition, lithography and etching
The chip of single 9*27mil is made in continuous processing technology.
It is found after test, using LED chip made of the prior art, the light intensity under 20mA driving current is
104mW, using LED chip made of manufacturing method provided in an embodiment of the present invention, the light intensity under 20mA driving current is
106mW, luminous efficiency about improve 2%.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, and is sequentially laminated on the lining
Buffer layer, undoped GaN layer, N-type layer, active layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type on bottom connect
Contact layer, the low temperature P-type layer are GaN layer, which is characterized in that
The electronic barrier layer is the Al for including N number of periodxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<
0.15,0.2<y<0.4, N is positive integer more than or equal to 2, the electronic barrier layer with a thickness of 10~25nm.
2. LED epitaxial slice according to claim 1, which is characterized in that in the AlxGa1-xN/AlN/GaN/
InyGa1-yEach Al in N superlattice structurexGa1-xN sublayer with a thickness of 0.5~1.5nm.
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the AlxGa1-xN/AlN/
GaN/InyGa1-yEach AlN sublayer with a thickness of 0.5~1.5nm in N superlattice structure.
4. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the AlxGa1-xN/AlN/
GaN/InyGa1-yEach GaN sublayer with a thickness of 1~2nm in N superlattice structure.
5. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the AlxGa1-xN/AlN/
GaN/InyGa1-yEach In in N superlattice structureyGa1-yN sublayer with a thickness of 1~2nm.
6. LED epitaxial slice according to claim 1 or 2, which is characterized in that 2≤N≤5.
7. LED epitaxial slice according to claim 1 or 2, which is characterized in that x=0.1, y=0.38.
8. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes：
One substrate is provided；
Successively grown buffer layer, undoped GaN layer, N-type layer, active layer and low temperature P-type layer over the substrate, the low temperature
P-type layer is GaN layer；
Electronic barrier layer is grown in the low temperature P-type layer, the electronic barrier layer is the Al for including N number of periodxGa1-xN/AlN/
GaN/InyGa1-yN superlattice structure, 0.05<x<0.15,0.2<y<0.4, N is the positive integer more than or equal to 2, the electronics resistance
Barrier with a thickness of 10~25nm；
High temperature P-type layer and p-type contact layer are grown on the electronic barrier layer.
9. manufacturing method according to claim 8, which is characterized in that the growth temperature of the electronic barrier layer be 850~
1080℃。
10. manufacturing method according to claim 8 or claim 9, which is characterized in that the growth pressure of the electronic barrier layer is
200~500Torr.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN110137319A (en) * | 2019-05-21 | 2019-08-16 | 芜湖德豪润达光电科技有限公司 | LED epitaxial structure and preparation method thereof |
| CN111883623A (en) * | 2020-06-11 | 2020-11-03 | 华灿光电（浙江）有限公司 | Near ultraviolet light emitting diode epitaxial wafer and preparation method thereof |
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| CN114613891A (en) * | 2022-03-24 | 2022-06-10 | 淮安澳洋顺昌光电技术有限公司 | Light-emitting diode with novel composite electron blocking layer and preparation method thereof |
| CN114613891B (en) * | 2022-03-24 | 2023-11-14 | 淮安澳洋顺昌光电技术有限公司 | Light-emitting diode with composite electron blocking layer and preparation method thereof |
| CN117476834A (en) * | 2023-12-28 | 2024-01-30 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN117476834B (en) * | 2023-12-28 | 2024-03-22 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
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