CN108831974B - Light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents

Light emitting diode epitaxial wafer and manufacturing method thereof Download PDF

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CN108831974B
CN108831974B CN201810395843.4A CN201810395843A CN108831974B CN 108831974 B CN108831974 B CN 108831974B CN 201810395843 A CN201810395843 A CN 201810395843A CN 108831974 B CN108831974 B CN 108831974B
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electron blocking
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blocking layer
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CN108831974A (en
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魏晓骏
郭炳磊
李鹏
胡加辉
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, and belongs to the technical field of semiconductors. Comprises a substrate, a buffer layer, an undoped GaN layer, an N-type layer, an active layer, a low-temperature P-type layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer, wherein the electron blocking layer is Al with N periodsxGa1‑xN/AlN/GaN/InyGa1‑ yThe N-type superlattice structure is characterized in that N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer is 10-25 nm. Compared with the existing electron blocking layer with the thickness of more than 50nm, the thickness of the electron blocking layer provided by the invention is greatly reduced, so that the polarization and stress action among materials are reduced, the valence band order generated by the electron blocking layer on a valence band heterojunction interface is reduced, holes can be better injected into an active layer, the concentration of the holes is increased, more holes can be subjected to recombination luminescence with electrons in the active layer, and the luminous efficiency of an LED is improved.

Description

Light emitting diode epitaxial wafer and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.
Background
An LED (Light Emitting Diode) is a semiconductor electronic component capable of Emitting Light. As a novel high-efficiency, environment-friendly and green solid-state illumination light source, the solid-state illumination light source is rapidly and widely applied, such as traffic signal lamps, automobile interior and exterior lamps, urban landscape illumination, mobile phone backlight sources and the like.
The conventional GaN-based LED epitaxial wafer comprises a substrate and a GaN-based epitaxial layer arranged on the substrate, wherein the GaN-based epitaxial layer comprises a buffer layer, an undoped GaN layer, an N-type layer (N-type region), an active layer, an electron blocking layer, a high-temperature P-type layer (P-type region) and a P-type contact layer which are sequentially stacked on the substrate. Electrons provided by the N-type region and holes provided by the P-type region are recombined in the active layer to emit light. The electron blocking layer is usually an AlGaN layer or a multi-period AlGaN/InGaN superlattice structure, and the thickness of the electron blocking layer is more than 50 nm.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
in the existing LED epitaxial wafer, the electron blocking layer is designed to be thick (usually greater than 50nm), the thick electron blocking layer causes polarization and stress action between materials, and at the same time, a high valence band is generated to block the migration of holes to the active layer, so that the concentration of electrons provided by the N-type region is higher than that of holes provided by the P-type region, the mobility of electrons is much faster than that of holes, and the light emitting efficiency of the recombination of electrons and holes is reduced, thereby reducing the light emitting efficiency of the LED.
Disclosure of Invention
In order to solve the problem that the luminous efficiency of an LED is reduced due to the fact that an electron blocking layer is designed to be thick in the prior art, the embodiment of the invention provides an LED epitaxial wafer and a manufacturing method thereof. The technical scheme is as follows:
in one aspect, the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, an active layer, a low-temperature P-type layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer which are sequentially stacked on the substrate, wherein the low-temperature P-type layer is a GaN layer,
the electron blocking layer is Al comprising N periodsxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, wherein N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer is 10-25 nm;
in the AlxGa1-xN/AlN/GaN/InyGa1-yEach Al in the N superlatticexGa1-xThe thickness of the N sublayer is 0.5-1.5 nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each AlN sub-layer in the N superlattice structure is 0.5-1.5 nm.
Further, in the AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each GaN sublayer in the N superlattice structure is 1-2 nm.
Go toStep one, in the AlxGa1-xN/AlN/GaN/InyGa1-yEach In of the N superlattice structureyGa1-yThe thickness of the N sublayer is 1-2 nm.
Further, N is more than or equal to 2 and less than or equal to 5.
Further, x is 0.1 and y is 0.38.
In another aspect, an embodiment of the present invention provides a method for manufacturing an epitaxial wafer of a light emitting diode, where the method includes:
providing a substrate;
sequentially growing a buffer layer, an undoped GaN layer, an N-type layer, an active layer and a low-temperature P-type layer on the substrate, wherein the low-temperature P-type layer is a GaN layer;
growing an electron blocking layer on the low-temperature P-type layer, wherein the electron blocking layer is Al with N periodsxGa1- xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, N is a positive integer more than or equal to 2, the thickness of the electron blocking layer is 10-25 nm, and Al isxGa1-xN/AlN/GaN/InyGa1-yEach Al in the N superlatticexGa1-xThe thickness of the N sublayer is 0.5-1.5 nm;
and growing a high-temperature P-type layer and a P-type contact layer on the electron blocking layer.
Furthermore, the growth temperature of the electron blocking layer is 850-1080 ℃.
Furthermore, the growth pressure of the electron blocking layer is 200-500 Torr.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the electron blocking layer is provided to include N periods of AlxGa1-xN/AlN/GaN/InyGa1-yAn N superlattice structure, wherein the low-temperature P-type layer is a GaN layer, and the AlN layer in the electron blocking layer is lattice mismatched with the low-temperature P-type GaN layer, so that Al is arrangedxGa1-xThe N is used as a buffer layer, and can reduce lattice mismatch between the electron blocking layer and the low-temperature P-type layer. The AlN layer can form a higher barrier energy levelAnd the migration of electrons is blocked, and meanwhile, due to the large lattice mismatch of the interface between the AlN layer and the GaN layer, a certain two-dimensional electron gas can be generated between the AlN layer and the GaN layer so as to provide more holes and improve the migration rate of carriers. InyGa1-yThe N layer can enhance the generation of two-dimensional electron gas, further provide more holes and improve the migration rate of carriers. The thickness of the electron blocking layer is 10-25 nm, and compared with the existing electron blocking layer with the thickness larger than 50nm, the thickness of the electron blocking layer is greatly reduced, so that the polarization and stress action among materials are reduced, the valence band order generated by the electron blocking layer with high Al component on a valence band heterojunction interface is reduced, holes can be better injected into an active layer, the concentration of the holes is increased, more holes can be combined with electrons in the active layer to emit light, and the light emitting efficiency of the LED is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 1, the led epitaxial wafer includes a substrate 1, and a buffer layer 2, an undoped GaN layer 3, an N-type layer 4, an active layer 5, a low-temperature P-type layer 6, an electron blocking layer 7, a high-temperature P-type layer 8, and a P-type contact layer 9, which are sequentially stacked on the substrate 1, where the low-temperature P-type layer 6 is a GaN layer.
Wherein the electron blocking layer 7 is Al including N periodsxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer 7 is 10-25 nm.
By arranging the electron blocking layer to include N periods of AlxGa1-xN/AlN/GaN/InyGa1-yAn N superlattice structure, wherein the low-temperature P-type layer is a GaN layer, and the AlN layer in the electron blocking layer is lattice mismatched with the low-temperature P-type GaN layer, so that Al is arrangedxGa1-xThe N is used as a buffer layer, and can reduce lattice mismatch between the electron blocking layer and the low-temperature P-type layer. The AlN layer can form a higher barrier energy level to block the migration of electrons, and meanwhile, due to the fact that the interface lattice mismatch between the AlN layer and the GaN layer is large, a certain two-dimensional electron gas can be generated between the AlN layer and the GaN layer to provide more holes and improve the migration rate of carriers. InyGa1-yThe N layer can enhance the generation of two-dimensional electron gas, further provide more holes and improve the migration rate of carriers. The thickness of the electron blocking layer is 10-25 nm, and compared with the existing electron blocking layer with the thickness larger than 50nm, the thickness of the electron blocking layer is greatly reduced, so that the polarization and stress action among materials are reduced, the valence band order generated by the electron blocking layer with high Al component on a valence band heterojunction interface is reduced, holes can be better injected into an active layer, the concentration of the holes is increased, more holes can be combined with electrons in the active layer to emit light, and the light emitting efficiency of the LED is improved.
Preferably, x is 0.1 and y is 0.38. The LED has the best luminous efficiency.
Specifically, each Al in the electron blocking layer 7xGa1-xN/AlN/GaN/InyGa1-yThe N superlattice structures all comprise AlxGa1-xN sublayer 71, AlN sublayer 72, GaN sublayer 73, and InyGa1-yAnd an N sublayer 74.
Further, the air conditioner is provided with a fan,each AlxGa1-xThe thickness of the N sublayer 71 is 0.5 to 1.5 nm. If each Al is presentxGa1-xThe thickness of the N sublayer 71 is less than 0.5nm, which does not reduce the lattice mismatch between the electron blocking layer 7 and the low-temperature P-type layer 6, and if each Al layer is formedxGa1- xThe thickness of the N sublayer 71 is greater than 1.5nm, which causes waste and results in an excessively thick electron blocking layer 7, which affects the light emitting efficiency of the LED.
Preferably, each AlxGa1-xThe thickness of the N sublayer 71 is 1 nm. At this time, the effect of reducing the lattice mismatch between the electron blocking layer 7 and the low-temperature P-type layer 6 can be achieved, and the electron blocking layer 7 is guaranteed not to be too thick, so that waste is caused.
Further, the thickness of each AlN sub-layer 72 is 0.5 to 1.5 nm. If the thickness of each AlN sub-layer 72 is less than 0.5nm, it does not function as a barrier to electrons. If the thickness of each AlN sublayer 72 is greater than 1.5nm, it will cause waste, and also result in an excessively thick electron blocking layer 7, which affects the light emitting efficiency of the LED.
Preferably, each AlN sub-layer 72 is 1nm thick. At the moment, the function of blocking electrons can be achieved, and the thickness of the electron blocking layer 7 can be prevented from being too thick, so that waste is caused.
Further, each GaN sublayer 73 has a thickness of 1 to 2 nm. If the thickness of each GaN sublayer 73 is less than 1nm, a certain two-dimensional electron gas cannot be generated to provide more holes and increase the mobility rate of carriers, and if the thickness of each GaN sublayer 73 is greater than 2nm, waste is caused, and the thickness of the electron blocking layer 7 is too thick, which affects the light emitting efficiency of the LED.
Preferably, each GaN sublayer 73 is 1nm thick. At this time, a certain amount of two-dimensional electron gas can be generated with the AlN sublayer 72 to provide more holes, increase the mobility rate of carriers, and ensure that the thickness of the electron blocking layer 7 is not too thick, resulting in waste.
Further, each InyGa1-yThe thickness of the N sublayer 74 is 1-2 nm. If each InyGa1-yThe thickness of the N sublayer 74 of less than 1nm does not enhance the generation of two-dimensional electron gas, if each isInyGa1-yThe thickness of the N sublayer 74 is greater than 2nm, which causes waste and results in an excessively thick electron blocking layer 7, which affects the luminous efficiency of the LED.
Preferably, each InyGa1-yThe thickness of the N sublayer 74 is 2 nm. At this time, more two-dimensional electron gas can be generated between the AlN sublayer 72 and the GaN sublayer 73, more holes can be further provided, the mobility rate of carriers can be increased, and the electron blocking layer 7 can be ensured not to be too thick, which causes waste.
Wherein N is more than or equal to 2 and less than or equal to 5. If N is less than 2, the thickness of the electron blocking layer 7 is too thin, and the electron blocking layer cannot block electrons, increase holes, and increase the mobility of carriers. If N is greater than 5, the thickness of the electron blocking layer 7 becomes too thick, and the light emission efficiency of the LED is reduced.
Alternatively, the substrate 1 may be a sapphire substrate of (0001) crystal orientation.
Optionally, the buffer layer 2 may be a GaN layer, and may have a thickness of 15 to 35 nm.
Optionally, the thickness of the undoped GaN layer 3 can be 1-5 um.
Alternatively, the N-type layer 4 may be a Si-doped GaN layer in which Si is doped in a concentration range of 1018cm-3～1019cm-3(ii) a The thickness of the N-type layer 4 can be 1-5 um.
Alternatively, the active layer 5 may be formed of 5 to 11 periods of InxGa1-xAn N-well layer 51 and a GaN barrier layer 52, wherein each layer of In has a superlattice structurexGa1-xThe thickness of the N-well layer 51 can be 2-3 nm, and the thickness of each GaN barrier layer 52 can be 9-20 nm.
Optionally, the high-temperature P-type layer 8 may be a GaN layer, and the thickness may be 20 to 50 nm.
Alternatively, the P-type contact layer 9 may be a GaN layer and may have a thickness of 5-300 nm.
Example two
An embodiment of the present invention provides a method for manufacturing an led epitaxial wafer, which is used to manufacture an led epitaxial wafer provided in the first embodiment of the present invention, and fig. 2 is a flowchart of a method for manufacturing an led epitaxial wafer provided in the first embodiment of the present invention, as shown in fig. 2, the method includes:
step 201, a substrate is provided.
Optionally, the substrate is (0001) oriented Al2O3A sapphire substrate.
Specifically, the step 201 includes:
and processing the substrate at high temperature for 8min under a hydrogen atmosphere. Wherein the temperature of the reaction chamber is 1000-1200 deg.C, and the pressure of the reaction chamber is controlled at 200-500 torr.
Step 202, a buffer layer is grown on the substrate.
Specifically, the buffer layer is a GaN layer, and the thickness is 15-35 nm. The temperature of the reaction chamber is 400-600 ℃, and the pressure of the reaction chamber is controlled at 400-600 torr.
Further, step 202 further comprises:
and controlling the pressure in the reaction chamber to be unchanged, raising the temperature to 1000-1200 ℃, and carrying out in-situ annealing treatment on the buffer for 5-10 min.
Step 203, growing an undoped GaN layer on the buffer layer.
In the present embodiment, the thickness of the undoped GaN layer is 1-5 um. When growing the undoped GaN layer, the temperature of the reaction chamber is 1000-1100 ℃, and the pressure of the reaction chamber is controlled at 100-500 torr.
Step 204, an N-type layer is grown on the undoped GaN layer.
In this embodiment, the N-type layer is a Si-doped GaN layer with a Si doping concentration of 1018cm-3～1019cm-3And the thickness is 1-5 um. When growing the N-type layer, the temperature of the reaction chamber is 1000-1200 ℃, and the pressure of the reaction chamber is controlled at 100-500 torr.
Step 205, an active layer is grown on the N-type layer.
The active layer may include 5 to 11 periods of InxGa1-xThe superlattice structures of the N well layer and the GaN barrier layer are disclosed, and x is more than or equal to 0 and less than or equal to 1. Wherein each layer of InxGa1-xThe thickness of the N well layer is 2-3 nm, and the thickness of each GaN barrier layer is 9-20 nm.
Specifically, an active layer is grownThe pressure in the reaction chamber is controlled to be 100 to 500 torr. Growing InxGa1-xWhen the N well layer is used, the temperature of the reaction chamber is 720-829 ℃. And when the GaN barrier layer grows, the temperature of the reaction chamber is 850-959 ℃.
Step 206, a low temperature P-type layer is grown on the active layer.
In the embodiment, the low-temperature P-type layer is a GaN layer with a thickness of 20-100 nm. When a high-temperature P-type layer is grown, the temperature of the reaction chamber is 700-900 ℃, and the pressure of the reaction chamber is controlled at 100-300 torr.
Step 207, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, the electron blocking layer is Al including N periodsxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, N is a positive integer of 2 or more.
Preferably, x is 0.1 and y is 0.38. The LED has the best luminous efficiency.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yEach Al in the N superlatticexGa1-xThe thickness of the N sublayer is 0.5-1.5 nm. If each Al is presentxGa1-xThe thickness of the N sublayer is less than 0.5nm, the lattice mismatch between the electron blocking layer and the low-temperature P type layer cannot be reduced, and if each Al sublayer is less than 0.5nm, each Al sublayer has no effect on reducing the lattice mismatch between the electron blocking layer and the low-temperature P type layerxGa1-xThe thickness of the N sublayer is larger than 1.5nm, which causes waste and causes the over-thickness of the electron blocking layer to affect the luminous efficiency of the LED.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each AlN sub-layer in the N superlattice structure is 0.5-1.5 nm. If the thickness of each AlN sub-layer is less than 0.5nm, it does not function as a barrier to electrons. If the thickness of each AlN sublayer is greater than 1.5nm, waste is caused, and the thickness of the electron blocking layer is too thick, so that the luminous efficiency of the LED is affected.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yThe thickness of each GaN sublayer in the N superlattice structure is 1-2 nm. If the thickness of each GaN sublayer is less than 1nm, it is impossible to do soA certain two-dimensional electron gas is generated to provide more holes and increase the mobility rate of carriers, if the thickness of each GaN sublayer is greater than 2nm, waste is caused, and the thickness of the electron blocking layer is too thick, which affects the luminous efficiency of the LED.
Further, in AlxGa1-xN/AlN/GaN/InyGa1-yEach In of the N superlattice structureyGa1-yThe thickness of the N sublayer is 1-2 nm. If each InyGa1-yIf the thickness of the N sublayer is less than 1nm, the generation of two-dimensional electron gas cannot be enhanced, and if each In isyGa1-yThe thickness of the N sublayer is greater than 2nm, which causes waste and causes the thickness of the electron blocking layer to be too thick, thereby affecting the luminous efficiency of the LED.
Wherein N is more than or equal to 2 and less than or equal to 5. If N is less than 2, the thickness of the electron blocking layer is too thin, and the electron blocking layer cannot block electrons, increase holes, and increase the mobility rate of carriers. If N is greater than 5, the thickness of the electron blocking layer becomes too thick, and the light emission efficiency of the LED is reduced.
In the present embodiment, each AlxGa1-xThe thickness of the N sublayer was 1nm, the thickness of each AlN sublayer was 1nm, the thickness of each GaN sublayer was 1nm, and each InyGa1-yThe thickness of the N sublayer is 2nm, the N is more than or equal to 2 and less than or equal to 5, and the thickness of the electron blocking layer 6 is 10-25 nm.
Step 208, a high temperature P-type layer is grown on the electron blocking layer.
In the present embodiment, the high temperature P-type layer is a GaN layer with a thickness of 20-50 nm. When a high-temperature P-type layer is grown, the temperature of the reaction chamber is 850-1080 ℃, and the pressure of the reaction chamber is controlled at 100-300 torr.
Step 209 is to grow a P-type contact layer on the high temperature P-type layer.
In the present embodiment, the P-type contact layer is a GaN layer with a thickness of 5-300 nm. When the P-type layer is grown, the temperature of the reaction chamber is 850-1050 ℃, and the pressure of the reaction chamber is controlled at 100-300 torr.
And after the epitaxial wafer growth is finished, reducing the temperature of the reaction cavity to 650-850 ℃, annealing the epitaxial wafer for 5-15 min in a nitrogen atmosphere, then reducing the temperature to room temperature, and finishing the epitaxial growth.
After the growth of the light emitting diode epitaxial wafer is finished, the temperature of the reaction chamber is reduced to 600-900 ℃, and the temperature is measured in PN2Annealing for 10-30 min in the atmosphere, then gradually cooling to room temperature, and then carrying out subsequent processing technologies of cleaning, deposition, photoetching and etching to prepare single 9 × 27mil chips.
After testing, the LED chip manufactured by adopting the prior art has the light intensity of 104mW under the drive current of 20mA, and the LED chip manufactured by adopting the manufacturing method provided by the embodiment of the invention has the light intensity of 106mW under the drive current of 20mA, so that the luminous efficiency is improved by about 2%.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. A light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, an active layer, a low-temperature P-type layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the low-temperature P-type layer is a GaN layer,
the electron blocking layer is Al comprising N periodsxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, wherein N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer is 10-25 nm;
in the AlxGa1-xN/AlN/GaN/InyGa1-yEach Al in the N superlatticexGa1-xThe thickness of the N sublayer is 0.5-1.5 nm.
2. The light emitting diode epitaxial wafer as claimed in claim 1, wherein the Al is on the substratexGa1-xN/AlN/GaN/InyGa1-yThe thickness of each AlN sub-layer in the N superlattice structure is 0.5-1.5 nm.
3. The light emitting diode epitaxial wafer as claimed in claim 1, wherein the Al is on the substratexGa1-xN/AlN/GaN/InyGa1-yThe thickness of each GaN sublayer in the N superlattice structure is 1-2 nm.
4. The light emitting diode epitaxial wafer as claimed in claim 1, wherein the Al is on the substratexGa1-xN/AlN/GaN/InyGa1-yEach In of the N superlattice structureyGa1-yThe thickness of the N sublayer is 1-2 nm.
5. The light-emitting diode epitaxial wafer as claimed in claim 1, wherein N is 2. ltoreq. N.ltoreq.5.
6. The light emitting diode epitaxial wafer according to claim 1, wherein x is 0.1 and y is 0.38.
7. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing a buffer layer, an undoped GaN layer, an N-type layer, an active layer and a low-temperature P-type layer on the substrate, wherein the low-temperature P-type layer is a GaN layer;
growing an electron blocking layer on the low-temperature P-type layer, wherein the electron blocking layer is Al with N periodsxGa1-xN/AlN/GaN/InyGa1-yN superlattice structure, 0.05<x<0.15，0.2<y<0.4, N is a positive integer more than or equal to 2, the thickness of the electron blocking layer is 10-25 nm, and Al isxGa1-xN/AlN/GaN/InyGa1-yEach Al in the N superlatticexGa1-xThe thickness of the N sublayer is 0.5-1.5 nm;
and growing a high-temperature P-type layer and a P-type contact layer on the electron blocking layer.
8. The method of claim 7, wherein the growth temperature of the electron blocking layer is 850 to 1080 ℃.
9. The method of manufacturing according to claim 7 or 8, wherein a growth pressure of the electron blocking layer is 200 to 500 Torr.
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