CN109346568B - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents
Light emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract
The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductors. The light emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer, a third sublayer and a fourth sublayer which are sequentially laminated; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride. The invention finally improves the photoelectric performance of the LED.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. The LED has the advantages of high efficiency, long service life, small volume, low power consumption and the like, and can be applied to the fields of indoor and outdoor white light illumination, screen display, backlight sources and the like. In the development of the LED industry, gallium nitride (GaN) -based materials are a typical representative of group V-III compound semiconductors, and improving the photoelectric properties of GaN-based LEDs has become a key to the semiconductor lighting industry.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional GaN-based LED epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The substrate is used for providing a growth surface for epitaxial materials, the N-type semiconductor layer is used for providing electrons for carrying out recombination luminescence, the P-type semiconductor layer is used for providing holes for carrying out recombination luminescence, and the active layer is used for carrying out radiation recombination luminescence of the electrons and the holes.
The active layer comprises a plurality of well layers and a plurality of barrier layers, the well layers and the barrier layers are alternately stacked, and electrons and holes injected into the active layer are limited in the well layers by the barrier layers to carry out compound light emission. Generally, the well layer is made of indium gallium nitride (InGaN) with high indium composition, and the barrier layer is made of gallium nitride (GaN). Since the lattice constant of gallium nitride is 3.181 and the lattice constant of indium nitride is 3.538, a large lattice mismatch exists between the well layer and the barrier layer, and the recombination efficiency of electrons and holes in space is affected by stress generated by the lattice mismatch, resulting in low light emitting efficiency of the LED.
In order to alleviate lattice mismatch between the well layer and the barrier layer, a stress release layer is generally grown on the N-type semiconductor layer before the active layer is grown, i.e., the stress release layer is disposed between the N-type semiconductor layer and the active layer. The stress release layer comprises a plurality of first sub-layers and a plurality of second sub-layers which are alternately stacked, the first sub-layers are made of indium gallium nitride with low indium composition (the content of indium composition in the first sub-layers is lower than that in the well layers), and the second sub-layers are made of gallium nitride (the material of the second sub-layers is the same as that of the barrier layers). The lattice matching between the first sub-layer and the second sub-layer is good, and meanwhile, the material of the first sub-layer is indium gallium nitride, so that the growth quality is poor, and the stress release layer formed by alternately stacking the plurality of first sub-layers and the plurality of second sub-layers can release stress generated by lattice mismatch between the well layer and the barrier layer in the active layer.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the lower the growth temperature of the stress release layer is, the better the stress release effect of the stress release layer is. However, if the growth temperature of the stress release layer is low, carbon impurities introduced into the stress release layer in the growth process are more, a thyristor effect occurs when the content of the carbon impurities in the stress release layer is too high, and meanwhile, the low growth temperature causes poor crystal quality of the stress release layer, and the antistatic capacity of the LED is reduced. Therefore, in order to avoid the above-mentioned adverse effects, the growth temperature of the stress relaxation layer is generally high (850 ℃ to 870 ℃), resulting in a limited stress relaxation effect of the stress relaxation layer.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode epitaxial wafer and a preparation method thereof, which can solve the problem that the growth temperature of a stress release layer is higher in the prior art to limit the stress release effect. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode epitaxial wafer, where the light emitting diode epitaxial wafer includes a substrate, an N-type semiconductor layer, a stress release layer, an active layer, and a P-type semiconductor layer, where the N-type semiconductor layer, the stress release layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer, a third sublayer and a fourth sublayer which are sequentially laminated; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride.
Optionally, the thickness of the second sublayer is less than or equal to 5 nm.
Optionally, the thickness of the third sublayer is less than or equal to 2 nm.
Optionally, the number of the composite structures is 2 to 20.
Optionally, the electron concentration in the fourth sublayer is 1017cm-3～1019cm-3。
On the other hand, the embodiment of the invention provides a preparation method of a light emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer on the substrate;
the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer, a third sublayer and a fourth sublayer which are sequentially laminated; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride.
Optionally, the growth temperature of the stress release layer is less than or equal to the growth temperature of the N-type semiconductor layer.
Optionally, the growth temperatures of the second sublayer, the third sublayer and the fourth sublayer are all greater than or equal to the growth temperature of the first sublayer, the growth temperature of the first sublayer is less than or equal to the growth temperature of the second sublayer, the growth temperature of the first sublayer is less than or equal to the growth temperature of the third sublayer, and the growth temperature of the first sublayer is less than or equal to the growth temperature of the fourth sublayer.
Optionally, the preparation method further comprises:
after each first sublayer grows, stopping introducing the gallium source and the indium source into the reaction cavity for growing the first sublayers, continuously introducing ammonia gas into the reaction cavity for growing the first sublayers, and stopping growing the first sublayers.
Optionally, the time period for stopping growth of the first sublayer is less than or equal to 15 s.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by sequentially inserting the aluminum nitride layer and the silicon nitride layer between the indium gallium nitride layer and the gallium nitride layer of the stress release layer, silicon atoms in the silicon nitride layer can be fully combined with the dangling bonds of the nitrogen atoms to form Si-N covalent bonds, redundant electrons are released, and the electron concentration in the stress release layer is effectively improved; meanwhile, the potential barrier of the aluminum nitride layer is high, and the aluminum nitride layer is matched with the gallium nitride layer to clamp the silicon nitride layer in the middle, so that the current expansion can be effectively improved, and the overall current expansion of the stress release layer is good. The good current spreading capability of the stress release layer can make up the reduction of thyristor effect and antistatic capability caused by low growth temperature of the stress release layer, so that the reduction of the growth temperature of the stress release layer (from 850 ℃ -870 ℃ to 820 ℃) can be realized, the stress release effect of the stress release layer is improved, the crystal quality of an active layer is further improved, and the photoelectric performance of the LED is finally improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a stress relieving layer provided in an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light-emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, a stress relief layer 30, an active layer 40, and a P-type semiconductor layer 50, and the N-type semiconductor layer 20, the stress relief layer 30, the active layer 40, and the P-type semiconductor layer 50 are sequentially stacked on the substrate 10.
Fig. 2 is a schematic structural diagram of a stress release layer according to an embodiment of the present invention. Referring to fig. 2, in the present embodiment, the stress relieving layer 30 includes a plurality of composite structures sequentially laminated, each of which includes a first sublayer 31, a second sublayer 32, a third sublayer 33, and a fourth sublayer 34 sequentially laminated. The first sublayer 31 is made of undoped indium gallium nitride, the second sublayer 32 is made of undoped aluminum nitride, the third sublayer 33 is made of silicon nitride, and the fourth sublayer 34 is made of undoped gallium nitride.
According to the embodiment of the invention, the aluminum nitride layer and the silicon nitride layer are sequentially inserted between the indium gallium nitride layer and the gallium nitride layer of the stress release layer, silicon atoms in the silicon nitride layer can be fully combined with the suspension bonds of the nitrogen atoms to form Si-N covalent bonds, redundant electrons are released, and the electron concentration in the stress release layer is effectively improved; meanwhile, the potential barrier of the aluminum nitride layer is high, and the aluminum nitride layer is matched with the gallium nitride layer to clamp the silicon nitride layer in the middle, so that the current expansion can be effectively improved, and the overall current expansion of the stress release layer is good. The good current spreading capability of the stress release layer can make up the reduction of thyristor effect and antistatic capability caused by low growth temperature of the stress release layer, so that the reduction of the growth temperature of the stress release layer (from 850 ℃ -870 ℃ to 820 ℃) can be realized, the stress release effect of the stress release layer is improved, the crystal quality of an active layer is further improved, and the photoelectric performance of the LED is finally improved. In addition, the active layer is arranged on the gallium nitride layer in the composite structure, and the growth quality is good.
Alternatively, the thickness of the first sub-layer 31 may be 1nm to 5nm, preferably 1.5nm, and the effect of stress release is better.
Alternatively, the thickness of the second sub-layer 32 may be less than or equal to 5nm, avoiding that the second sub-layer is thicker and thus affecting the electron injection into the active layer.
Preferably, the thickness of the second sublayer 32 may be 2 nm.
Optionally, the thickness of the third sub-layer 33 may be less than or equal to 2nm, so as to avoid that the crystal quality of the stress release layer is too poor due to the thicker third sub-layer, and the crystal quality of the whole epitaxial wafer is affected.
Preferably, the thickness of the third sublayer 33 may be 1 nm.
Alternatively, the thickness of the fourth sub-layer 34 may be 20nm to 60nm, preferably 40nm, to ensure the overall crystal structure and crystal quality of the stress relieving layer.
Alternatively, the number of composite structures may be 2 to 20, preferably 3.
If the number of the composite structures is less than 2, stress generated by lattice mismatch between the well layer and the barrier layer in the active layer may not be effectively released due to the small number of the composite structures; if the number of the composite structures is greater than 20, the complexity of the process and the cost of production may be increased due to the greater number of the composite structures.
Alternatively, the electron concentration in the fourth sublayer 34 may be 1017cm-3～1019cm-3Preferably 1.8 x 1018cm-3And the current spreading effect of the stress release layer is better.
Optionally, the content of the indium component in the first sub-layer 31 may be less than or equal to 3%, so as to avoid the influence on the overall crystal quality of the epitaxial wafer due to the high content of the indium component in the first sub-layer.
Preferably, the content of the indium component in the first sub-layer 31 may be 1.5%.
Specifically, the material of the substrate 10 may be sapphire (aluminum oxide is a main material), silicon, or silicon carbide. The material of the N-type semiconductor layer 20 may be N-type doped (e.g., silicon or germanium) gan. The active layer 40 may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the quantum well material may be indium gallium nitride (InGaN), such as InxGa1-xN, 0 < x < 1, and gallium nitride can be used as the material of the quantum barrier. The P-type semiconductor layer 50 may be made of P-type doped (e.g., mg) gan.
Further, the thickness of the N-type semiconductor layer 20 may be 1 to 5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 20 may be 1018cm-3～9*1019cm-3Preferably 1019cm-3. The thickness of the quantum well can be 2.5 nm-3.5 nm, and is preferably 3 nm; the thickness of the quantum barrier can be 9nm to 13nm, and is preferably 11 nm; the number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers may be 10 to 15, and preferably 12. The thickness of the P-type semiconductor layer 50 may be 100nm to 300nm, preferably 200 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 50 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
In practical applications, the substrate 10 may be provided with a patterned silicon dioxide layer, so as to reduce the dislocation density of the GaN epitaxial material, and change the light exit angle to improve the light extraction efficiency. Specifically, a layer of silicon dioxide material can be laid on a sapphire substrate; forming a photoresist with a certain pattern on the silicon dioxide material by adopting a photoetching technology; then removing the silicon dioxide material which is not covered by the photoresist by adopting a dry etching technology, and forming a patterned silicon dioxide layer by using the left silicon dioxide material; and finally removing the photoresist.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a buffer layer 61, where the buffer layer 61 is disposed between the substrate 10 and the N-type semiconductor layer 20 to relieve stress and defects generated by lattice mismatch between the substrate material and the gallium nitride and provide nucleation centers for epitaxial growth of the gallium nitride material.
Specifically, the material of the buffer layer 61 may be gallium nitride or aluminum nitride.
Further, the thickness of the buffer layer 61 may be 15nm to 35nm, preferably 25 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 62, where the undoped gallium nitride layer 62 is disposed between the buffer layer 61 and the N-type semiconductor layer 20 to further alleviate stress and defects generated by lattice mismatch between the substrate material and gallium nitride, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on the patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer in this embodiment.
Further, the thickness of the undoped gallium nitride layer 62 may be 1 μm to 3 μm, preferably 2 μm.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an electron blocking layer 71, and the electron blocking layer 71 is disposed between the active layer 40 and the P-type semiconductor layer 50to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the material of the electron blocking layer 71 may be P-type doped aluminum gallium nitride (AlGaN), such as AlyGa1-yN，0.1＜y＜0.5。
Further, the thickness of the electron blocking layer 71 may be 50nm to 150nm, preferably 100 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a low temperature P-type layer 72, where the low temperature P-type layer 72 is disposed between the active layer 40 and the electron blocking layer 71, so as to avoid indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the light emitting diode.
Specifically, the material of the low temperature P-type layer 72 may be the same as the material of the P-type semiconductor layer 50. In the present embodiment, the material of the low temperature P-type layer 72 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 72 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 72 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a contact layer 80, and the contact layer 80 is disposed on the P-type semiconductor layer 50to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 80 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 80 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 80 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a preparation method of a light-emitting diode epitaxial wafer, which is suitable for preparing the light-emitting diode epitaxial wafer shown in figure 1. Fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 3, the preparation method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the surface of the substrate is cleaned.
Specifically, cleaning the surface of the substrate may include:
and controlling the temperature to be 1110 ℃, and annealing the substrate in a hydrogen atmosphere for 8-10 minutes.
Step 202: an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In this embodiment, the stress release layer includes a plurality of composite structures stacked in sequence, and each composite structure includes a first sublayer, a second sublayer, a third sublayer and a fourth sublayer stacked in sequence; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride.
Alternatively, the growth temperature of the stress relieving layer may be less than or equal to the growth temperature of the N-type semiconductor layer. The growth temperature of the stress release layer is low, so that stress generated by lattice mismatch between the well layer and the barrier layer in the active layer can be released, the crystal quality of the active layer is improved, and the photoelectric performance of the LED is improved.
The growth temperature of the stress release layer is less than or equal to the growth temperature of the N-type semiconductor layer, that is, the growth temperature of the first sublayer is less than or equal to the growth temperature of the N-type semiconductor layer, the growth temperature of the second sublayer is less than or equal to the growth temperature of the N-type semiconductor layer, the growth temperature of the third sublayer is less than or equal to the growth temperature of the N-type semiconductor layer, and the growth temperature of the fourth sublayer is less than or equal to the growth temperature of the N-type semiconductor layer.
Optionally, the growth temperatures of the second sublayer, the third sublayer and the fourth sublayer may be all greater than or equal to the growth temperature of the first sublayer, that is, the growth temperature of the first sublayer is less than or equal to the growth temperature of the second sublayer, the growth temperature of the first sublayer is less than or equal to the growth temperature of the third sublayer, and the growth temperature of the first sublayer is less than or equal to the growth temperature of the fourth sublayer. The growth temperature of the first sub-layer is low, so that indium in the first sub-layer can be prevented from being analyzed due to high-temperature growth.
Specifically, the growth temperature of the first sub-layer may be 820 to 840 ℃, the growth temperature of the second sub-layer may be 820 to 840 ℃, the growth temperature of the third sub-layer may be 820 to 840 ℃, and the growth temperature of the fourth sub-layer may be 820 to 840 ℃.
Accordingly, the growth pressure of the first sub-layer may be 100torr to 500torr, the growth pressure of the second sub-layer may be 100torr to 500torr, the growth pressure of the third sub-layer may be 100torr to 500torr, and the growth temperature of the fourth sub-layer may be 100torr to 500 torr.
Optionally, the preparation method may further include:
after each first sublayer grows, stopping introducing the gallium source and the indium source into the reaction cavity for growing the first sublayers, continuously introducing ammonia gas into the reaction cavity for growing the first sublayers, and stopping growing the first sublayers.
Indium atoms accumulated on the surface of the first sublayer are volatilized through intermittent growth, the indium atoms are prevented from diffusing into a subsequently grown semiconductor layer, and the crystal quality of an interface of the first sublayer and the subsequently grown semiconductor layer is improved.
Preferably, the time length of the growth stop of the first sublayer can be less than or equal to 15s, so that the influence on the overall production efficiency of the epitaxial wafer due to the long growth stop time is avoided;
more preferably, the time length of the growth stop of the first sublayer may be 8s, and the production efficiency of the whole epitaxial wafer is considered under the condition that indium atoms accumulated on the surface of the first sublayer are fully volatilized.
Specifically, this step 202 may include:
a first step of growing an N-type semiconductor layer on a substrate at a temperature of 1050 ℃ to 1100 ℃ (preferably 1080 ℃) and a pressure of 100torr to 500torr (preferably 300 torr);
secondly, growing a stress release layer on the N-type semiconductor layer;
thirdly, growing an active layer on the stress release layer; wherein the growth temperature of the quantum well is 780 ℃ -820 ℃ (preferably 800 ℃), and the pressure is 100 torr-500 torr (preferably 300 torr); the growth temperature of the quantum barrier is 900 ℃ -950 ℃ (preferably 930 ℃), and the pressure is 100 torr-500 torr (preferably 300 torr);
and fourthly, controlling the temperature to be 850-1080 ℃ (preferably 960 ℃) and the pressure to be 100-300 torr (preferably 200torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the first step, the preparation method may further comprise:
a buffer layer is formed on a substrate.
Accordingly, an N-type semiconductor layer is grown on the buffer layer.
Specifically, forming the buffer layer on the substrate may include:
a Physical Vapor Deposition (PVD) technique is used to form a buffer layer on a substrate.
Preferably, after growing the buffer layer on the substrate, the preparation method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
the undoped gallium nitride layer is grown on the buffer layer under a temperature of 1000 ℃ to 1200 ℃ (preferably 1100 ℃) and a pressure of 100torr to 500torr (preferably 300 torr).
Optionally, before the fourth step, the preparation method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
the temperature is controlled to be 850 ℃ to 1080 ℃ (preferably 960 ℃), the pressure is controlled to be 200torr to 500torr (preferably 350torr), and the electron blocking layer is grown on the active layer.
Preferably, before growing the electron blocking layer on the active layer, the preparation method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fourth step, the preparation method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as an N-type dopant, and magnesium diclocide is used as a P-type dopant.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The light-emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer, a third sublayer and a fourth sublayer which are sequentially laminated; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride.
2. The light emitting diode epitaxial wafer of claim 1, wherein the thickness of the second sub-layer is less than or equal to 5 nm.
3. Light emitting diode epitaxial wafer according to claim 1 or 2, characterized in that the thickness of the third sublayer is less than or equal to 2 nm.
4. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein the number of the composite structures is 2-20.
5. Light emitting diode epitaxial wafer according to claim 1 or 2, wherein the light emitting diode epitaxial wafer is characterized in thatThen, the electron concentration in the fourth sublayer is 1017cm-3～1019cm-3。
6. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer on the substrate;
the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer, a third sublayer and a fourth sublayer which are sequentially laminated; the first sublayer is made of undoped indium gallium nitride, the second sublayer is made of undoped aluminum nitride, the third sublayer is made of silicon nitride, and the fourth sublayer is made of undoped gallium nitride.
7. The method according to claim 6, wherein a growth temperature of the stress release layer is less than or equal to a growth temperature of the N-type semiconductor layer.
8. The method according to claim 6 or 7, wherein the growth temperatures of the second, third and fourth sublayers are all greater than or equal to the growth temperature of the first sublayer, the growth temperature of the first sublayer is less than or equal to the growth temperature of the second sublayer, the growth temperature of the first sublayer is less than or equal to the growth temperature of the third sublayer, and the growth temperature of the first sublayer is less than or equal to the growth temperature of the fourth sublayer.
9. The production method according to claim 6 or 7, characterized by further comprising:
after each first sublayer grows, stopping introducing the gallium source and the indium source into the reaction cavity for growing the first sublayers, continuously introducing ammonia gas into the reaction cavity for growing the first sublayers, and stopping growing the first sublayers.
10. A method of manufacturing according to claim 9, wherein the length of time for which the growth of the first sub-layer is stopped is less than or equal to 15 s.
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