CN109103303B - Preparation method of light-emitting diode epitaxial wafer and light-emitting diode epitaxial wafer - Google Patents
Preparation method of light-emitting diode epitaxial wafer and light-emitting diode epitaxial wafer Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 89
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 86
- 229910052738 indium Inorganic materials 0.000 claims abstract description 77
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 77
- 229910052749 magnesium Inorganic materials 0.000 claims abstract description 39
- 239000011777 magnesium Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000012159 carrier gas Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 25
- -1 magnesium nitride Chemical class 0.000 claims abstract description 23
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 16
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 239000001257 hydrogen Substances 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 4
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 276
- 235000012431 wafers Nutrition 0.000 description 31
- 239000013078 crystal Substances 0.000 description 13
- 238000004020 luminiscence type Methods 0.000 description 13
- 150000001875 compounds Chemical class 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 7
- 238000010348 incorporation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- MQBKFPBIERIQRQ-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene;cyclopentane Chemical compound [Mg+2].C=1C=C[CH-]C=1.[CH-]1[CH-][CH-][CH-][CH-]1 MQBKFPBIERIQRQ-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a preparation method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: providing a substrate; sequentially growing a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer on the substrate, wherein the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer; at least one of the low-temperature P-type layer and the high-temperature P-type layer is of a superlattice structure, the superlattice structure comprises a plurality of sequentially stacked sublayers, and each sublayer is formed in the following mode: continuously introducing an indium source, a gallium source, ammonia gas and carrier gas to form an indium gallium nitride layer; stopping introducing the indium source and the gallium source, and simultaneously continuously introducing ammonia gas and carrier gas to process the indium gallium nitride layer; and beginning to introduce a magnesium source, and simultaneously continuing to introduce ammonia gas and carrier gas to form a magnesium nitride layer on the indium gallium nitride layer. The invention can improve the concentration of holes in the superlattice structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. As a novel high-efficiency, environment-friendly and green solid-state illumination light source, LEDs are being widely applied in the fields of illumination, display screens, signal lamps, backlight sources, toys, and the like. In the development of the light emitting diode industry, the development of a wide bandgap (Eg > 2.3eV) semiconductor material, gallium nitride (GaN), is very rapid.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The P-type semiconductor layer is used for providing holes for carrying out compound luminescence, the N-type semiconductor layer is used for providing electrons for carrying out compound luminescence, the active layer is used for carrying out radiation compound luminescence of the electrons and the holes, and the substrate is used for providing a growth surface for the epitaxial material; the material of the substrate is generally selected from sapphire, the material of the N-type semiconductor layer and the like is generally selected from gallium nitride, the sapphire and the gallium nitride are heterogeneous materials, large lattice mismatch exists between the sapphire and the gallium nitride, and the buffer layer is used for relieving the lattice mismatch between the substrate and the N-type semiconductor layer.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
unintentionally doped intrinsic gallium nitride has high background electron concentration (electron concentration is up to 10)16/cm3) Therefore, the intrinsic gallium nitride is N-type, which results in that the difficulty of obtaining P-type gallium nitride is much higher than that of obtaining N-type gallium nitride, and the activation rate of P-type impurities in the P-type gallium nitride is very low, so that a P-type semiconductor layer formed by the P-type gallium nitride is difficult to realize high hole concentration, and the number of holes provided by the P-type semiconductor layer is small, so that the number of holes for performing composite light emission with electrons in the active layer is small, the composite light emission efficiency in the active layer is limited, and finally the light emission efficiency of the LED is low.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer, which can solve the problem that in the prior art, a P-type semiconductor layer is difficult to realize high hole concentration, and finally the luminous efficiency of an LED is low. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a method for preparing a light emitting diode epitaxial wafer, where the method for preparing the light emitting diode epitaxial wafer includes:
providing a substrate;
sequentially growing a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer on the substrate, wherein the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer;
at least one of the low-temperature P-type layer and the high-temperature P-type layer is of a superlattice structure, the superlattice structure comprises a plurality of sequentially stacked sublayers, and each sublayer is formed in the following mode:
continuously introducing an indium source, a gallium source, ammonia gas and carrier gas to form an indium gallium nitride layer;
stopping introducing the indium source and the gallium source, and simultaneously continuously introducing ammonia gas and carrier gas to process the indium gallium nitride layer;
and beginning to introduce a magnesium source, and simultaneously continuing to introduce ammonia gas and carrier gas to form a magnesium nitride layer on the indium gallium nitride layer.
Optionally, the carrier gas is a mixed gas of nitrogen and hydrogen, and a proportion of hydrogen in the carrier gas is smaller when the low-temperature P-type layer grows than that of hydrogen in the carrier gas when the high-temperature P-type layer grows.
Optionally, the number of sublayers is 5 to 30.
Optionally, the thickness of the indium gallium nitride layer is 10nm to 50 nm.
Optionally, the processing time of the indium gallium nitride layer is 5s to 30 s.
Optionally, the forming time of the magnesium nitride layer is 10s to 5 min.
Optionally, the growth temperature is kept constant during the formation of the individual sub-layers.
Optionally, the growth temperature of the low-temperature P-type layer is 750 ℃ to 800 ℃.
Optionally, the growth temperature of the high-temperature P-type layer is 950 ℃ to 1000 ℃.
On the other hand, the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer, wherein the buffer layer, the N-type semiconductor layer, the active layer, the low-temperature P-type layer and the high-temperature P-type layer are sequentially laminated on the substrate, and the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer; at least one of the low-temperature P-type layer and the high-temperature P-type layer is of a superlattice structure, the superlattice structure comprises a plurality of sublayers which are sequentially stacked, each sublayer comprises an indium gallium nitride layer and a magnesium nitride layer which are sequentially stacked, and ammonia gas and carrier gas are introduced into the indium gallium nitride layer for treatment before the magnesium nitride layers are stacked.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by forming the indium gallium nitride layer first, the indium component in the indium gallium nitride layer can reduce the incorporation efficiency of gallium, reduce nitrogen vacancies (vacancies of group V elements), increase vacancies of group III elements, facilitate the incorporation of magnesium, and improve the concentration of holes in the superlattice structure. And then the indium gallium nitride layer is processed by nitrogen and carrier gas, so that partial gallium atoms on the surface of the indium gallium nitride layer can be desorbed to form gallium vacancies, magnesium atoms can be favorably incorporated, and the concentration of holes in the superlattice structure can be further improved. And finally, forming a magnesium nitride layer on the indium gallium nitride layer, wherein the growth of the indium gallium nitride layer is interrupted when the magnesium nitride layer grows, so that the formation of the magnesium nitride layer on the indium gallium nitride layer is equivalent to doping magnesium after the growth of the III-V group compound semiconductor is stopped, and the discontinuous growth of gallium nitride can effectively inhibit the formation of stacking dislocation when magnesium atoms are doped with gallium nitride, reduce the defect density, reduce the self-compensation effect, improve the crystal quality and finally improve the concentration of holes in the superlattice structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
FIG. 2 is a flow chart of a manner in which individual sub-layers may be formed as provided by an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 4 is a schematic structural view of a superlattice structure provided in accordance with an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a method for preparing a light emitting diode epitaxial wafer, fig. 1 is a flow chart of the method for preparing the light emitting diode epitaxial wafer provided by the embodiment of the invention, and referring to fig. 1, the method for preparing the light emitting diode epitaxial wafer comprises the following steps:
step 101: a substrate is provided.
Specifically, the material of the substrate may be one of sapphire, silicon, and silicon carbide.
Optionally, before step 101, the preparation method may further include:
controlling the temperature to be 1000-1200 ℃ (preferably 1100 ℃), and annealing the substrate for 1-10 minutes (preferably 8 minutes) in a hydrogen atmosphere;
the substrate is subjected to a nitridation process.
The surface of the substrate is cleaned by adopting the steps, so that the phenomenon that impurities are doped into the epitaxial wafer to influence the overall crystal quality is avoided, and the luminous efficiency of the LED is reduced.
Step 102: a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer are sequentially grown on a substrate.
In this embodiment, the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer.
The growth temperature of the low-temperature P-type layer is low, so that indium precipitation caused by the fact that indium-nitrogen bonds in the active layer are broken at high temperature can be effectively avoided, and the active layer is protected from being damaged. Meanwhile, the growth temperature of the high-temperature P-type layer is higher, the good crystal quality of the high-temperature P-type layer can be guaranteed, the influence on the poor crystal quality of the whole epitaxial wafer and the influence on the luminous efficiency of the LED can be avoided, and the improvement on the concentration of holes in the superlattice structure is facilitated.
Accordingly, the molar content of the indium component in the low-temperature P-type layer is smaller than that in the high-temperature P-type layer.
Alternatively, the growth temperature of the low-temperature P-type layer may be 750 to 800 ℃, preferably 760 ℃.
If the growth temperature of the low-temperature P-type layer is lower than 750 ℃, the growth quality of the low-temperature P-type layer is possibly poor due to too low growth temperature of the low-temperature P-type layer, so that the overall crystal quality of the epitaxial wafer is poor, the compound luminescence of electrons and holes is influenced, and the luminous efficiency of the LED is reduced; if the growth temperature of the low-temperature P-type layer is higher than 800 ℃, the low-temperature P-type layer may not protect the active layer due to too high growth temperature of the low-temperature P-type layer, so that an indium nitrogen bond in the active layer is broken at high temperature to cause indium precipitation, which affects the compound luminescence of electrons and holes and reduces the luminous efficiency of the LED.
Alternatively, the growth temperature of the high temperature P-type layer may be 950 to 1000 deg.c, preferably 970 deg.c.
If the growth temperature of the high-temperature P-type layer is lower than 950 ℃, the growth quality of the high-temperature P-type layer is possibly poor due to too low growth temperature of the high-temperature P-type layer, so that the overall crystal quality of the epitaxial wafer is poor, the compound luminescence of electrons and holes is influenced, and the luminous efficiency of the LED is reduced; if the growth temperature of the high-temperature P-type layer is higher than 1000 ℃, the active layer may be damaged due to the high growth temperature of the high-temperature P-type layer, and indium is separated out due to the breakage of indium-nitrogen bonds in the active layer at high temperature, which affects the recombination luminescence of electrons and holes and reduces the luminous efficiency of the LED.
In this embodiment, at least one of the low-temperature P-type layer and the high-temperature P-type layer is a superlattice structure including a plurality of sub-layers stacked in sequence.
Specifically, the low-temperature P-type layer may be a superlattice structure, and the high-temperature P-type layer may be a single-layer structure; or the low-temperature P-type layer is of a single-layer structure, and the high-temperature P-type layer is of a superlattice structure; the low-temperature P-type layer can also be of a superlattice structure, and the high-temperature P-type layer can be of a superlattice structure. Wherein, the single-layer structure can be a P-type gallium nitride layer.
Fig. 2 is a flow chart of the manner in which the individual sub-layers are formed, and referring to fig. 2, each sub-layer is formed as follows:
step S1: continuously introducing an indium source, a gallium source, ammonia gas and carrier gas to form an indium gallium nitride layer;
step S2: stopping introducing the indium source and the gallium source, and simultaneously continuously introducing ammonia gas and carrier gas to process the indium gallium nitride layer;
step S3: and beginning to introduce a magnesium source, and simultaneously continuing to introduce ammonia gas and carrier gas to form a magnesium nitride layer on the indium gallium nitride layer.
According to the embodiment of the invention, the indium gallium nitride layer is formed firstly, and the indium component in the indium gallium nitride layer can reduce the incorporation efficiency of gallium, reduce nitrogen vacancies (V-group element vacancies), increase III-group element vacancies, facilitate the incorporation of magnesium and improve the concentration of holes in the superlattice structure.
And then the indium gallium nitride layer is processed by nitrogen and carrier gas, so that partial gallium atoms on the surface of the indium gallium nitride layer can be desorbed to form gallium vacancies, magnesium atoms can be favorably incorporated, and the concentration of holes in the superlattice structure can be further improved.
And finally, forming a magnesium nitride layer on the indium gallium nitride layer, wherein the growth of the indium gallium nitride layer is interrupted when the magnesium nitride layer grows, so that the formation of the magnesium nitride layer on the indium gallium nitride layer is equivalent to doping magnesium after the growth of the III-V group compound semiconductor is stopped, and the discontinuous growth of gallium nitride can effectively inhibit the formation of stacking dislocation when magnesium atoms are doped with gallium nitride, reduce the defect density, reduce the self-compensation effect, improve the crystal quality and finally improve the concentration of holes in the superlattice structure.
In a specific implementation, each sub-layer in the superlattice structure is formed by sequentially performing steps S1 to S3, that is, when the superlattice structure is formed, steps S1 to S3 are performed first to form a first sub-layer; sequentially executing the step S1 to the step S3 to form a second sublayer; then, steps S1 to S3 are sequentially performed, and the third sub-layer … … is formed, and steps S1 to S3 are cyclically performed until all sub-layers in the superlattice structure are formed.
In particular, the growth temperature may remain unchanged during the formation of the individual sub-layers.
Likewise, the carrier gas may also remain unchanged during the formation of the individual sublayers.
By adopting the process conditions, on one hand, the stability of the growth environment in the process of forming the sub-layer can be ensured, the negative influence caused by the change of the process conditions is avoided, and on the other hand, the method is convenient to realize.
Optionally, the carrier gas may be a mixed gas of nitrogen and hydrogen, and a proportion of hydrogen in the carrier gas when the low-temperature P-type layer is grown may be smaller than a proportion of hydrogen in the carrier gas when the high-temperature P-type layer is grown.
When the low-temperature P-type layer grows, the proportion of hydrogen in the carrier gas is smaller, namely, the amount of introduced hydrogen is smaller when the low-temperature P-type layer grows, and the active layer is prevented from being damaged by the hydrogen under the etching effect. Meanwhile, the proportion of hydrogen in the carrier gas is larger when the high-temperature P-type layer grows, namely, the amount of the introduced hydrogen is larger when the high-temperature P-type layer grows, the crystal quality of the high-temperature P-type layer can be improved, the influence on the poor crystal quality of the whole epitaxial wafer and the influence on the luminous efficiency of the LED are avoided, and the improvement on the concentration of a cavity in the superlattice structure is facilitated.
Preferably, the volume ratio of nitrogen to hydrogen in the carrier gas may be 3:1 when the low-temperature P-type layer is grown, and the volume ratio of nitrogen to hydrogen in the carrier gas may be 3:2 when the high-temperature P-type layer is grown.
Alternatively, the number of sublayers may be 5 to 30.
If the number of the sub-layers is less than 5, the light emission of the recombination of electrons and holes can be influenced due to the insufficient number of the holes, and even the problem of poor quality such as light attenuation and the like can be caused; if the number of sublayers is more than 30, the light extraction efficiency may be affected due to the P-type layer thickness being too thick.
Preferably, the number of sublayers in the low-temperature P-type layer may be greater than the number of sublayers in the high-temperature P-type layer.
The low-temperature P-type layer is of a structure mainly providing holes, so that the number of sublayers in the low-temperature P-type layer is large, and the number of holes injected into the active layer can be ensured; and the number of sublayers in the high-temperature P-type layer is less, so that the influence on light emission caused by the fact that the high-temperature P-type layer is too thick can be effectively avoided, and the light extraction efficiency is reduced.
More preferably, the number of sublayers in the low-temperature P-type layer may be 30, and the number of sublayers in the high-temperature P-type layer may be 5.
Alternatively, the thickness of the indium gallium nitride layer may be 10nm to 50nm, preferably 30 nm.
If the thickness of the indium gallium nitride layer is less than 10nm, the thickness of the indium gallium nitride layer is too small to provide enough space for the incorporation of magnesium, which may affect the number of holes provided by the superlattice structure and limit the compound light emission of electrons and holes of the active layer, resulting in lower light emission efficiency of the LED; if the thickness of the indium gallium nitride layer is larger than 50nm, the growth quality of the superlattice structure may be affected due to the too large thickness of the indium gallium nitride layer, so that the overall crystal quality of the epitaxial wafer is poor, the compound luminescence of electrons and holes is affected, and the luminous efficiency of the LED is reduced.
Alternatively, the molar content of the indium component in the indium gallium nitride layer may be 1% to 10%, preferably 5%.
If the molar content of the indium component in the indium gallium nitride layer is less than 1%, the incorporation efficiency of the indium component in the indium gallium nitride layer cannot be effectively reduced due to the fact that the molar content of the indium component in the indium gallium nitride layer is too small, and the effect of improving the hole concentration in the superlattice structure cannot be achieved; if the molar content of the indium component in the indium gallium nitride layer is greater than 10%, the growth quality of the superlattice structure may be affected due to too large molar content of the indium component in the indium gallium nitride layer, so that the overall crystal quality of the epitaxial wafer is poor, the compound luminescence of electrons and holes is affected, and the luminous efficiency of the LED is reduced.
Alternatively, the processing time of the indium gallium nitride layer may be 5s to 30s, preferably 10 s.
If the processing time of the indium gallium nitride layer is less than 5s, gallium atoms on the surface of the indium gallium nitride layer cannot be desorbed by the processing due to the too short processing time of the indium gallium nitride layer, so that the effect of improving the hole concentration in the superlattice structure cannot be achieved; if the processing time of the ingan layer is longer than 30s, the structure of the ingan layer may be damaged due to too long processing time of the ingan layer, which is not favorable for increasing the hole concentration in the superlattice structure.
Alternatively, the formation time of the magnesium nitride layer may be 10s to 5min, preferably 3 min.
If the forming time of the magnesium nitride layer is less than 10s, insufficient magnesium may be doped into the sub-layer due to too short forming time of the magnesium nitride layer, the number of holes provided by the superlattice structure is affected, the recombination luminescence of electrons and holes of the active layer is limited, and the luminous efficiency of the LED is low; if the forming time of the magnesium nitride layer is more than 5min, unnecessary defects may be introduced due to too long forming time of the magnesium nitride layer, which affects the growth quality of the superlattice structure, causes poor crystal quality of the whole epitaxial wafer, affects the recombination luminescence of electrons and holes, and reduces the luminous efficiency of the LED.
Further, the flow rate of the magnesium source may be 1. mu. mol/min to 5. mu. mol/min, preferably 3.8. mu. mol/min.
If the flow rate of the magnesium source is less than 1 mu mol/min, insufficient magnesium may be doped into the sub-layer due to too small flow rate of the magnesium source, the number of holes provided by the superlattice structure is influenced, the recombination luminescence of electrons and holes of the active layer is limited, and the luminous efficiency of the LED is low; if the flow rate of the magnesium source is more than 5 mu mol/min, unnecessary defects can be introduced due to too much flow rate of the magnesium source, the growth quality of a superlattice structure is influenced, the overall crystal quality of an epitaxial wafer is poor, the compound luminescence of electrons and holes is influenced, and the luminous efficiency of the LED is reduced.
Specifically, the material of the buffer layer may employ aluminum nitride (AlN) or gallium nitride (GaN). The material of the N-type semiconductor layer may be N-type doped gallium nitride (gan), and the N-type doping may be silicon (Si) doping or germanium (Ge) doping. The quantum well may be indium gallium nitride (InGaN), and the quantum barrier may be gallium nitride (gan).
Further, this step 202 may include:
firstly, forming a buffer layer with the thickness of 15 nm-35 nm (preferably 25nm) on a substrate by adopting a Physical Vapor Deposition (PVD);
and a second step of growing an N-type semiconductor layer of 1 to 5 μm (preferably 3 μm) thickness on the buffer layer by controlling the temperature to 1000 to 1100 deg.C (preferably 1050 deg.C) and the pressure to 200to 300torr (preferably 250torr) on the buffer layerThe doping concentration of the N-type dopant is 1018cm-3～1019cm-3(preferably 5 x 10)18cm-3)；
Thirdly, controlling the pressure to be 100-500 torr (preferably 300torr), and growing an active layer on the N-type semiconductor layer, wherein the active layer comprises a plurality of quantum wells and a plurality of quantum barriers which are alternately grown; the number of quantum wells is the same as that of quantum barriers, and the number of quantum barriers is 5-15 (preferably 10); the thickness of the quantum well is 2.5 nm-3.5 nm (preferably 3nm), the growth temperature of the quantum well is 720 ℃ -829 ℃ (preferably 770 ℃); the thickness of the quantum barrier is 9 nm-20 nm (preferably 15nm), the growth temperature of the quantum barrier is 850 ℃ -959 ℃ (preferably 900 ℃);
fourthly, growing a low-temperature P-type layer on the active layer;
and fifthly, growing a high-temperature P-type layer on the low-temperature P-type layer.
Optionally, before the second step, the preparation method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer with a thickness of 1 μm to 5 μm (preferably 3 μm) is grown on the buffer layer under a temperature of 800 ℃ to 1180 ℃ (preferably 1040 ℃) and a pressure of 120torr to 600torr (preferably 360 torr).
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown on the substrate at a low temperature, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called a high-temperature buffer layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, the two-dimensional recovery layer, and the high-temperature buffer layer are collectively referred to as an undoped gallium nitride layer in this embodiment.
Optionally, before the third step, the preparation method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Accordingly, an active layer is grown on the stress relieving layer.
Specifically, the stress release layer may include a plurality of first sublayers and a plurality of second sublayers, which are alternately stacked; the first sub-layer may be made of indium gallium nitride, and the second sub-layer may be made of gallium nitride. The thickness of the indium gallium nitride layer can be 1nm to 3nm, and preferably 2 nm; the thickness of the gallium nitride layer can be 20 nm-40 nm, preferably 30 nm; the number of the indium gallium nitride layers is the same as that of the gallium nitride layers, and the number of the gallium nitride layers may be 3 to 9, preferably 6.
Further, growing a stress relief layer on the N-type semiconductor layer may include:
the temperature is controlled to be 550 ℃ to 900 ℃ (preferably 755 ℃), the pressure is 50torr to 500torr (preferably 400torr), and the stress release layer is grown on the N-type semiconductor layer.
Optionally, before the fifth step, the preparation method may further include:
and growing an electron blocking layer on the low-temperature P-type layer.
Accordingly, a high temperature P-type layer is grown on the electron blocking layer.
Specifically, the electron blocking layer may be made of P-type doped aluminum gallium nitride (AlGaN) such as AlyGa1-yN，0.1＜y＜0.5。
Further, growing an electron blocking layer on the low temperature P-type layer may include:
the temperature is controlled to be 900-1000 ℃ (preferably 950 ℃), the pressure is controlled to be 100-600 torr (preferably 350torr), and the electron blocking layer with the thickness of 50-150 nm (preferably 100nm) is grown on the low-temperature P-type layer.
Preferably, before growing the electron blocking layer on the active layer, the manufacturing method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 700 ℃ to 900 ℃ (preferably 800 ℃) and the pressure is controlled to be 150torr to 250torr (preferably 200torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fifth step, the preparation method may further include:
and growing a P-type contact layer on the high-temperature P-type layer.
Specifically, the P-type contact layer may be made of one of P-type doped indium gallium nitride, P-type doped gallium nitride, and N-type doped gallium nitride, so as to reduce the barrier of ohmic contact between the epitaxial material and the chip structure.
Further, growing a P-type contact layer on the high-temperature P-type layer may include:
the temperature is controlled to be 700 ℃ to 800 ℃ (preferably 750 ℃) and the pressure is controlled to be 300torr to 600torr (preferably 450torr), and the P type contact layer is grown on the high-temperature P type layer.
After the completion of the epitaxial growth, the temperature is lowered to 500to 900 ℃ (preferably 800 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature, thereby completing the epitaxial growth.
The control of temperature and pressure refers to controlling the temperature and pressure in a reaction chamber for growing epitaxial wafers, such as the temperature and pressure in a Metal Organic Chemical Vapor Deposition (MOCVD) equipment with the model of VeecoK465i C4. During implementation, high-purity hydrogen or high-purity nitrogen or mixed gas of hydrogen and nitrogen is used as carrier gas, high-purity ammonia gas is used as a nitrogen source, trimethyl gallium or triethyl gallium is used as a gallium source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as an N-type dopant, and dicyclopentadienyl magnesium is used as a P-type dopant.
The embodiment of the invention provides a light-emitting diode epitaxial wafer which is suitable for being prepared by adopting the preparation method shown in figure 1. Fig. 3 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention, and referring to fig. 3, the led epitaxial wafer includes a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, an active layer 40, a low-temperature P-type layer 50, and a high-temperature P-type layer 60, wherein the buffer layer 20, the N-type semiconductor layer 30, the active layer 40, the low-temperature P-type layer 50, and the high-temperature P-type layer 60 are sequentially stacked on the substrate 10.
In the present embodiment, the growth temperature of the low-temperature P-type layer 50 is lower than that of the high-temperature P-type layer 60. At least one of the low-temperature P-type layer 50 and the high-temperature P-type layer 60 is a superlattice structure, fig. 4 is a schematic structural diagram of the superlattice structure provided in the embodiment of the present invention, referring to fig. 4, the superlattice structure 100 includes a plurality of sub-layers 200 stacked in sequence, each sub-layer 200 includes an indium gallium nitride layer 300 and a magnesium nitride layer 400 stacked in sequence, and the indium gallium nitride layer 300 is treated by introducing ammonia gas and carrier gas before the magnesium nitride layer 400 is stacked.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer on the substrate, wherein the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer;
at least one of the low-temperature P-type layer and the high-temperature P-type layer is of a superlattice structure, the superlattice structure comprises a plurality of sequentially stacked sublayers, and each sublayer is formed in the following mode:
continuously introducing an indium source, a gallium source, ammonia gas and carrier gas to form an indium gallium nitride layer;
stopping introducing the indium source and the gallium source, and simultaneously continuously introducing ammonia gas and carrier gas to process the indium gallium nitride layer;
and beginning to introduce a magnesium source, and simultaneously continuing to introduce ammonia gas and carrier gas to form a magnesium nitride layer on the indium gallium nitride layer.
2. The method according to claim 1, wherein the carrier gas is a mixed gas of nitrogen and hydrogen, and a proportion of hydrogen in the carrier gas when the low-temperature P-type layer is grown is smaller than a proportion of hydrogen in the carrier gas when the high-temperature P-type layer is grown.
3. A production method according to claim 1 or 2, characterized in that the number of sublayers is 5 to 30.
4. The production method according to claim 1 or 2, wherein the thickness of the indium gallium nitride layer is 10nm to 50 nm.
5. The production method according to claim 1 or 2, wherein the processing time of the indium gallium nitride layer is 5s to 30 s.
6. The production method according to claim 1 or 2, wherein the magnesium nitride layer is formed for a time of 10s to 5 min.
7. A method of manufacturing as claimed in claim 1 or 2, characterized in that the growth temperature is kept constant during the formation of the individual sub-layers.
8. The production method according to claim 1 or 2, wherein the growth temperature of the low-temperature P-type layer is 750 ℃ to 800 ℃.
9. The manufacturing method according to claim 1 or 2, wherein the growth temperature of the high-temperature P-type layer is 950 ℃ to 1000 ℃.
10. A light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer, a low-temperature P-type layer and a high-temperature P-type layer, wherein the buffer layer, the N-type semiconductor layer, the active layer, the low-temperature P-type layer and the high-temperature P-type layer are sequentially laminated on the substrate, and the growth temperature of the low-temperature P-type layer is lower than that of the high-temperature P-type layer; the solar cell is characterized in that at least one of the low-temperature P-type layer and the high-temperature P-type layer is of a superlattice structure, the superlattice structure comprises a plurality of sub-layers which are sequentially stacked, each sub-layer consists of an indium gallium nitride layer and a magnesium nitride layer which are sequentially stacked, and ammonia gas and carrier gas are introduced into the indium gallium nitride layer for treatment before the magnesium nitride layers are stacked.
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| CN112436076A (en) * | 2020-11-20 | 2021-03-02 | 湘能华磊光电股份有限公司 | LED epitaxial structure and growth method |
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| CN106711299A (en) * | 2016-12-19 | 2017-05-24 | 华灿光电（浙江）有限公司 | Epitaxial wafer of light emitting diode and manufacturing method thereof |
| CN107068822A (en) * | 2017-01-16 | 2017-08-18 | 湘能华磊光电股份有限公司 | A kind of smooth extraction efficiency high LED epitaxial structure and its growing method |
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