CN116454184B - High-light-efficiency LED epitaxial wafer, preparation method thereof and LED - Google Patents
High-light-efficiency LED epitaxial wafer, preparation method thereof and LED Download PDFInfo
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- CN116454184B CN116454184B CN202310713677.9A CN202310713677A CN116454184B CN 116454184 B CN116454184 B CN 116454184B CN 202310713677 A CN202310713677 A CN 202310713677A CN 116454184 B CN116454184 B CN 116454184B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
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- 229960003461 dezocine Drugs 0.000 claims abstract description 35
- 230000000903 blocking effect Effects 0.000 claims abstract description 24
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical group [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims abstract description 18
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- 238000000034 method Methods 0.000 claims description 19
- 239000011777 magnesium Substances 0.000 claims description 17
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 15
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- 229910052749 magnesium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
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- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The application provides a high-light-efficiency LED epitaxial wafer, a preparation method thereof and an LED, wherein the high-light-efficiency LED epitaxial wafer comprises an electron blocking layer, and the electron blocking layer comprises a first sub-layer, a second sub-layer and a third sub-layer; the first sub-layer is an AlN layer, the second sub-layer is a DGaN/DAlGaN superlattice layer, and the third sub-layer comprises P-type AlxGa 1‑x N/D y Ga 1‑y N-superlattice layer, P-type Al x Ga 1‑x N thin-layer reduction and D y Ga 1‑y An N thin layer; the DGaN/DAlGaN superlattice layer comprises a DGaN layer and a DAlGaN layer which are periodically and alternately laminated. The application improves the effective injection efficiency of the holes, effectively solves the core difficulty of ionization activation of magnesium atoms, improves the effective activation and incorporation of the magnesium atoms, and improves the generation of the holes, thereby improving the luminous efficiency.
Description
Technical Field
The application relates to the technical field of semiconductor preparation, in particular to a high-light-efficiency LED epitaxial wafer, a preparation method thereof and an LED.
Background
Gallium nitride material is used as a typical representative of third-generation semiconductors, and has the characteristics of large forbidden bandwidth, high electron mobility and the like. Especially, the gallium nitride-based device is widely applied to electronic systems such as wireless communication, radars and the like in microwave and millimeter wave frequency bands, and has very wide development prospect in the fields of photoelectrons and microelectronics.
Currently, conventional GaN diodes generally include a substrate, a buffer layer, n-type GaN, an active layer, an electron blocking layer, and P-type GaN, and the main light emitting source is the active layer. For an epitaxial structure, holes are required to be sourced from Mg ionization of P-type GaN, and an electron blocking layer is an Al component AlGaN layer to act as a barrier for electron overflow, but hole injection is also blocked, and the most important difficulty faced by high-efficiency P-type GaN is that very high Mg acceptor activation energy is effectively overcome while the thermodynamic precondition of high Mg incorporation is met, and the Al component can reduce the activation energy of Mg, so that the extremely low thermal activation efficiency is caused. Because gallium nitride diodes are generally prepared by a Metal Organic Chemical Vapor Deposition (MOCVD) system, the realization of P-type GaN by an MOCVD method is extremely important, and an effective way for realizing the high incorporation efficiency of Mg atoms in the P-type GaN and the effective ionization and activation of the Mg atoms based on the MOCVD method is a key technology to be broken through urgently.
Disclosure of Invention
Based on the above, the application aims to provide a high-light-efficiency LED epitaxial wafer, a preparation method thereof and an LED, so as to solve the defects in the prior art.
In order to achieve the above purpose, the application provides a high light efficiency LED epitaxial wafer, which comprises a substrate, a buffer layer, an N-type layer, an active layer, an electron blocking layer and a P-type layer which are sequentially stacked, wherein the electron blocking layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked on the active layer;
the first sub-layer is an AlN layer, the second sub-layer is a DGaN/DAlGaN superlattice layer, and the third sub-layer comprises P-type Al x Ga 1-x N/D y Ga 1-y N-superlattice layer, P-type Al x Ga 1-x N thin-layer reduction and D y Ga 1-y An N thin layer;
the DGaN/DAlGaN superlattice layer comprises a DGaN layer and a DAlGaN layer which are periodically and alternately laminated, and the P-type Al layer x Ga 1-x N/D y Ga 1-y The N superlattice layer comprises periodically and alternately laminated P-type Al x Ga 1-x N layer and D y Ga 1-y N layer, the P type Al x Ga 1-x The thickness of the N thin layer is smallIn the P-type Al x Ga 1-x Thickness of N layer, D y Ga 1-y The thickness of the N thin layer is smaller than that of the D y Ga 1-y The thickness of the N layer;
wherein D is at least one of boron, indium or carbon.
Preferably, the thickness of the first sub-layer is 4nm-6nm, the thickness of the DGaN layer and the DAlGaN layer are both 4nm-6nm, and the P-type Al x Ga 1-x N layer and said D y Ga 1-y The thickness of the N layer is 3nm-4nm.
Preferably, the P-type Al x Ga 1-x Al element in the N layer gradually decreases along with the period, and D is as follows y Ga 1-y The thickness of the N layer gradually increases along with the period, and the P type Al x Ga 1-x The doping degree of Mg element in the N layer is 1E+16 atoms/cm 3 ~2E+17 atoms/cm 3 。
Preferably, the P-type Al x Ga 1-x N layer and said D y Ga 1-y The value ranges of x and y in the N layers are respectively as follows: x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x<y。
Preferably, the period of the alternate stacking of the DGaN layer and the DAlGaN layer is 2-3, and the P-type Al in the combined structure x Ga 1-x N layer and said D y Ga 1-y The period of the N layers alternately stacked is 3-4.
Preferably, the P-type Al x Ga 1-x N thinner layers and said D y Ga 1-y The concentration of the gallium component in the N-thin layer is respectively lower than that of the P-type Al x Ga 1-x N layer and said D y Ga 1-y Concentration of gallium component in the N layer.
Preferably, the substrate is a sapphire substrate, a SiC substrate or SiO 2 One of the substrates.
In order to achieve the above object, the present application further provides a method for preparing the high-light-efficiency LED epitaxial wafer, which includes:
obtaining a substrate;
introducing nitrogen and hydrogen at a first ambient temperature to perform high-temperature treatment on the substrate, and introducing a nitrogen source and an aluminum source into the MOCVD reaction chamber to deposit a buffer layer on the substrate after the high-temperature treatment;
doping silicon element with a first doping concentration at a second ambient temperature to generate an N-type layer on the buffer layer;
doping aluminum element with a second doping concentration at a third ambient temperature and a first ambient pressure to generate an active layer on the N-type layer;
depositing an electron blocking layer on the active layer by a vapor deposition method at a fourth ambient temperature and a second ambient pressure;
and doping magnesium element with a third doping concentration at a fifth ambient temperature and a third ambient pressure to deposit a P-type layer on the electron blocking layer.
Preferably, the step of depositing the electron blocking layer on the active layer by a vapor deposition method includes:
introducing the nitrogen source, the aluminum source, the boron source and the gallium source into an MOCVD reaction chamber, sequentially generating a first sub-layer, a second sub-layer and a third sub-layer on the active layer by a vapor deposition method, stopping introducing the aluminum source and the gallium source, and carrying out desorption thinning on the surface layer of the third sub-layer to obtain P-type Al x Ga 1-x N thin-layer reduction and D y Ga 1-y And N is a thin layer.
In order to achieve the above purpose, the application also provides an LED, which comprises the high-light-efficiency LED epitaxial wafer.
The beneficial effects of the application are as follows: the first sublayer provides a barrier energy level to block migration of electrons, D element in the second sublayer can be used for inserting or filling blank positions caused by dislocation, dislocation extension caused by line defects is restrained, the probability of defect generation is reduced, meanwhile, adaptive stress between lattices and a stress field generated correspondingly are ensured to be smaller, effective injection efficiency of holes is improved, then efficient incorporation of magnesium atoms is realized by using the surface effect of the third sublayer, namely, the surface layer of the third sublayer is subjected to desorption thinning, the surface layer structure for completing desorption thinning operation is used as a barrier layer, modulation of periodic variation of Al components along the growth direction is realized, core difficulty of ionization activation of magnesium atoms is effectively solved, effective activation and incorporation of magnesium atoms are improved, generation of holes is improved, and light-emitting efficiency is improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
Fig. 1 is a schematic diagram of a high-light-efficiency LED epitaxial wafer according to a first embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing a high-light-efficiency LED epitaxial wafer according to a second embodiment of the present application.
Description of main reference numerals:
the application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Several embodiments of the application are presented in the figures. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, a high-light-efficiency LED epitaxial wafer according to a first embodiment of the present application includes a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, an electron blocking layer and a P-type layer 80 stacked in order.
Wherein: the electron blocking layer includes a first sub-layer 50, a second sub-layer 60, and a third sub-layer 70 laminated on the active layer 40;
the first sub-layer 50 is an AlN layer, and the first sub-layer 50 is used to provide a better barrier energy level;
the second sub-layer 60 is a DGaN/DAlGaN superlattice layer, the DGaN/DAlGaN superlattice layer includes a DGaN layer 61 and a DAlGaN layer 62 that are periodically and alternately stacked, and the DGaN layer 61 and the DAlGaN layer 62 are both superlattice structures;
the third sub-layer 70 comprises sequentially stacked P-type Al x Ga 1-x N/D y Ga 1-y N superlattice layer 71, P-type Al x Ga 1-x N thinner layer 72 and D y Ga 1-y N thinner layer 73, P type Al x Ga 1-x N/D y Ga 1-y The N-superlattice layer 71 includes periodically alternately stacked P-type Al x Ga 1-x N layer 711 and D y Ga 1-y N layer 712, it can be appreciated that by performing desorption thinning of the surface layer of the pre-formed third sub-layer 70, P-type Al is obtained x Ga 1-x N thinner layer 72 and D y Ga 1-y The N-thinning layer 73 is specifically formed by desorbing and thinning the surface layer of the third sub-layer 70, and the surface layer of the third sub-layer spontaneously converts to P-type Al with sub-nanometer thickness due to the characteristic that Ga atoms in the AlGaN system are easier to desorb than Al atoms x Ga 1-x N-thinning layer 72 and D y Ga 1-y The N thinning layer 73 and the rest structure of the third sub-layer 70 which is not subjected to desorption thinning are P-type Al x Ga 1-x N/D y Ga 1-y N superlattice layer 71, thereby P-type Al x Ga 1-x N thinningLayers 72 and D y Ga 1-y The concentration of the gallium component in the N-thin layer 73 is lower than that of P-type Al, respectively x Ga 1-x N layer 711 and D y Ga 1-y Concentration of gallium component in N layer 712 and P-type Al x Ga 1-x The thickness of the N-thinner layer 72 is smaller than that of P-type Al x Ga 1-x Thickness of N layer 711, D y Ga 1-y The thickness of the N-thinned layer 73 is less than D y Ga 1-y The thickness of the N layer 712 is such that D is at least one of boron, indium, or carbon.
In some of these embodiments, the first sub-layer 50 has a thickness of 4nm to 6nm, the DGaN layer 61 and the DAlGaN layer 62 have a thickness of 4nm to 6nm, and the P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The thickness of the N layer 712 is 3nm-4nm. The optimal thickness of the first sub-layer 50 is 5nm, the optimal thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both 5nm, and the P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The optimal thickness of the N layer 712 is 3.5nm.
It will be appreciated that since the DGaN layer 61 and the DAlGaN layer 62 in the second sub-layer 60 are relatively thin, the stress generated at the interface can be continuously distorted, thereby reducing the occurrence of defects.
In some of these embodiments, the DGaN layers 61 and DAlGaN layers 62 are alternately stacked with a period of 2-3, and the P-type Al in the combined structure x Ga 1-x N layer 711 and D y Ga 1-y The period of the alternating stacking of the N layers 712 is 3-4.
In some of these embodiments, P-type Al x Ga 1-x The Al element in the N layer 711 gradually decreases with the period, D y Ga 1-y The thickness of the N layer 712 increases gradually with the period, P-type Al x Ga 1-x The doping degree of Mg element in the N layer 711 is 1E+16 atoms/cm 3 ~2E+17 atoms/cm 3 。
In some of these embodiments, P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The range of values of x and y in the N layer 712 is: x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x<y。
In some of these embodiments, the substrate 10 is a sapphire substrate, siCSubstrate and SiO 2 One of the substrates.
In specific implementation, the first sub-layer 50 provides a barrier energy level to block migration of electrons, the D element in the second sub-layer 60 can be used for inserting or filling blank positions caused by dislocation, dislocation extension caused by line defects is restrained, adaptive stress between lattices and a stress field generated correspondingly are small while probability of defect generation is reduced, effective injection efficiency of holes is improved, then efficient incorporation of magnesium atoms is achieved by using the surface effect of the third sub-layer 70, namely, a process of desorption thinning operation is achieved by using a surface layer structure of the third sub-layer 70 as a barrier layer, modulation of periodic variation of Al components along the growth direction is achieved, core difficulty of ionization activation of magnesium atoms is effectively solved, effective activation and incorporation of magnesium atoms are improved, generation of holes is improved, and light emitting efficiency is improved.
It should be noted that the foregoing implementation process is only for illustrating the feasibility of the present application, but this does not represent that the LED epitaxial wafer with high light efficiency of the present application has only one implementation process, and instead, the LED epitaxial wafer with high light efficiency of the present application can be incorporated into the feasible implementation of the present application.
Referring to fig. 2, a method for preparing a high-light-efficiency LED epitaxial wafer according to a second embodiment of the present application is used for preparing a high-light-efficiency LED epitaxial wafer according to a first embodiment, and includes the following steps:
step S101, a substrate 10 is obtained;
wherein the substrate 10 may be a sapphire substrate, a SiC substrate, or SiO 2 One of the substrates.
Step S102, introducing nitrogen and hydrogen at a first ambient temperature to perform high-temperature treatment on the substrate 10, and introducing a nitrogen source and an aluminum source into the MOCVD reaction chamber to deposit a buffer layer 20 on the substrate 10 after the high-temperature treatment;
the substrate 10 is subjected to a high temperature treatment, which can avoid oxidation or contamination of the surface of the substrate 10, and it can be understood that the first ambient temperature is 1000 ℃ to 1150 ℃, and the high temperature treatment is specifically that the substrate 10 is placed in a MOCVD (Metal-organic chemical vapor deposition) reaction chamber, and then high-purity ammonia and nitrogen gas are introduced into the MOCVD reaction chamber at the first ambient temperature, and the substrate is treated at a high temperature for 10min to 15min.
It is to be noted that, the substrate 10 after the high temperature treatment is transferred into a PVD (Physical Vapor Deposition ) reaction chamber, ammonia gas is introduced into the PVD reaction chamber, trimethylaluminum is used as a target, and direct current is used to perform magnetron sputtering on the substrate, so as to generate the buffer layer 20 with a thickness of 10nm-30nm, that is, trimethylaluminum and ammonia gas are respectively used as an aluminum source and a nitrogen source, and the material of the buffer layer 20 is aluminum nitride. In this embodiment, the optimal thickness of the buffer layer 20 is 15nm.
Step S103, doping silicon element with a first doping concentration at a second ambient temperature to generate an N-type layer 30 on the buffer layer 20;
wherein the second ambient temperature is 1000-1150 ℃, and the first doping concentration of the silicon element is 1.5+E18 atoms/cm 3 The N-type layer 30 is a GaN layer, the thickness of the N-type layer 30 is 2nm-3nm, specifically, the substrate 10 with the buffer layer 20 is transferred into the MOCVD reaction chamber, and the first doping concentration of silicon element is 1.5+E18 atoms/cm at 1000 DEG C 3 The N-type layer 30 having a thickness of 2.5nm is grown on the buffer layer 20, i.e. the optimum thickness of the N-type layer 30 is 2.5nm.
Step S104, doping aluminum element with a second doping concentration under a third ambient temperature and a first ambient pressure to generate an active layer 40 on the N-type layer 30;
the third ambient temperature is 800 ℃ to 900 ℃, the thickness of the active layer 40 is 3nm to 3.5nm, the active layer 40 comprises InGaN quantum well layers and AlGaN quantum barrier layers which are alternately stacked, the stacking period of the active layer 40 is 6 to 15, the growth temperature of the InGaN quantum well layers in the active layer 40 is 800 ℃ to 900 ℃, the thickness of the InGaN quantum well layers is 3nm nm to 3.5nm, the growth temperature of the AlGaN quantum barrier layers is 850 ℃ to 900 ℃ and the growth pressure is 200torr to 250torr, the thickness of the AlGaN quantum barrier layers is 9 nm nm to 12nm, and the Al composition is 0.1.
In order to smoothly grow the active layer 40, the ambient temperature in the MOCVD reaction chamber is 900 ℃ and high purity NH is adopted 3 As an N source, TMIn provides an In source, trimethylgallium (TMGa) and triethylgallium (TEGa) as a gallium source, and trimethylaluminum (TMAl) as an aluminum source, and an InGaN quantum well layer and an AlGaN quantum barrier layer, which are alternately stacked, are formed on the N-type layer 30 by a vapor deposition method, to obtain the desired active layer 40.
Step S105 of depositing an electron blocking layer on the active layer 40 by a vapor deposition method at a fourth ambient temperature and a second ambient pressure;
wherein the fourth ambient temperature is 900 ℃ to 1000 ℃, the second ambient pressure is 100torr to 200torr, and the electron blocking layer comprises a first sub-layer 50, a second sub-layer 60 and a third sub-layer 70 laminated on the active layer.
At step S106, doping magnesium element with a third doping concentration at a fifth ambient temperature and a third ambient pressure to deposit the P-type layer 80 on the electron blocking layer.
Wherein, the P-type layer 80 is a GaN layer, and the growth conditions of the P-type layer 80 are as follows: the growth temperature is 1000 ℃ to 1100 ℃, the growth pressure is 100torr to 600torr, and the doping concentration of magnesium element is 1E+19 atoms/cm 3 ~5E+20 atoms/cm 3 . Under the above growth conditions, the P-type layer 80 can be grown on the electron blocking layer to a thickness of 20nm-200nm, that is, the fifth ambient temperature is 1000-1100deg.C, the third ambient pressure is 100-600 torr, and the third doping concentration is 1E+19 atoms/cm 3 ~5E+20 atoms/cm 3 Wherein the optimum value of the fifth ambient temperature is 1050 ℃, the optimum value of the third ambient pressure is 200torr, and the optimum value of the third doping concentration is 5E+19 atoms/cm 3 。
Specifically, the growth temperature is 1050 ℃, the growth pressure is 200torr, and the doping concentration of magnesium element5E+19 atoms/cm 3 The P-type layer 80 is grown on the electron blocking layer to a thickness of 100nm, it is understood that too high a doping concentration of magnesium may deteriorate the crystal quality, while a lower doping concentration may affect the hole concentration.
Through the steps, the first sub-layer 50 is utilized to provide a barrier energy level to block migration of electrons, the D element in the second sub-layer 60 can be used for inserting or filling blank positions caused by dislocation, dislocation extension caused by line defects is restrained, the probability of defects is reduced, meanwhile, adaptive stress between lattices and a stress field generated correspondingly are ensured to be smaller, effective injection efficiency of holes is improved, then the surface effect of the third sub-layer 70 is utilized to realize efficient incorporation of magnesium atoms, namely, the surface layer structure of the desorption thinning operation is utilized as a barrier layer, modulation of periodic variation of Al components along the growth direction is realized, so that core difficulty of ionization activation of magnesium atoms is effectively solved, effective activation and incorporation of magnesium atoms are improved, generation of holes is improved, and luminous efficiency is improved.
In some of these embodiments, the step of depositing an electron blocking layer on the active layer 40 by a vapor deposition method includes:
introducing the nitrogen source, the aluminum source, the boron source and the gallium source into an MOCVD reaction chamber, sequentially generating a first sub-layer 50, a second sub-layer 60 and a third sub-layer 70 on the active layer 40 by a vapor deposition method, stopping introducing the aluminum source and the gallium source, and desorbing and thinning the surface layer of the third sub-layer 70 to obtain P-type Al x Ga 1-x N thinner layer 72 and D y Ga 1-y An N-thinning layer 73.
Wherein the first sub-layer 50 is an AlN layer, and the first sub-layer 50 is configured to provide a better barrier energy level; the second sub-layer 60 is a DGaN/DAlGaN superlattice layer, the DGaN/DAlGaN superlattice layer includes a DGaN layer 61 and a DAlGaN layer 62 that are periodically and alternately stacked, and the DGaN layer 61 and the DAlGaN layer 62 are both superlattice structures; the third sub-layer 70 comprises sequentially stacked P-type Al x Ga 1-x N/D y Ga 1-y N superlattice layer 71, P-type Al x Ga 1-x N thinner layer 72 and D y Ga 1-y N thinner layer 73, P type Al x Ga 1-x N/D y Ga 1-y The N-superlattice layer 71 includes periodically alternately stacked P-type Al x Ga 1-x N layer 711 and D y Ga 1-y N layer 712.
It can be appreciated that the P-type Al is obtained by subjecting the surface layer of the pre-formed third sub-layer 70 to desorption thinning x Ga 1-x N thinner layer 72 and D y Ga 1-y The N-thinning layer 73 is specifically formed by desorbing and thinning the surface layer of the third sub-layer 70, and the surface layer of the third sub-layer spontaneously converts to P-type Al with sub-nanometer thickness due to the characteristic that Ga atoms in the AlGaN system are easier to desorb than Al atoms x Ga 1-x N-thinning layer 72 and D y Ga 1-y The N thinning layer 73 and the rest structure of the third sub-layer 70 which is not subjected to desorption thinning are P-type Al x Ga 1-x N/D y Ga 1-y N superlattice layer 71, thereby P-type Al x Ga 1-x N-thinning layer 72 and D y Ga 1-y The concentration of the gallium component in the N-thin layer 73 is lower than that of P-type Al, respectively x Ga 1-x N layer 711 and D y Ga 1-y Concentration of gallium component in N layer 712 and P-type Al x Ga 1-x The thickness of the N-thinner layer 72 is smaller than that of P-type Al x Ga 1-x Thickness of N layer 711, D y Ga 1-y The thickness of the N-thinned layer 73 is less than D y Ga 1-y The thickness of the N layer 712 is such that D is at least one of boron, indium, or carbon.
In some embodiments, the thickness of the first sub-layer 50 is 4nm-6nm, if the thickness is less than 4nm, it is difficult to block the migration of electrons, and the potential energy is not controlled to be higher than the crystal quality, so that defects are easily generated, and thus the effective injection efficiency of holes cannot be effectively improved, if the thickness is greater than 6nm, the working voltage of the product is improved, which is unfavorable for improving the light emitting efficiency, for example, the thickness of the first sub-layer 50 is 4nm, 5nm or 6nm.
In some of these embodiments, DGaN layer 61 and DAlGaN layer 62 are both 4nm-6nm thick and P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The thickness of the N layer 712 is 3nm-4nm.
When the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both smaller than 4nm, the number of D may be insufficient in the stress process generated by the twisted interface due to the excessive thinness, so that it is difficult to fill the blank positions caused by most of the dislocations, and the required requirements are not met; when the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both greater than 6nm, the thickness is relatively too thick to facilitate the distortion of the stress generated at the interface; and when P-type Al x Ga 1-x N layer 711 and D y Ga 1-y When the thickness of the N layer 712 is less than 3nm, the effective activation and incorporation of magnesium are not improved, the generation of holes is not improved, and when P-type Al x Ga 1-x N layer 711 and D y Ga 1-y When the thickness of the N layer 712 is greater than 4nm, it is difficult to control the crystal quality, which is disadvantageous for improving the light emitting efficiency.
The optimal thickness of the first sub-layer 50 is 5nm, the optimal thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both 5nm, and the P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The optimal thickness of the N layer 712 is 3.5nm. Experiments show that when the first sub-layer, the DGaN layer 61, the DAlGaN layer 62 and the P-type Al layer are formed x Ga 1-x N layer 711 and D y Ga 1-y The N layer 712 is at an optimal thickness to produce optimal light efficiency.
It will be appreciated that since the DGaN layer 61 and the DAlGaN layer 62 in the second sub-layer 60 are relatively thin, the stress generated at the interface can be continuously distorted, thereby reducing the occurrence of defects.
In some of these embodiments, the DGaN layers 61 and DAlGaN layers 62 are alternately stacked with a period of 2-3, and the P-type Al in the combined structure x Ga 1-x N layer 711 and D y Ga 1-y The period of the alternating stacking of the N layers 712 is 3-4.
In some of these embodiments, P-type Al x Ga 1-x The Al element in the N layer 711 gradually decreases with the period, D y Ga 1-y The thickness of the N layer 712 increases gradually with the period, P-type Al x Ga 1-x The doping degree of Mg element in the N layer 711 is 1E+16 atoms/cm 3 ~2E+17 atoms/cm 3 。
In some of these embodiments, P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The range of values of x and y in the N layer 712 is: x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x<y。
In one embodiment, the following test examples are given for illustration:
in the test, a conventional LED epitaxial wafer is used as a control group, and the structure of the conventional LED epitaxial wafer is basically consistent with that of the high-light-efficiency LED epitaxial wafer provided by the application, and the difference is that the electron blocking layer is of a conventional structure and has a thickness of 50nm.
6 test groups were set up, test group 1, test group 2, test group 3, test group 4, test group 5 and test group 6, respectively.
The structure in test group 1 was substantially identical to that in the present application, except that the first sub-layer 50 in the electron blocking layer had a thickness of 5nm, the DGaN layers 61 and DAlGaN layers 62 had a thickness of 4nm, and the DGaN layers 61 and DAlGaN layers 62 were alternately stacked with a period of 3, P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The N layer 712 has a thickness of 3nm and P-type Al x Ga 1-x N layer 711 and D y Ga 1-y The period of the alternating stacking of N layers 712 is 3 and D is boron;
the structure in test set 2 is substantially identical to the structure in test set 1, except for D y Ga 1-y D in N layer 712 is indium;
the structure in test group 3 is substantially identical to that in test group 1, except that the P-type Al x Ga 1-x N layer 711 and P type D y Ga 1-y The N layer 712 has a thickness of 3.5nm and P-type Al x Ga 1-x N layer 711 and P type D y Ga 1-y The period in which the N layers 712 are alternately stacked is 4;
the structure of test set 4 is substantially identical to that in test set 3, except that D y Ga 1-y D in N layer 712 is indium;
the structure of test set 5 is substantially identical to that of test set 3, except that the thickness of both DGaN layer 61 and DAlGaN layer 62 is 5nm.
The structure of test set 6 is substantially identical to the structure in test set 5, except that the thickness of first sub-layer 50 is 4nm.
And optical tests are respectively carried out on the control group, the test group 1, the test group 2, the test group 3, the test group 4, the test group 5 and the test group 6, the obtained test results are improved in light efficiency of the LED epitaxial wafer, and the following table shows that:
the LED in the third embodiment of the application comprises the high-light-efficiency LED epitaxial wafer.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (8)
1. The high-light-efficiency LED epitaxial wafer comprises a substrate, a buffer layer, an N-type layer, an active layer, an electron blocking layer and a P-type layer which are sequentially stacked, and is characterized in that the electron blocking layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked on the active layer;
the first sub-layer is an AlN layer, the second sub-layer is a DGaN/DAlGaN superlattice layer, and the third sub-layer comprises P-type Al which are sequentially stacked x Ga 1-x N/D y Ga 1-y N-superlattice layer, P-type Al x Ga 1-x N thin-layer reduction and D y Ga 1-y An N thin layer;
the DGaN/DAlGaN superlattice layer comprises a DGaN layer and a DAlGaN layer which are periodically and alternately laminated, and the P-type Al layer x Ga 1- x N/D y Ga 1-y The N superlattice layer comprises periodically and alternately laminated P-type Al x Ga 1-x N layer and D y Ga 1-y N layer, the P type Al x Ga 1-x The thickness of the N thin layer is smaller than that of the P-type Al x Ga 1-x Thickness of N layer, D y Ga 1-y The thickness of the N thin layer is smaller than that of the D y Ga 1-y Thickness of N layer, the P type Al x Ga 1-x N thinner layers and said D y Ga 1-y The N thin layers are all formed by spontaneous conversion after desorption thinning of the surface layer of a pre-generated third sub-layer, and the residual structure of the pre-generated third sub-layer which is not subjected to desorption thinning is the P-type Al x Ga 1-x N/D y Ga 1-y N-superlattice layer, the P-type Al x Ga 1-x N thinner layers and said D y Ga 1-y The concentration of the gallium component in the N-thin layer is respectively lower than that of the P-type Al x Ga 1-x N layer and said D y Ga 1-y Concentration of gallium component in the N layer;
wherein D is at least one of boron, indium or carbon, and the P-type Al x Ga 1-x N layer and said D y Ga 1-y The value ranges of x and y in the N layers are respectively as follows: 0 < x < 1,0 < y < 1, and x<y。
2. The high-efficiency LED epitaxial wafer of claim 1, wherein the first sub-layer has a thickness of 4nm to 6nm, the DGaN layer and the DAlGaN layer have a thickness of 4nm to 6nm, and the P-type Al x Ga 1-x N layer and said D y Ga 1-y The N layers all have a thickness of 3nm-4nm。
3. The high light efficiency LED epitaxial wafer of claim 1, wherein said P-type Al x Ga 1-x Al element in the N layer gradually decreases along with the period, and D is as follows y Ga 1-y The thickness of the N layer gradually increases along with the period, and the P type Al x Ga 1-x The doping degree of Mg element in the N layer is 1E+16 atoms/cm 3 ~2E+17 atoms/cm 3 。
4. The high-efficiency LED epitaxial wafer of claim 1, wherein the DGaN layers and the DAlGaN layers are alternately stacked with a period of 2-3, the P-type Al x Ga 1-x N layer and said D y Ga 1-y The period of the N layers alternately stacked is 3-4.
5. The high light efficiency LED epitaxial wafer of claim 1, wherein the substrate is a sapphire substrate, a SiC substrate, and SiO 2 One of the substrates.
6. A method for preparing the high light efficiency LED epitaxial wafer according to any one of claims 1 to 5, comprising:
obtaining a substrate;
introducing nitrogen and hydrogen at a first ambient temperature to perform high-temperature treatment on the substrate, and introducing a nitrogen source and an aluminum source into the MOCVD reaction chamber to deposit a buffer layer on the substrate after the high-temperature treatment;
doping silicon element with a first doping concentration at a second ambient temperature to generate an N-type layer on the buffer layer;
doping aluminum element with a second doping concentration at a third ambient temperature and a first ambient pressure to generate an active layer on the N-type layer;
depositing an electron blocking layer on the active layer by a vapor deposition method at a fourth ambient temperature and a second ambient pressure;
and doping magnesium element with a third doping concentration at a fifth ambient temperature and a third ambient pressure to deposit a P-type layer on the electron blocking layer.
7. The method of manufacturing a high light efficiency LED epitaxial wafer of claim 6, wherein said step of depositing an electron blocking layer on the active layer by vapor deposition comprises:
introducing the nitrogen source, the aluminum source, the boron source and the gallium source into an MOCVD reaction chamber, sequentially generating a first sub-layer, a second sub-layer and a third sub-layer on the active layer by a vapor deposition method, stopping introducing the aluminum source and the gallium source, and desorbing and thinning the surface layer of the third sub-layer generated in advance to obtain P-type Al x Ga 1-x N thin-layer reduction and D y Ga 1-y And N is a thin layer.
8. An LED comprising the high light efficiency LED epitaxial wafer of any one of claims 1-5.
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