CN109273571B - Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents
Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof Download PDFInfo
- Publication number
- CN109273571B CN109273571B CN201811035789.9A CN201811035789A CN109273571B CN 109273571 B CN109273571 B CN 109273571B CN 201811035789 A CN201811035789 A CN 201811035789A CN 109273571 B CN109273571 B CN 109273571B
- Authority
- CN
- China
- Prior art keywords
- type semiconductor
- substrate
- semiconductor layer
- layer
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
The invention discloses a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. The GaN-based light emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on a first surface of the substrate along the extending direction of a first straight line, and the first straight line is parallel to the first surface of the substrate. According to the invention, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the first surface of the substrate along the direction parallel to the first surface of the substrate, so that the stress and defect generated by lattice mismatch of sapphire and gallium nitride can be effectively prevented from continuously extending and expanding along the direction of epitaxial growth, the defect of the stress in an epitaxial wafer is reduced, the crystal growth quality of epitaxial base crystals is improved, and the composite luminescence of current carriers in the active layer is facilitated.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. Gallium nitride (GaN) has good thermal conductivity, and also has excellent characteristics of high temperature resistance, acid and alkali resistance, high hardness and the like, so that gallium nitride (GaN) based LEDs are receiving more and more attention and research.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are sequentially stacked on the substrate. The P-type semiconductor layer is used for providing holes for carrying out compound luminescence, the N-type semiconductor layer is used for providing electrons for carrying out compound luminescence, the active layer is used for carrying out radiation compound luminescence of the electrons and the holes, and the substrate is used for providing a growth surface for the epitaxial material.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the substrate is made of sapphire, the N-type semiconductor layer and the like, gallium nitride is usually selected, the sapphire and the gallium nitride are heterogeneous materials, the lattice constant difference is large, and large lattice mismatch exists between the sapphire and the gallium nitride. The stress and defects generated by lattice mismatch are more introduced into the gallium nitride and continuously extend and expand along the direction of epitaxial growth, reaching the maximum at the top of the epitaxial wafer. These stresses and defects cause the reduction of the crystal growth quality of the epitaxial barrier crystal, affect the recombination luminescence of carriers in the active layer, and limit the application of the gallium nitride-based LED in the long wave band, especially in the green light and above.
Disclosure of Invention
The embodiment of the invention provides a gallium nitride-based light-emitting diode epitaxial wafer and a manufacturing method thereof, which can solve the problem that stress and defect extension generated by lattice mismatch of sapphire and gallium nitride in the prior art influence the composite luminescence of carriers in an active layer. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a gallium nitride-based light emitting diode epitaxial wafer, where the gallium nitride-based light emitting diode epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, where the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially disposed on a first surface of the substrate along an extending direction of a first straight line, and the first straight line is parallel to the first surface of the substrate.
Optionally, the active layer includes a plurality of quantum wells and a plurality of quantum barriers, and the plurality of quantum wells and the plurality of quantum barriers are alternately disposed on the first surface of the substrate along an extending direction of the first straight line.
Preferably, the number of the quantum wells is the same as the number of the quantum barriers, and the number of the quantum barriers is 3 to 15.
Optionally, the lengths of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in a direction perpendicular to the first surface of the substrate are equal.
Preferably, the length of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in a direction perpendicular to the first surface of the substrate is 0.02 to 2 μm.
Optionally, the length of the N-type semiconductor layer in the extending direction of the first straight line is 0.02 μm to 2 μm.
Optionally, the length of the P-type semiconductor layer in the extending direction of the first straight line is 0.02 μm to 2 μm.
In another aspect, an embodiment of the present invention provides a method for manufacturing a gallium nitride-based light emitting diode epitaxial wafer, where the method includes:
providing a substrate;
and growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence along the extension direction of the first straight line.
Optionally, the growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the first surface of the substrate in sequence along the extending direction of the first straight line includes:
arranging a first shielding plate on the first surface of the substrate, wherein the first shielding plate covers the arrangement region of the active layer and the P-type semiconductor layer;
growing an N-type semiconductor layer on the first surface of the substrate;
removing the first shielding plate from the first surface of the substrate;
arranging a second shielding plate on the first surface of the substrate, wherein the second shielding plate covers the arrangement region of the active layer and the N-type semiconductor layer;
growing a P-type semiconductor layer on the first surface of the substrate;
removing the second shielding plate from the first surface of the substrate;
arranging a third shielding plate on the first surface of the substrate, wherein the third shielding plate covers the arrangement regions of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of the substrate;
removing the third shielding plate from the first surface of the substrate.
Optionally, the growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the first surface of the substrate in sequence along the extending direction of the first straight line includes:
forming a first growth suppression layer on the first surface of the substrate by using a photolithography technique, the first growth suppression layer being located on the active layer and the P-type semiconductor layer;
growing an N-type semiconductor layer on the first surface of the substrate;
removing the first growth-suppressing layer from the first surface of the substrate;
forming a second growth suppression layer on the first surface of the substrate by using a photolithography technique, the second growth suppression layer being located on the active layer and the arrangement region of the N-type semiconductor layer;
growing a P-type semiconductor layer on the first surface of the substrate;
removing the second growth-suppression layer from the first surface of the substrate;
forming a third growth suppression layer on the first surface of the substrate by using a photolithography technique, wherein the third growth suppression layer is positioned on the arrangement region of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of the substrate;
removing the third growth-suppression layer from the first surface of the substrate.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the first surface of the substrate along the direction parallel to the first surface of the substrate, so that stress and defects generated by lattice mismatch of sapphire and gallium nitride can be effectively prevented from continuously extending and expanding along the direction of epitaxial growth, the defect of stress in an epitaxial wafer is reduced, the crystal growth quality of epitaxial base crystals is improved, and composite luminescence of current carriers in the active layer is facilitated. Meanwhile, the active layer is positioned in the middle of the first surface of the substrate, and the influence of the warpage formed by epitaxy due to high temperature and the like on carrier recombination luminescence in the active layer can be improved. In summary, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially disposed on the first surface of the substrate along a direction parallel to the first surface of the substrate, so that the crystal quality of the epitaxial wafer can be effectively improved, and the epitaxial wafer is suitable for the application of the gallium nitride-based LED in a long wavelength band, especially in a green light band and above.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gan-based led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an active layer provided in an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a gallium nitride-based light emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of a gallium nitride-based light emitting diode epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the gan-based light emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, an active layer 30, and a P-type semiconductor layer 40, and the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially disposed on a first surface of the substrate 10 along an extending direction (indicated by an arrow a in fig. 1) of a first straight line parallel to the first surface of the substrate 10.
According to the embodiment of the invention, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the first surface of the substrate along the direction parallel to the first surface of the substrate, so that the stress and the defect generated by lattice mismatch of sapphire and gallium nitride can be effectively prevented from continuously extending and expanding along the direction of epitaxial growth, the defect of the stress in an epitaxial wafer is reduced, the crystal growth quality of epitaxial base crystals is improved, and the composite luminescence of current carriers in the active layer is facilitated. Meanwhile, the active layer is positioned in the middle of the first surface of the substrate, and the influence of the warpage formed by epitaxy due to high temperature and the like on carrier recombination luminescence in the active layer can be improved. In summary, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially disposed on the first surface of the substrate along a direction parallel to the first surface of the substrate, so that the crystal quality of the epitaxial wafer can be effectively improved, and the epitaxial wafer is suitable for the application of the gallium nitride-based LED in a long wavelength band, especially in a green light band and above.
Fig. 2 is a schematic structural diagram of an active layer according to an embodiment of the present invention. Referring to fig. 2, the active layer 30 may optionally include a plurality of quantum wells 31 and a plurality of quantum barriers 32, the plurality of quantum wells 31 and the plurality of quantum barriers 32 being alternately disposed on the first surface of the substrate 10 along an extending direction of the first straight line (indicated by an arrow a in the drawing).
The quantum wells and the quantum barriers are alternately arranged, carriers are limited in the quantum wells by the quantum barriers to carry out compound light emission, and the compound light emission efficiency of the active layer is high. And the plurality of quantum wells and the plurality of quantum barriers are correspondingly adjusted to be alternately arranged along the extending direction of the first straight line according to the arrangement positions of the N-type semiconductor layer and the P-type semiconductor layer corresponding to the active layer.
Preferably, the number of quantum wells 31 is the same as the number of quantum barriers 32, and the number of quantum barriers 32 may be 3 to 15, preferably 9.
If the number of the quantum wells and the quantum barriers is less than 3, the recombination luminous efficiency of the carriers may be affected due to the small number of the quantum wells and the quantum barriers; if the number of the quantum well and the quantum barrier is more than 15, the complexity of the manufacturing process may be increased due to the large number of the quantum well and the quantum barrier, and the production cost may be increased.
Specifically, as shown in fig. 2, the length a of each quantum barrier 32 in the extending direction of the first straight line may be 9nm to 20nm, preferably 15 nm.
If the length of the quantum barrier in the extending direction of the first straight line is less than 9nm, carriers can not be effectively limited in the quantum well for compound light emission due to the short length of the quantum barrier in the extending direction of the first straight line; if the length of the quantum well barrier in the direction of the first straight line is greater than 20nm, the carrier migration may be affected due to the longer length of the quantum barrier in the extending direction of the first straight line, eventually reducing the light emitting efficiency of the LED.
Specifically, as shown in fig. 2, the length b of each quantum well 31 in the extending direction of the first straight line may be 2nm to 4nm, preferably 3 nm.
If the length of the quantum well in the extending direction of the first straight line is less than 2nm, the quantum well may not provide enough space for the carriers to perform compound light emission due to the short length of the quantum well in the extending direction of the first straight line; if the length of the quantum well in the extending direction of the first straight line is greater than 4nm, the crystal quality of the active layer may be poor due to the longer length of the quantum barrier in the direction of the first straight line, eventually reducing the light emitting efficiency of the LED.
Alternatively, as shown in fig. 1, the length c of the N-type semiconductor layer 20 in the extending direction of the first straight line may be 0.02 μm to 2 μm, preferably 1 μm.
If the length of the N-type semiconductor layer in the extending direction of the first straight line is less than 0.02 μm, the number of electrons supplied from the N-type semiconductor layer may be small due to the short length of the N-type semiconductor layer in the extending direction of the first straight line, affecting the light emitting efficiency of the LED; if the length of the N-type semiconductor layer in the extending direction of the first straight line is greater than 2 μm, a waste of material may be caused due to the long length of the N-type semiconductor layer in the extending direction of the first straight line.
Alternatively, as shown in fig. 1, the length d of the P-type semiconductor layer 40 in the extending direction of the first straight line may be 0.02 μm to 2 μm, preferably 1 μm.
If the length of the P-type semiconductor layer in the extending direction of the first straight line is less than 0.02 μm, the number of holes provided by the P-type semiconductor layer may be small due to the short length of the P-type semiconductor layer in the extending direction of the first straight line, which affects the light emitting efficiency of the LED; if the length of the P-type semiconductor layer in the extending direction of the first straight line is greater than 2 μm, a waste of material may be caused due to the long length of the P-type semiconductor layer in the extending direction of the first straight line.
Alternatively, as shown in fig. 1, the lengths e of the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 in a direction perpendicular to the first surface of the substrate 10 may be equal. The N-type semiconductor layer and the active layer are equal in length in the direction perpendicular to the first surface of the substrate in the P-type semiconductor layer, and therefore comprehensive use efficiency of the N-type semiconductor layer and the active layer can be maximized.
Preferably, the lengths of the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 in a direction perpendicular to the first surface of the substrate 10 may be 0.02 μm to 2 μm.
If the lengths of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in a direction perpendicular to the first surface of the substrate are less than 0.02 μm, a light emitting area may be small due to the short lengths of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in the direction perpendicular to the first surface of the substrate, affecting the light emitting efficiency of the LED; if the lengths of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in a direction perpendicular to the first surface of the substrate are greater than 2 μm, there may be more internal loss of light due to the longer lengths of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer in the direction perpendicular to the first surface of the substrate.
Optionally, as shown in fig. 1, the gan-based led epitaxial wafer may further include a buffer layer 51, where the buffer layer 51 is disposed on the first surface of the substrate 10 to relieve stress and defects generated by lattice mismatch between the substrate material and the gan and provide nucleation centers for epitaxial growth of the gan material.
Accordingly, the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially disposed on the buffer layer 51 in an extending direction of the first straight line.
Specifically, gallium nitride may be used as the material of the buffer layer 51.
Further, the thickness of the buffer layer 51 may be 15nm to 35nm, preferably 25 nm.
Preferably, as shown in fig. 1, the gan-based led epitaxial wafer may further include an undoped gan layer 52, where the undoped gan layer 52 is disposed on the buffer layer 51 to further alleviate stress and defects caused by lattice mismatch between the substrate material and gan, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
Accordingly, the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially disposed on the undoped gallium nitride layer 52 in the extending direction of the first straight line.
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on the patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer in this embodiment.
Further, the thickness of the undoped gallium nitride layer 52 may be 1 μm to 5 μm, preferably 3 μm.
Optionally, as shown in fig. 1, the gan-based LED epitaxial wafer may further include an electron blocking layer 61, where the electron blocking layer 61 is disposed between the active layer 30 and the P-type semiconductor layer 40 to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the electron blocking layer 61 may be made of P-type doped aluminum gallium nitride (AlGaN) such as AlyGa1-yN，0.1＜y＜0.5。
Further, the thickness of the electron blocking layer 61 may be 50nm to 150nm, preferably 100 nm.
Preferably, as shown in fig. 1, the gan-based led epitaxial wafer may further include a low temperature P-type layer 62, where the low temperature P-type layer 62 is disposed between the active layer 30 and the electron blocking layer 61, so as to avoid indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the led.
Specifically, the material of the low temperature P-type layer 62 may be the same as the material of the P-type semiconductor layer 40. In the present embodiment, the material of the low temperature P-type layer 62 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 62 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 62 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the gan-based led epitaxial wafer may further include a P-type contact layer 70, where the P-type contact layer 70 is disposed on the P-type semiconductor layer 40 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the P-type contact layer 70 may be made of P-type doped indium gallium nitride.
Further, the thickness of the P-type contact layer 70 may be 5nm to 100nm, preferably 50 nm; the doping concentration of the P-type dopant in the P-type contact layer 70 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a method for manufacturing a gallium nitride-based light-emitting diode epitaxial wafer, which is suitable for manufacturing the gallium nitride-based light-emitting diode epitaxial wafer shown in figure 1. Fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention. Referring to fig. 3, the manufacturing method includes:
step 201: a substrate is provided.
Specifically, the step 201 may include:
controlling the temperature to be 1000-1200 ℃ (preferably 1100 ℃), and annealing the substrate for 1-10 minutes (preferably 5 minutes) in a hydrogen atmosphere;
the substrate is subjected to a nitridation process.
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: and growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence along the extension direction of the first straight line.
In an implementation manner of this embodiment, the step 202 may include:
arranging a first shielding plate on the first surface of the substrate, wherein the first shielding plate covers the arrangement region of the active layer and the P-type semiconductor layer;
growing an N-type semiconductor layer on a first surface of a substrate;
removing the first shielding plate from the first surface of the substrate;
arranging a second shielding plate on the first surface of the substrate, wherein the second shielding plate covers the arrangement region of the active layer and the N-type semiconductor layer;
growing a P-type semiconductor layer on a first surface of a substrate;
removing the second shielding plate from the first surface of the substrate;
arranging a third shielding plate on the first surface of the substrate, wherein the third shielding plate covers the arrangement regions of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of a substrate;
the third shielding plate is removed from the first surface of the substrate.
In the above implementation manner, the first shielding plate, the second shielding plate, and the third shielding plate are shielding plates having different installation areas. The shielding plate is formed of a non-substrate material, so that the semiconductor layer cannot grow on the shielding plate.
In another implementation manner of this embodiment, this step 202 may include:
forming a first growth inhibition layer on the first surface of the substrate by adopting a photoetching technology, wherein the first growth inhibition layer is positioned on the active layer and the arrangement region of the P-type semiconductor layer;
growing an N-type semiconductor layer on a first surface of a substrate;
removing the first growth-inhibiting layer from the first surface of the substrate;
forming a second growth inhibition layer on the first surface of the substrate by adopting a photoetching technology, wherein the second growth inhibition layer is positioned on the active layer and the arrangement region of the N-type semiconductor layer;
growing a P-type semiconductor layer on a first surface of a substrate;
removing the second growth-suppressing layer from the first surface of the substrate;
forming a third growth inhibition layer on the first surface of the substrate by adopting a photoetching technology, wherein the third growth inhibition layer is positioned on the arrangement regions of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of a substrate;
the third growth-inhibiting layer is removed from the first surface of the substrate.
In the above-described implementation, the first growth-suppression layer, the second growth-suppression layer, and the third growth-suppression layer are growth-suppression layers having different installation regions. The growth-inhibiting layer is formed using a material (e.g., silicon dioxide) on which the semiconductor material cannot be deposited, thereby inhibiting growth of the semiconductor layer.
When the active layer includes a plurality of quantum wells and a plurality of quantum barriers, the quantum wells and the quantum barriers may be formed using different materials, and thus, in a specific implementation, the quantum wells and the quantum barriers may be formed using different shielding plates or growth suppression layers.
Specifically, growing the N-type semiconductor layer on the first surface of the substrate may include:
an N-type semiconductor layer is grown on the first surface of the substrate at a controlled temperature of 850 to 1080 deg.C (preferably 960 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
Growing a P-type semiconductor layer on a first surface of a substrate may include:
the P-type semiconductor layer is grown on the first surface of the substrate at a controlled temperature of 850 to 1080 deg.c (preferably 960 deg.c) and a pressure of 100to 300torr (preferably 200 torr).
Growing an active layer on a first surface of a substrate may include:
growing an active layer on a first surface of a substrate; wherein the growth temperature of the quantum well is 720 ℃ to 829 ℃ (preferably 760 ℃), and the pressure is 100torr to 500torr (preferably 300 torr); the growth temperature of the quantum barrier is 850 to 959 deg.C (preferably 900 deg.C), and the pressure is 100to 500torr (preferably 300 torr).
Optionally, before step 202, the manufacturing method may further include:
a buffer layer is grown on a substrate.
Accordingly, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are grown on the buffer layer.
Specifically, growing a buffer layer on a substrate may include:
controlling the temperature to be 400-600 ℃ (preferably 500 ℃), and the pressure to be 400-600 torr (preferably 500torr), and growing a buffer layer on the substrate;
the buffer layer is subjected to in-situ annealing treatment for 5 to 10 minutes (preferably 8 minutes) at a controlled temperature of 1000 to 1200 c (preferably 1100 c) and a pressure of 400to 600torr (preferably 500 torr).
Preferably, after growing the buffer layer on the substrate, the manufacturing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 100torr to 500torr (preferably 300 torr).
Optionally, the manufacturing method may further include:
an electron blocking layer is formed between the active layer and the P-type semiconductor layer.
Specifically, the formation process of the electron blocking layer may be similar to the N-type semiconductor layer, the active layer and the P-type semiconductor layer, and is not described herein again. The difference is that the growth temperature is 850-1080 deg.C (preferably 950 deg.C) and the growth pressure is 200-500 torr (preferably 350torr) when the electron blocking layer is grown.
Preferably, the manufacturing method may further include:
a low temperature P-type layer is formed between the active layer and the electron blocking layer.
Specifically, the formation process of the low temperature P-type layer may be similar to that of the electron blocking layer, and is not described herein again. The difference is mainly that when the low-temperature P-type layer is grown, the growth temperature is 600 ℃ to 850 ℃ (preferably 750 ℃), and the growth pressure is 100torr to 600torr (preferably 300 torr).
Optionally, after step 202, the manufacturing method may further include:
and growing a P-type contact layer on the P-type semiconductor layer.
Specifically, growing the P-type contact layer on the P-type semiconductor layer may include:
the temperature is controlled to be 850 to 1050 ℃ (preferably 950 ℃), and the pressure is controlled to be 100to 300torr (preferably 200torr), and the P-type contact layer is grown on the P-type semiconductor layer.
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as an N-type dopant, and magnesium diclocide is used as a P-type dopant.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The GaN-based light emitting diode epitaxial wafer is characterized by comprising a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on a first surface of the substrate along the extension direction of a first straight line, and the first straight line is parallel to the first surface of the substrate.
2. The gan-based led epitaxial wafer of claim 1, wherein the active layer comprises a plurality of quantum wells and a plurality of quantum barriers, the plurality of quantum wells and the plurality of quantum barriers being alternately disposed on the first surface of the substrate along an extension direction of the first straight line.
3. The GaN-based LED epitaxial wafer as claimed in claim 2, wherein the number of the quantum wells is the same as the number of the quantum barriers, and the number of the quantum barriers is 3-15.
4. The GaN-based LED epitaxial wafer as claimed in any of claims 1-3, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer have equal lengths in a direction perpendicular to the first surface of the substrate.
5. The GaN-based LED epitaxial wafer of claim 4, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer have a length in a direction perpendicular to the first surface of the substrate of 0.02 μm to 2 μm.
6. The gallium nitride-based light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the length of the N-type semiconductor layer in the extending direction of the first straight line is 0.02 μm to 2 μm.
7. The gallium nitride-based light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the length of the P-type semiconductor layer in the extending direction of the first straight line is 0.02 μm to 2 μm.
8. A manufacturing method of a gallium nitride-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
and sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate along the extension direction of a first straight line, wherein the first straight line is parallel to the first surface of the substrate.
9. The method according to claim 8, wherein the growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence along the extending direction of the first straight line comprises:
arranging a first shielding plate on the first surface of the substrate, wherein the first shielding plate covers the arrangement region of the active layer and the P-type semiconductor layer;
growing an N-type semiconductor layer on the first surface of the substrate;
removing the first shielding plate from the first surface of the substrate;
arranging a third shielding plate on the first surface of the substrate, wherein the third shielding plate covers the arrangement regions of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of the substrate;
removing the third shielding plate from the first surface of the substrate;
arranging a second shielding plate on the first surface of the substrate, wherein the second shielding plate covers the arrangement region of the active layer and the N-type semiconductor layer;
growing a P-type semiconductor layer on the first surface of the substrate;
removing the second shielding plate from the first surface of the substrate.
10. The method according to claim 8, wherein the growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence along the extending direction of the first straight line comprises:
forming a first growth suppression layer on the first surface of the substrate by using a photolithography technique, the first growth suppression layer being located on the active layer and the P-type semiconductor layer;
growing an N-type semiconductor layer on the first surface of the substrate;
removing the first growth-suppressing layer from the first surface of the substrate;
forming a third growth suppression layer on the first surface of the substrate by using a photolithography technique, wherein the third growth suppression layer is positioned on the arrangement region of the N-type semiconductor layer and the P-type semiconductor layer;
growing an active layer on a first surface of the substrate;
removing the third growth-suppression layer from the first surface of the substrate;
forming a second growth suppression layer on the first surface of the substrate by using a photolithography technique, the second growth suppression layer being located on the active layer and the arrangement region of the N-type semiconductor layer;
growing a P-type semiconductor layer on the first surface of the substrate;
removing the second growth suppression layer from the first surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811035789.9A CN109273571B (en) | 2018-09-06 | 2018-09-06 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811035789.9A CN109273571B (en) | 2018-09-06 | 2018-09-06 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109273571A CN109273571A (en) | 2019-01-25 |
| CN109273571B true CN109273571B (en) | 2020-04-14 |
Family
ID=65187960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811035789.9A Active CN109273571B (en) | 2018-09-06 | 2018-09-06 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109273571B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112467003B (en) * | 2020-11-26 | 2021-11-23 | 华南师范大学 | Deep ultraviolet light-emitting device with P-type region growing in parallel in quantum well region and preparation method thereof |
| CN113540300B (en) * | 2021-05-27 | 2022-08-12 | 华灿光电（浙江）有限公司 | Preparation method of light-emitting diode epitaxial wafer for improving surface flatness |
| CN114141911B (en) * | 2021-11-10 | 2023-05-16 | 重庆康佳光电技术研究院有限公司 | Epitaxial structure, manufacturing method thereof and light-emitting device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1731587A (en) * | 2005-08-05 | 2006-02-08 | 西安电子科技大学 | Vertical type wide bandgap semiconductor device structure and making method |
| CN108123015A (en) * | 2017-12-20 | 2018-06-05 | 西安智盛锐芯半导体科技有限公司 | The device architecture of GaN transverse directions LED based on multiple quantum wells |
| CN108269890A (en) * | 2018-01-25 | 2018-07-10 | 扬州乾照光电有限公司 | A kind of LED chip and preparation method thereof |
-
2018
- 2018-09-06 CN CN201811035789.9A patent/CN109273571B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1731587A (en) * | 2005-08-05 | 2006-02-08 | 西安电子科技大学 | Vertical type wide bandgap semiconductor device structure and making method |
| CN108123015A (en) * | 2017-12-20 | 2018-06-05 | 西安智盛锐芯半导体科技有限公司 | The device architecture of GaN transverse directions LED based on multiple quantum wells |
| CN108269890A (en) * | 2018-01-25 | 2018-07-10 | 扬州乾照光电有限公司 | A kind of LED chip and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109273571A (en) | 2019-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109346576B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN110718612B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109786529B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN110112269B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109860358B (en) | Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof | |
| CN109860359B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109103303B (en) | Preparation method of light-emitting diode epitaxial wafer and light-emitting diode epitaxial wafer | |
| CN109065679B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN109346583B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109273571B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN108447952B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109346568B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109545918B (en) | Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof | |
| CN109671817B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109103312B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN107658374B (en) | Epitaxial wafer of light emitting diode and preparation method thereof | |
| CN112687773B (en) | Epitaxial wafer of ultraviolet light-emitting diode and preparation method thereof | |
| CN109473511B (en) | Gallium nitride-based light emitting diode epitaxial wafer and growth method thereof | |
| CN109686823B (en) | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN117199203A (en) | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode | |
| CN109473521B (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN109950375B (en) | Light emitting diode epitaxial wafer and growth method thereof | |
| CN109087977B (en) | Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof | |
| CN113571615B (en) | Light emitting diode epitaxial wafer for improving ohmic contact and manufacturing method thereof | |
| CN109411575B (en) | Light emitting diode epitaxial wafer and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |