CN109950375B - Light emitting diode epitaxial wafer and growth method thereof - Google Patents
Light emitting diode epitaxial wafer and growth method thereof Download PDFInfo
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Abstract
The invention discloses a light emitting diode epitaxial wafer and a growth method thereof, and belongs to the technical field of semiconductors. The epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer comprises a plurality of laminated structures which are sequentially laminated, and each laminated structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of laminated structures are all reduced layer by layer along the laminating direction of the plurality of laminated structures; in the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer. The invention can improve the luminous efficiency of the LED.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light emitting diode epitaxial wafer and a growth method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. As a novel efficient, environment-friendly and green solid-state illumination light source, LEDs are being rapidly and widely applied in the fields of traffic signal lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlight sources and the like. The core component of the LED is a chip, and improving the light emitting efficiency of the chip is a goal continuously pursued in the application process of the LED.
The chip comprises an epitaxial wafer and an electrode arranged on the epitaxial wafer. The conventional LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The substrate is used for providing an epitaxial growth surface, the buffer layer is used for providing a nucleation center of epitaxial growth, the N-type semiconductor layer is used for providing electrons of composite luminescence, the P-type semiconductor layer is used for providing holes of the composite luminescence, and the active layer is used for carrying out the composite luminescence of the electrons and the holes.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the N-type semiconductor layer is made of heavily silicon-doped gallium nitride. Silicon substitutes gallium to form a covalent bond with nitrogen to generate freely moving electrons, so that the number of electrons is in direct proportion to the doping concentration of silicon in the N-type semiconductor layer. The doping concentration of silicon in the N-type semiconductor layer is high, and a larger number of electrons can be provided. However, since the moving rate of electrons is fast, when the number of electrons injected into the active layer by the N-type semiconductor layer is too large, part of the electrons will cross the active layer and reach the P-type semiconductor layer to undergo non-radiative recombination with holes, consuming the holes in the P-type semiconductor layer, resulting in a decrease in the number of holes injected into the active layer by the P-type semiconductor layer, and reducing the light emitting efficiency of the LED.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode epitaxial wafer and a growth method thereof, which can solve the problem that the luminous efficiency of an LED in the prior art needs to be improved. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode epitaxial wafer, where the light emitting diode epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, where the buffer layer, the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the N-type semiconductor layer comprises a plurality of laminated structures which are sequentially laminated, and the laminated structures comprise a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of stacked structures are all reduced layer by layer along the stacking direction of the plurality of stacked structures; in the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer.
Optionally, in the same stacked structure, the doping concentration of silicon in the first sublayer is 1.5 to 2.5 times that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is 5 to 10 times that of silicon in the second sublayer.
Optionally, a reduction ratio of the doping concentration of silicon in the first sub-layer of the plurality of stacked structures, a reduction ratio of the doping concentration of silicon in the second sub-layer of the plurality of stacked structures, and a reduction ratio of the doping concentration of silicon in the third sub-layer of the plurality of stacked structures are equal.
Furthermore, in two adjacent first sublayers, the doping concentration of silicon in the first sublayer stacked first is 1.5-5 times that of silicon in the first sublayer stacked later.
Optionally, the thicknesses of the first sub-layer of the plurality of stacked structures, the second sub-layer of the plurality of stacked structures, and the third sub-layer of the plurality of stacked structures decrease layer by layer along the stacking direction of the plurality of stacked structures.
Further, the reduction ratio of the thickness of the first sub-layer of the plurality of stacked structures, the reduction ratio of the thickness of the second sub-layer of the plurality of stacked structures, and the reduction ratio of the thickness of the third sub-layer of the plurality of stacked structures are equal.
Furthermore, in two adjacent first sublayers, the thickness of the first sublayer stacked first is 1.5 to 6 times of the thickness of the first sublayer stacked later.
Optionally, in the same stacked structure, the thickness of the second sublayer is smaller than that of the first sublayer, and the thickness of the third sublayer is equal to that of the first sublayer.
Further, in the same laminated structure, the thickness of the first sublayer is 1.5 to 8 times that of the second sublayer.
In another aspect, an embodiment of the present invention provides a growth method of a light emitting diode epitaxial wafer, where the growth method includes:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the N-type semiconductor layer comprises a plurality of laminated structures which are sequentially laminated, and the laminated structures comprise a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of stacked structures are all reduced layer by layer along the stacking direction of the plurality of stacked structures; in the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by dividing the N-type semiconductor layer into a plurality of laminated structures, wherein each laminated structure comprises three gallium nitride layers with different silicon doping concentrations, the condition of continuous high-doped silicon in the N-type semiconductor layer is changed, and on one hand, the damage of the high-doped silicon to the integrity of crystal lattices can be reduced; on the other hand, under the condition of providing enough electrons for the active layer, the quantity of electrons injected into the active layer is reduced, the migration rate of the electrons is reduced, partial electrons are prevented from jumping into the P-type semiconductor layer to be subjected to non-radiative recombination with holes, and the luminous efficiency of the LED is improved.
The doping concentration of silicon in the middle gallium nitride layer is the lowest, so that the doping concentration of silicon in the laminated structure is concave, on one hand, the condition that the high-doped silicon gallium nitride layer grows for a long time can be effectively changed, namely, the growth time of the high-doped silicon gallium nitride layer is dispersed, the improvement of the integrity of crystal lattices is facilitated, and the influence of the composite luminescence of electrons and holes caused by the fact that stress and defects generated by the high-doped silicon extend to an active layer is reduced; on the other hand, current spreading can be facilitated. Meanwhile, for the high-doped silicon gallium nitride layers on the two sides of the low-doped silicon gallium nitride layer, the doping concentration of silicon in the gallium nitride layer far away from the active layer is greater than that of silicon in the gallium nitride layer close to the active layer, so that the quantity of electrons far away from the active layer area in the laminated structure is greater than that of electrons close to the active layer area, and the difference in quantity is favorable for the electrons to move towards the direction close to the active layer.
In addition, the doping concentration of silicon in the laminated structures is reduced layer by layer along the laminating direction of the laminated structures, on one hand, the doping concentration of silicon in the laminated structure far away from the active layer is greater than that of silicon in the laminated structure close to the active layer, so that the quantity of electrons in the area far away from the active layer is greater than that in the area close to the active layer, and the difference in quantity is beneficial to the movement of electrons towards the direction close to the active layer; on the other hand, the doping concentration of silicon in the laminated structure close to the active layer is lower and is matched with the crystal lattice of the active layer, the transverse expansion of current is better, partial electrons can be further prevented from jumping into the P-type semiconductor layer to be non-radiatively compounded with holes, and the luminous efficiency of the LED is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an N-type semiconductor layer provided in an embodiment of the invention;
fig. 3 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light-emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5, and the buffer layer 2, the N-type semiconductor layer 3, the active layer 4, and the P-type semiconductor layer 5 are sequentially stacked on the substrate 1.
Fig. 2 is a schematic structural diagram of an N-type semiconductor layer according to an embodiment of the invention. Referring to fig. 2, the N-type semiconductor layer 3 includes a plurality of stacked structures 30 sequentially stacked, and the stacked structure 30 includes a first sublayer 31, a second sublayer 32, and a third sublayer 33 sequentially stacked. The materials of the first sublayer 31, the second sublayer 32 and the third sublayer 33 are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer 31 of the plurality of stacked structures 30, the doping concentration of silicon in the second sublayer 32 of the plurality of stacked structures 30 and the doping concentration of silicon in the third sublayer 33 of the plurality of stacked structures 30 are all decreased layer by layer along the stacking direction of the plurality of stacked structures 30; that is, the doping concentration of silicon in the first sub-layer 31 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30, the doping concentration of silicon in the second sub-layer 32 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30, and the doping concentration of silicon in the third sub-layer 33 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30. In the same stack structure, the doping concentration of silicon in the first sublayer 31 is greater than the doping concentration of silicon in the third sublayer 33, and the doping concentration of silicon in the third sublayer 33 is greater than the doping concentration of silicon in the second sublayer 32.
According to the embodiment of the invention, the N-type semiconductor layer is divided into a plurality of laminated structures, each laminated structure comprises three gallium nitride layers with different silicon doping concentrations, so that the condition of continuous high-doped silicon in the N-type semiconductor layer is changed, and on one hand, the damage of the high-doped silicon to the integrity of crystal lattices can be reduced; on the other hand, under the condition of providing enough electrons for the active layer, the quantity of electrons injected into the active layer is reduced, the migration rate of the electrons is reduced, partial electrons are prevented from jumping into the P-type semiconductor layer to be subjected to non-radiative recombination with holes, and the luminous efficiency of the LED is improved.
The doping concentration of silicon in the middle gallium nitride layer is the lowest, so that the doping concentration of silicon in the laminated structure is concave, on one hand, the condition that the high-doped silicon gallium nitride layer grows for a long time can be effectively changed, namely, the growth time of the high-doped silicon gallium nitride layer is dispersed, the improvement of the integrity of crystal lattices is facilitated, and the influence of the composite luminescence of electrons and holes caused by the fact that stress and defects generated by the high-doped silicon extend to an active layer is reduced; on the other hand, current spreading can be facilitated. Meanwhile, for the high-doped silicon gallium nitride layers on the two sides of the low-doped silicon gallium nitride layer, the doping concentration of silicon in the gallium nitride layer far away from the active layer is greater than that of silicon in the gallium nitride layer close to the active layer, so that the quantity of electrons far away from the active layer area in the laminated structure is greater than that of electrons close to the active layer area, and the difference in quantity is favorable for the electrons to move towards the direction close to the active layer.
In addition, the doping concentration of silicon in the laminated structures is reduced layer by layer along the laminating direction of the laminated structures, on one hand, the doping concentration of silicon in the laminated structure far away from the active layer is greater than that of silicon in the laminated structure close to the active layer, so that the quantity of electrons in the area far away from the active layer is greater than that in the area close to the active layer, and the difference in quantity is beneficial to the movement of electrons towards the direction close to the active layer; on the other hand, the doping concentration of silicon in the laminated structure close to the active layer is lower and is matched with the crystal lattice of the active layer, the transverse expansion of current is better, partial electrons can be further prevented from jumping into the P-type semiconductor layer to be non-radiatively compounded with holes, and the luminous efficiency of the LED is improved.
Alternatively, in the same stacked structure 30, the doping concentration of silicon in the first sub-layer 31 may be 1.5 times to 2.5 times, for example, 2 times, that of silicon in the third sub-layer 33; the doping concentration of silicon in the third sub-layer 33 may be 5 times to 10 times, such as 6 times to 10 times, the doping concentration of silicon in the second sub-layer 32. The doping concentration of silicon in the first sublayer is slightly higher than that of silicon in the third sublayer, and meanwhile, the doping concentration of silicon in the third sublayer is far higher than that of silicon in the second sublayer, so that the doping concentration of silicon in the laminated structure is concave, and the transverse expansion of current can be effectively promoted; meanwhile, the doping concentration of silicon in the sub-layers on the two sides is slightly different, so that the quantity of electrons on the two sides is slightly different, and the electrons can be promoted to move towards the direction close to the active layer by using the quantity difference.
Alternatively, the reduction ratio of the doping concentration of silicon in the first sub-layer 31 of the plurality of stacked structures 30, the reduction ratio of the doping concentration of silicon in the second sub-layer 32 of the plurality of stacked structures 30, and the reduction ratio of the doping concentration of silicon in the third sub-layer 33 of the plurality of stacked structures 30 may be equal. The doping concentration of silicon in each sublayer is reduced by adopting the same proportion, and the difference of the doping concentration of silicon among the sublayers in the same laminated structure is constant, thereby being beneficial to the stability of the crystal structure.
Further, in two adjacent first sub-layers 31, the doping concentration of silicon in the first sub-layer 31 stacked first may be 1.5 times to 5 times, for example, 1.5 times to 4 times, the doping concentration of silicon in the first sub-layer 31 stacked later. If the doping concentration of silicon in the first sublayer stacked first is less than 1.5 times of the doping concentration of silicon in the first sublayer stacked later, it may be impossible to effectively avoid that part of electrons jump into the P-type semiconductor layer to be non-radiatively recombined with holes due to small change of the doping concentration of silicon in the first sublayer, and the luminous efficiency of the LED is finally affected; if the doping concentration of silicon in the first sublayer stacked first is greater than 5 times of the doping concentration of silicon in the first sublayer stacked later, the crystal quality may be poor due to the large variation of the doping concentration of silicon in the first sublayer, and the light emitting efficiency of the LED may be affected finally.
Correspondingly, in two adjacent second sub-layers 32, the doping concentration of silicon in the first stacked second sub-layer 32 may be 1.5 times to 5 times, for example, 1.5 times to 4 times, the doping concentration of silicon in the second sub-layer 32 stacked later; in two adjacent third sub-layers 33, the doping concentration of silicon in the first stacked third sub-layer 33 may be 1.5 times to 5 times, for example, 1.5 times to 4 times, the doping concentration of silicon in the second stacked third sub-layer 33.
Exemplarily, the doping concentration of silicon in the first sub-layer 31 may be 5 × 1018/cm3～5*1019/cm3E.g. 5 x 1018/cm3～3*1019/cm3(ii) a The doping concentration of silicon in the second sub-layer 32 may be 5 x 1017/cm3～2.5*1018/cm3E.g. 6 x 1017/cm3～2.5*1018/cm3(ii) a The doping concentration of silicon in the third sub-layer 33 may be 2.5 x 1018/cm3～2.5*1019/cm3E.g. 2.5 x 1018/cm3～1*1019/cm3And the realization effect is good.
Alternatively, the thickness of the first sub-layer 31 of the plurality of stacked structures 30, the thickness of the second sub-layer 32 of the plurality of stacked structures 30, and the thickness of the third sub-layer 33 of the plurality of stacked structures 30 may each decrease layer by layer along the stacking direction of the plurality of stacked structures 30; that is, the thickness of the first sub-layer 31 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30, the thickness of the second sub-layer 32 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30, and the thickness of the third sub-layer 33 of the plurality of stacked structures 30 decreases layer by layer along the stacking direction of the plurality of stacked structures 30. The thickness of each sublayer and the doping concentration of silicon in each sublayer are reduced synchronously, the two sublayers are matched with each other, the doping concentration of silicon in the laminated structure far away from the active layer is higher, and meanwhile, the larger thickness is adopted, so that enough electrons can be provided for the active layer; the doping concentration of silicon in the laminated structure close to the active layer is low, and meanwhile, the thickness is small, so that electron injection into the active layer is facilitated.
Further, the reduction ratio of the thicknesses of the first sub-layers 31 of the plurality of stacked structures 30, the reduction ratio of the thicknesses of the second sub-layers 32 of the plurality of stacked structures 30, and the reduction ratio of the thicknesses of the third sub-layers 33 of the plurality of stacked structures 30 may be equal. The thicknesses of the sub-layers are reduced by adopting the same proportion, and the difference of the thicknesses of the sub-layers in the same laminated structure is constant, so that the stability of a crystal structure is facilitated.
Further, of the two adjacent first sub-layers 31, the thickness of the first sub-layer 31 stacked first is 1.5 to 6 times, such as 1.5 to 4 times, the thickness of the first sub-layer 31 stacked later. If the thickness of the first sub-layer stacked first is less than 1.5 times of the thickness of the first sub-layer stacked later, the variation of the silicon doping concentration in the first sub-layer cannot be matched due to small variation of the thickness of the first sub-layer, so that the quantity of electrons injected into the active layer is too small or too much; if the thickness of the first sub-layer stacked first is greater than 6 times the thickness of the first sub-layer stacked later, the crystal quality may be poor due to too large variation in the thickness of the first sub-layer, eventually affecting the light emitting efficiency of the LED.
Correspondingly, in two adjacent second sub-layers 32, the thickness of the first stacked second sub-layer 32 is 1.5 to 6 times, for example, 1.5 to 4 times, the thickness of the second sub-layer 32 stacked later; of the adjacent two third sub-layers 33, the thickness of the first stacked third sub-layer 33 is 1.5 to 6 times, for example, 1.5 to 4 times, the thickness of the second stacked third sub-layer 33.
Optionally, in the same stack structure 30, the thickness of the second sub-layer 32 may be smaller than the thickness of the first sub-layer 31, and the thickness of the third sub-layer 33 may be equal to the thickness of the first sub-layer 31, so as to avoid that the second sub-layer is too thick to cause a low silicon doping concentration of the entire N-type semiconductor layer, thereby affecting current spreading.
Further, in the same laminate structure 30, the thickness of the first sub-layer 31 may be 1.5 times to 8 times, such as 3 times to 8 times, the thickness of the second sub-layer 32. If the thickness of the first sub-layer is less than 1.5 times of the thickness of the second sub-layer, the silicon doping concentration of the whole N-type semiconductor layer may be low due to the fact that the second sub-layer is too thick, and current spreading is further affected; if the thickness of the first sub-layer is greater than 8 times the thickness of the second sub-layer, the second sub-layer may be too thin to effectively protect the integrity of the crystal lattice.
Illustratively, the thickness of the first sub-layer 31 may be 100nm to 500nm, such as 100nm to 400 nm; the thickness of the second sub-layer 32 may be 40nm to 100nm, such as 40nm to 80 nm; the thickness of the third sub-layer 33 may be 100nm to 500nm, such as 100nm to 400nm, which is good in implementation effect.
Alternatively, the number of stacked structures 30 may be 5 to 20, such as 6 to 15. If the number of the stacked structures is less than 5, the number of electrons injected into the active layer may not be effectively adjusted due to the small number of the stacked structures; if the number of the stacked structures is more than 20, the growth process may be complicated, the growth cost may be high due to the large number of the stacked structures, and the electron injection into the active layer may be affected.
Alternatively, the material of the substrate 1 may be sapphire (alumina is a main material), for example, with a crystal orientation of [0001 ]]The sapphire of (4). The buffer layer 2 may be made of undoped gallium nitride or aluminum nitride. The active layer 4 may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the quantum well material may be indium gallium nitride (InGaN), such as InxGa1-xN, 0 < x < 1, and gallium nitride can be used as the material of the quantum barrier. The P-type semiconductor layer 5 may be made of P-type doped (e.g., mg) gan.
Further, the thickness of the buffer layer 2 may be 15nm to 30nm, preferably 25 nm. The thickness of the quantum well can be 2 nm-3 nm, preferably 2.5 nm; the thickness of the quantum barrier can be 8nm to 11nm, preferably 9.5 nm; the number of the quantum wells is the same as that of the quantum barriers, and the number of the quantum barriers can be 11-13, preferably 12; the thickness of the active layer 4 may be 130nm to 160nm, preferably 145 nm. The thickness of the P-type semiconductor layer 5 may be 50nm to 80nm, preferably 65 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 5 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 6, where the undoped gallium nitride layer 6 is disposed between the buffer layer 2 and the N-type semiconductor layer 3 to relieve stress and defects caused by lattice mismatch between the substrate material and the gallium nitride, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
In a specific implementation, buffer layer 2 is a thin layer of gallium nitride that is first grown at low temperature on a patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer 6 in this embodiment.
Further, the thickness of the undoped gallium nitride layer 6 may be 2 μm to 3.5 μm, preferably 2.75 μm.
Optionally, the light emitting diode epitaxial wafer may further include a stress release layer 7, where the stress release layer 7 is disposed between the N-type semiconductor layer 3 and the active layer 4 to release stress generated by lattice mismatch between sapphire and gallium nitride, so as to improve crystal quality of the active layer, facilitate radiation recombination of electrons and holes in the active layer for light emission, improve internal quantum efficiency of the LED, and further improve light emission efficiency of the LED.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an electron blocking layer 81, and the electron blocking layer 81 is disposed between the active layer 4 and the P-type semiconductor layer 5 to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the electron blocking layer 81 may be made of P-type doped aluminum gallium nitride (AlGaN) such as AlyGa1-yN，0.15＜y＜0.25。
Further, the thickness of the electron blocking layer 81 may be 30nm to 50nm, preferably 40 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a low temperature P-type layer 82, and the low temperature P-type layer 82 is disposed between the active layer 4 and the electron blocking layer 81, so as to prevent indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the light emitting diode.
Specifically, the material of the low temperature P-type layer 82 may be P-type doped gallium nitride.
Further, the thickness of the low-temperature P-type layer 82 may be 10nm to 50nm, preferably 30 nm; doping concentration of P-type dopant in low temperature P-type layer 82The degree may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a contact layer 9, and the contact layer 9 is disposed on the P-type semiconductor layer 5 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 9 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 9 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 9 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a method for growing a light-emitting diode epitaxial wafer, which is suitable for growing the light-emitting diode epitaxial wafer shown in figure 1. Fig. 3 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 3, the growing method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the substrate is annealed at a temperature of 1000 to 1100 deg.C (preferably 1050 deg.C) and a pressure of 200to 500torr (preferably 350torr) in a hydrogen atmosphere for 5 to 6 minutes (preferably 5.5 minutes).
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In this embodiment, the N-type semiconductor layer includes a plurality of stacked structures stacked in sequence, and the stacked structure includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence. The materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of stacked structures are all reduced layer by layer along the stacking direction of the plurality of stacked structures. In the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer.
Alternatively, in the same stacked structure, the growth conditions of the first sublayer, the second sublayer and the third sublayer may be the same. Further, the growth conditions of the respective stacked structures may also be the same for easy implementation. The growth conditions may include, among others, growth temperature and growth pressure.
Optionally, this step 202 may include:
firstly, controlling the temperature to be 530-560 ℃ (preferably 545 ℃) and the pressure to be 200-500 torr (preferably 350torr), and growing a buffer layer on a substrate;
secondly, controlling the temperature to be 1000-1100 ℃ (preferably 1050 ℃) and the pressure to be 200-300 torr (preferably 250torr), and growing an N-type semiconductor layer on the buffer layer;
thirdly, growing an active layer on the N-type semiconductor layer; wherein, the growth temperature of the quantum well is 760 ℃ to 780 ℃ (preferably 770 ℃), and the pressure is 200 torr; the growth temperature of the quantum barrier is 860 ℃ -890 ℃ (preferably 875 ℃), and the pressure is 200 torr;
and fourthly, controlling the temperature to be 940-980 ℃ (preferably 960 ℃) and the pressure to be 200-600 torr (preferably 400torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the second step, the growing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 200torr to 600torr (preferably 400 torr).
Optionally, before the third step, the growing method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Accordingly, an active layer is grown on the stress relieving layer.
Optionally, before the fourth step, the growing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
the electron blocking layer is grown on the active layer at a controlled temperature of 930 deg.C to 970 deg.C (preferably 950 deg.C) and a pressure of 100 torr.
Preferably, before growing the electron blocking layer on the active layer, the growth method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fourth step, the growing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device, such as Veeco K465i MOCVD or Veeco C4 MOCVD. During implementation, hydrogen or nitrogen or a mixed gas of hydrogen and nitrogen is used as a carrier gas, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, and magnesium diclocide is used as a magnesium source.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A light emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate; the N-type semiconductor layer comprises a plurality of laminated structures which are sequentially laminated from the buffer layer, and the laminated structures comprise a first sublayer, a second sublayer and a third sublayer which are sequentially laminated from the buffer layer; the materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of stacked structures are all reduced layer by layer along the stacking direction of the plurality of stacked structures; in the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer.
2. The light-emitting diode epitaxial wafer according to claim 1, wherein in the same stacked structure, the doping concentration of silicon in the first sub-layer is 1.5 times to 2.5 times that of silicon in the third sub-layer, and the doping concentration of silicon in the third sub-layer is 5 times to 10 times that of silicon in the second sub-layer.
3. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein a reduction ratio of the doping concentration of silicon in a first sublayer of the plurality of stacked structures, a reduction ratio of the doping concentration of silicon in a second sublayer of the plurality of stacked structures, and a reduction ratio of the doping concentration of silicon in a third sublayer of the plurality of stacked structures are equal.
4. The light-emitting diode epitaxial wafer according to claim 3, wherein in two adjacent first sub-layers, the doping concentration of silicon in the first sub-layer stacked first is 1.5-5 times that of silicon in the first sub-layer stacked later.
5. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein the thickness of the first sub-layer of the plurality of stacked structures, the thickness of the second sub-layer of the plurality of stacked structures, and the thickness of the third sub-layer of the plurality of stacked structures decrease layer by layer along the stacking direction of the plurality of stacked structures.
6. The light-emitting diode epitaxial wafer according to claim 5, wherein the reduction ratio of the thickness of the first sub-layer of the plurality of stacked structures, the reduction ratio of the thickness of the second sub-layer of the plurality of stacked structures, and the reduction ratio of the thickness of the third sub-layer of the plurality of stacked structures are equal.
7. The light-emitting diode epitaxial wafer according to claim 6, wherein the thickness of the first sub-layer stacked first in two adjacent first sub-layers is 1.5 to 6 times the thickness of the first sub-layer stacked later.
8. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein in the same laminated structure, the thickness of the second sub-layer is smaller than that of the first sub-layer, and the thickness of the third sub-layer is equal to that of the first sub-layer.
9. The light-emitting diode epitaxial wafer according to claim 8, wherein in the same laminated structure, the thickness of the first sub-layer is 1.5 times to 8 times that of the second sub-layer.
10. A growth method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the N-type semiconductor layer comprises a plurality of laminated structures which are sequentially laminated from the buffer layer, and the laminated structures comprise a first sublayer, a second sublayer and a third sublayer which are sequentially laminated from the buffer layer; the materials of the first sublayer, the second sublayer and the third sublayer are all silicon-doped gallium nitride, and the doping concentration of silicon in the first sublayer, the doping concentration of silicon in the second sublayer and the doping concentration of silicon in the third sublayer of the plurality of stacked structures are all reduced layer by layer along the stacking direction of the plurality of stacked structures; in the same laminated structure, the doping concentration of silicon in the first sublayer is greater than that of silicon in the third sublayer, and the doping concentration of silicon in the third sublayer is greater than that of silicon in the second sublayer.
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