CN109671817B - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents
Light emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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Abstract
The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductors. The epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the active layer comprises a plurality of composite structures, and each composite structure comprises a well layer and a barrier layer; the well layers closest to the P-type semiconductor layer are first well layers, and the first well layers comprise a first sub-layer, a second sub-layer and a third sub-layer; the well layer other than the first well layer is a second well layer including a fourth sublayer, a fifth sublayer and a sixth sublayer; in is adopted as the material of the second sub-layer and the material of the fifth sub-layerxGa1‑xN, the material of the first sub-layer and the material of the third sub-layer are both AlaInbGa1‑a‑bN, adopting Al as the material of the fourth sublayer and the material of the sixth sublayercIndGa1‑c‑dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d). The invention can improve the luminous efficiency of the epitaxial wafer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. The LED has the advantages of high efficiency, long service life, small volume, low power consumption and the like, and can be applied to the fields of indoor and outdoor white light illumination, screen display, backlight sources and the like. In the development of the LED industry, gallium nitride (GaN) -based materials are a typical representative of group V-III compound semiconductors, and improving the photoelectric properties of GaN-based LEDs has become a key to the semiconductor lighting industry.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional GaN-based LED epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The substrate is used for providing a growth surface for epitaxial materials, the N-type semiconductor layer is used for providing electrons for carrying out recombination luminescence, the P-type semiconductor layer is used for providing holes for carrying out recombination luminescence, and the active layer is used for carrying out radiation recombination luminescence of the electrons and the holes.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the active layer comprises a plurality of well layers and a plurality of barrier layers, the well layers and the barrier layers are alternately stacked, and electrons and holes injected into the active layer are limited in the well layers by the barrier layers to carry out compound light emission. Generally, the well layer is made of indium gallium nitride (InGaN) with high indium composition, and the barrier layer is made of gallium nitride (GaN). Since the lattice constant of gallium nitride is 3.181 and the lattice constant of indium nitride is 3.538, a large lattice mismatch exists between the well layer and the barrier layer, and the recombination efficiency of electrons and holes in space is affected by stress generated by the lattice mismatch, resulting in low light emitting efficiency of the LED.
Disclosure of Invention
The embodiment of the invention provides a light emitting diode epitaxial wafer and a preparation method thereof, which can solve the problem of low light emitting efficiency of an LED (light emitting diode) caused by larger lattice mismatch between a well layer and a barrier layer in the prior art. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode epitaxial wafer, where the light emitting diode epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, where the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the active layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a well layer and a barrier layer laminated on the well layer; the well layers closest to the P-type semiconductor layer in the active layer are first well layers, and each first well layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked; the well layer except the first well layer in the active layer is a second well layer which comprises a fourth sub-layer, a fifth sub-layer and a sixth sub-layer which are sequentially laminated; material of the second sub-layerAnd the material of the fifth sublayer adopts InxGa1-xN, the material of the first sublayer and the material of the third sublayer are both AlaInbGa1-a-bN, the material of the fourth sublayer and the material of the sixth sublayer are both AlcIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d).
Alternatively, (a/b) > (4/9).
Optionally, the thickness of the first sub-layer is smaller than the thickness of the second sub-layer, and the thickness of the second sub-layer is larger than the thickness of the third sub-layer; the thickness of the fourth sublayer is smaller than that of the fifth sublayer, and the thickness of the fifth sublayer is larger than that of the sixth sublayer.
Preferably, the thickness of the second sub-layer is 5 to 10 times that of the first sub-layer, and the thickness of the second sub-layer is 5 to 10 times that of the third sub-layer; the thickness of the fifth sublayer is 5-10 times that of the fourth sublayer, and the thickness of the fifth sublayer is 5-10 times that of the sixth sublayer.
More preferably, the thickness of the second sublayer is greater than the thickness of the fifth sublayer; the thickness of the first sublayer, the thickness of the third sublayer, the thickness of the fourth sublayer and the thickness of the sixth sublayer are equal.
Optionally, the number of the first well layers is 1/5-1/2 of the total number of the well layers in the active layer.
Preferably, the number of the first well layers is 1 to 5.
More preferably, the number of the second well layers is 4 to 8.
On the other hand, the embodiment of the invention provides a preparation method of a light emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
wherein the active layer comprises a plurality of composite structures stacked in sequenceEach of the composite structures includes a well layer and a barrier layer laminated on the well layer; the well layers closest to the P-type semiconductor layer in the active layer are first well layers, and each first well layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked; the well layer except the first well layer in the active layer is a second well layer which comprises a fourth sub-layer, a fifth sub-layer and a sixth sub-layer which are sequentially laminated; the material of the second sub-layer and the material of the fifth sub-layer both adopt InxGa1-xN, the material of the first sublayer and the material of the third sublayer are both AlaInbGa1-a-bN, the material of the fourth sublayer and the material of the sixth sublayer are both AlcIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d).
Optionally, the growth temperature of the second sublayer and the growth temperature of the fifth sublayer are T1, the growth temperature of the first sublayer and the growth temperature of the third sublayer are T2, the growth temperature of the fourth sublayer and the growth temperature of the sixth sublayer are T3, the growth temperature of the barrier layer is T4, and T1 ≦ T2 ═ T3 < T4.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
through setting up the AlInGaN layer In the both sides on InGaN layer, the buffer layer between InGaN layer and the barrier layer can be regarded as to the AlInGaN layer, through the content of adjusting Al component and the content of In component, can effectively adjust band gap width and the lattice match degree between InGaN layer and the barrier layer, alleviates the lattice mismatch between well layer and the barrier layer, reduces the polarity mismatch, improves the radiation recombination efficiency In electron and hole, finally improves LED's luminous efficacy. Meanwhile, the energy band height of the AlInGaN layer is higher than that of the InGaN layer, electrons and holes can be better limited in the InGaN layer to be subjected to radiation recombination, the radiation recombination efficiency of the electrons and the holes is further improved, and the luminous efficiency of the LED is finally improved. The Al component content in the AlInGaN layer close to the N-type semiconductor layer is higher than that in the AlInGaN layer close to the P-type semiconductor layer, so that the barrier effect on electrons can be improved, and the electron overflow is reduced; on the other hand, electrons and holes can be concentrated in a plurality of well layers closest to the P-type semiconductor for radiative recombination, so that the internal quantum efficiency of the epitaxial wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an active layer provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first well layer provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second well layer provided in an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light-emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, an active layer 30, and a P-type semiconductor layer 40, and the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially stacked on the substrate 10.
Fig. 2 is a schematic structural diagram of an active layer according to an embodiment of the present invention. Referring to fig. 2, in the present embodiment, the active layer 30 includes a plurality of composite structures 31 sequentially stacked, and each composite structure 31 includes a well layer 32 and a barrier layer 33 stacked on the well layer 32. Several well layers 32 of the active layer 30 closest to the P-type semiconductor layer are first well layers. For example, in fig. 2, the two well layers 32 closest to the P-type semiconductor layer are first well layers, and the three well layers closest to the N-type semiconductor layer are not first well layers (the first well layers and the non-first well layers are shown in different figures).
Fig. 3 is a schematic structural diagram of a first well layer according to an embodiment of the present invention. Referring to fig. 3, the first well layer includes a first sublayer 32a, a second sublayer 32b, and a third sublayer 32c, which are sequentially stacked. The well layer 32 other than the first well layer in the active layer is a second well layer. Fig. 4 is a schematic structural diagram of a second well layer according to an embodiment of the present invention. Referring to fig. 4, the second well layer 32 includes a fourth sublayer 32d, a fifth sublayer 32e, and a sixth sublayer 32f, which are sequentially stacked. In is used for the material of the second sub-layer 32b and the material of the fifth sub-layer 32exGa1-xN, Al is adopted as the material of the first sub-layer 32a and the material of the third sub-layer 32caInbGa1-a-bN, Al is adopted as the material of the fourth sublayer 32d and the material of the sixth sublayer 32fcIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d).
According to the embodiment of the invention, the AlInGaN layers are arranged on the two sides of the InGaN layer and can be used as buffer layers between the InGaN layer and the barrier layer, the band gap width and the lattice matching degree between the InGaN layer and the barrier layer can be effectively adjusted by adjusting the content of the Al component and the content of the In component, the lattice mismatch between the well layer and the barrier layer is relieved, the polarity mismatch is reduced, the radiation recombination efficiency of electrons and holes is improved, and the luminous efficiency of the LED is finally improved. Meanwhile, the energy band height of the AlInGaN layer is higher than that of the InGaN layer, electrons and holes can be better limited in the InGaN layer to be subjected to radiation recombination, the radiation recombination efficiency of the electrons and the holes is further improved, and the luminous efficiency of the LED is finally improved. The Al component content in the AlInGaN layer close to the N-type semiconductor layer is higher than that in the AlInGaN layer close to the P-type semiconductor layer, so that the barrier effect on electrons can be improved, and the electron overflow is reduced; on the other hand, electrons and holes can be concentrated in a plurality of well layers closest to the P-type semiconductor for radiative recombination, so that the internal quantum efficiency of the epitaxial wafer is improved.
Alternatively, 0.02 ≦ x ≦ 0.06, such as x ≦ 0.03. Because the AlInGaN layer can effectively adjust the lattice matching degree between the InGaN layer and the barrier layer, the content of an In component In the InGaN layer can be improved, the radiation recombination efficiency of carriers is improved, and the photoelectric performance of the epitaxial wafer is further improved.
Alternatively, (a/b) > (4/9), such as (a/b) ═ 0.6, and (c/d) ═ 0.7. The potential barrier of the AlInGaN layer is higher than that of the barrier layer, and therefore electrons and holes are limited in the InGaN layer to carry out composite luminescence.
Alternatively, the thickness of the first sub-layer 32a may be less than the thickness of the second sub-layer 32b, and the thickness of the second sub-layer 32b may be greater than the thickness of the third sub-layer 32 c; the thickness of the fourth sub-layer 32d may be less than the thickness of the fifth sub-layer 32e, and the thickness of the fifth sub-layer 32e may be greater than the thickness of the sixth sub-layer 32 f. The InGaN layer is thickest, so that the radiation recombination probability of carriers is favorably improved, and the photoelectric performance of the epitaxial wafer is further improved.
Preferably, the thickness of the second sub-layer 32b may be 5 to 10 times, such as 30 times, the thickness of the first sub-layer 32 a; the thickness of the second sub-layer 32b may be 5 to 10 times, such as 8 times, the thickness of the third sub-layer 32 c. The thickness of the fifth sublayer 32e may be 5 to 10 times, such as 8 times, the thickness of the fourth sublayer 32 d; the thickness of the fifth sublayer 32e may be 5 to 10 times, such as 8 times, the thickness of the sixth sublayer 32 f. The InGaN layer is effectively utilized to improve the radiation recombination efficiency of carriers, and meanwhile, the lattice mismatch between the InGaN layer and the barrier layer is reduced as much as possible.
More preferably, the thickness of the second sub-layer 32b may be greater than the thickness of the fifth sub-layer 32e, and the thickness of the first sub-layer 32a, the thickness of the third sub-layer 32c, the thickness of the fourth sub-layer 32d, and the thickness of the sixth sub-layer 32f may be equal. The InGaN layer close to the P-type semiconductor layer is thick, more holes and electrons can be concentrated on the well layers closest to the P-type semiconductor layer for radiation recombination, the overall radiation recombination efficiency of the active layer is improved, the internal quantum efficiency of the epitaxial wafer is further improved, and the light emitting efficiency of the LED is finally improved.
In particular, the thickness of the first sub-layer 32a may be 0.3nm to 0.5nm, such as 0.4 nm; the thickness of the second sub-layer 32b may be 3nm to 4nm, such as 3.5 nm; the thickness of the third sublayer 32c may be between 0.3nm and 0.5nm, such as 0.4 nm. The thickness of the fourth sublayer 32d may be 0.3nm to 0.5nm, such as 0.4 nm; the thickness of the fifth sublayer 32e may be 2.5nm to 3.5nm, such as 3 nm; the thickness of the sixth sublayer 32f may be in the range of 0.3nm to 0.5nm, such as 0.4 nm.
Optionally, the number of the first well layers can be 1/5-1/2 of the total number of the well layers in the active layer, such as 1/4, which is beneficial to the radiative recombination of carriers concentrated in the well layers closest to the P-type semiconductor layer, and the radiative recombination efficiency of the whole active layer is improved.
Preferably, the number of the first well layers can be 1 to 5, such as 4, which is good in practical application.
Preferably, the number of the second well layers can be 4 to 8, such as 5, which is good in practical application effect.
Alternatively, the barrier layer 33 may be made of undoped gan or N-type doped gan (e.g., si or ge). When the barrier layer is made of N-type doped gallium nitride, the electron migration is facilitated, and the radiation recombination efficiency of the active layer is improved.
Preferably, the barrier layer 33 adjacent to the first well layer may be made of undoped gallium nitride, and the barrier layer 33 adjacent to the second well layer may be made of N-type doped gallium nitride, which is beneficial to the radiative recombination of the electrons and the holes concentrated in the several well layers closest to the P-type semiconductor layer, and improves the overall radiative recombination efficiency of the active layer.
Further, when the barrier layer 33 is made of N-type doped gan, the doping concentration of the N-type dopant in the barrier layer 33 may be 1017/cm3～1017/cm3E.g. 1018/cm3. The mobility of electrons can be improved, and the crystal structure of the active layer is not influenced.
Specifically, the number of the composite structures 31 may be 5 to 13, which may satisfy the recombination requirement of the carriers.
Specifically, the material of the substrate 10 may be sapphire (aluminum oxide is a main material), silicon, or silicon carbide. The material of the N-type semiconductor layer 20 may be N-type doped (e.g., silicon or germanium) gan. The P-type semiconductor layer 40 may be P-type doped (e.g., mg) gan.
Further, the thickness of the N-type semiconductor layer 20 may be 1 to 5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 20 may be 1018cm-3～9*1019cm-3Preferably 1019cm-3. The thickness of the P-type semiconductor layer 40 may be 100nm to 300nm, preferably 200 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 40 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a buffer layer 51, where the buffer layer 51 is disposed between the substrate 10 and the N-type semiconductor layer 20 to relieve stress and defects generated by lattice mismatch between the substrate material and the gallium nitride and provide nucleation centers for epitaxial growth of the gallium nitride material.
Specifically, the material of the buffer layer 51 may be gallium nitride or aluminum nitride.
Further, the thickness of the buffer layer 51 may be 15nm to 35nm, preferably 25 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 52, where the undoped gallium nitride layer 52 is disposed between the buffer layer 51 and the N-type semiconductor layer 20 to further alleviate stress and defects generated by lattice mismatch between the substrate material and the gallium nitride, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on the patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer in this embodiment.
Further, the thickness of the undoped gallium nitride layer 52 may be 1 μm to 3 μm, preferably 2 μm.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a stress release layer 60, where the stress release layer 60 is disposed between the N-type semiconductor layer 20 and the active layer 30 to release stress generated by lattice mismatch between sapphire and gallium nitride, so as to improve crystal quality of the active layer, facilitate radiation recombination of electrons and holes in the active layer for light emission, improve internal quantum efficiency of the LED, and further improve light emission efficiency of the LED.
Specifically, the stress release layer 60 may be a gallium indium aluminum nitride (AlInGaN) layer, which can effectively release the stress generated by lattice mismatch between sapphire and gallium nitride, improve the crystal quality of the epitaxial wafer, and improve the light emitting efficiency of the LED.
Further, the thickness of the stress relaxation layer 60 may be 50nm to 500nm, preferably 300 nm.
Optionally, as shown in fig. 1, the gan-based LED epitaxial wafer may further include an electron blocking layer 71, where the electron blocking layer 71 is disposed between the active layer 30 and the P-type semiconductor layer 40 to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the electron blocking layer 71 may be made of P-type doped aluminum gallium nitride, such as AlyGa1-yN， 0.1＜y＜0.5。
Further, the thickness of the electron blocking layer 71 may be 50nm to 150nm, preferably 100 nm.
Preferably, as shown in fig. 1, the gan-based led epitaxial wafer may further include a low-temperature P-type layer 72, where the low-temperature P-type layer 72 is disposed between the active layer 30 and the electron blocking layer 71, so as to avoid indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the led.
Specifically, the material of the low temperature P-type layer 72 may be the same as the material of the P-type semiconductor layer 40. In the present embodiment, the material of the low temperature P-type layer 72 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 72 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 72 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a contact layer 80, and the contact layer 80 is disposed on the P-type semiconductor layer 40 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 80 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 80 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 80 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a preparation method of a light-emitting diode epitaxial wafer, which is suitable for preparing the light-emitting diode epitaxial wafer shown in figure 1. Fig. 5 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 5, the preparation method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the surface of the substrate is cleaned.
Specifically, cleaning the surface of the substrate may include:
and controlling the temperature to be 1110 ℃, and annealing the substrate in a hydrogen atmosphere for 8-10 minutes.
Step 202: an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In the present embodiment, the active layer includes a plurality of composite structures stacked in sequence, each of the composite structures including a well layer and a barrier layer stacked on the well layer; the ones of the well layers closest to the P-type semiconductor layer in the active layer are first well layers,the first well layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated; the well layer except the first well layer in the active layer is a second well layer, and the second well layer comprises a fourth sub-layer, a fifth sub-layer and a sixth sub-layer which are sequentially laminated; in is adopted as the material of the second sub-layer and the material of the fifth sub-layerxGa1-xN, the material of the first sub-layer and the material of the third sub-layer are both AlaInbGa1-a-bN, adopting Al as the material of the fourth sublayer and the material of the sixth sublayercIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d).
Optionally, the growth temperature of the second sublayer and the growth temperature of the fifth sublayer are T1, the growth temperature of the first sublayer and the growth temperature of the third sublayer are T2, the growth temperature of the fourth sublayer and the growth temperature of the sixth sublayer are T3, the growth temperature of the barrier layer is T4, and T1 ≦ T2 ═ T3 < T4. The growth temperature of the InGaN layer is the lowest, so that In can be effectively prevented from being resolved at high temperature, the content of In components is ensured, and the light-emitting wavelength of an epitaxial wafer is prevented from being influenced; the growth temperature of the barrier layer is the highest, so that the good crystal quality of the barrier layer can be ensured; the growth temperature of the AlInGaN layer is between the barrier layer and the InGaN layer, so that the crystal quality of the AlInGaN layer can be guaranteed, and In analysis In the InGaN layer can be avoided.
Specifically, T1 is more than or equal to 780 ℃ and less than or equal to 820 ℃, such as T1 is 800 ℃; t2 is more than or equal to 820 ℃ and less than or equal to 840 ℃, such as T2 is 820 ℃; t3 is more than or equal to 820 ℃ and less than or equal to 840 ℃, such as T3 is 820 ℃; t4 is more than or equal to 845 ℃ and less than or equal to 875 ℃, and the realization effect is better if T4 is 860 ℃.
Specifically, this step 202 may include:
a first step of growing an N-type semiconductor layer on a substrate at a temperature of 1050 ℃ to 1100 ℃ (preferably 1080 ℃) and a pressure of 100torr to 500torr (preferably 300 torr);
secondly, controlling the pressure to be 100-500 torr (preferably 300torr), and growing an active layer on the N-type semiconductor layer;
and thirdly, controlling the temperature to be 850-1080 ℃ (preferably 960 ℃) and the pressure to be 100-300 torr (preferably 200torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the first step, the preparation method may further comprise:
a buffer layer is formed on a substrate.
Accordingly, an N-type semiconductor layer is grown on the buffer layer.
Specifically, forming the buffer layer on the substrate may include:
a Physical Vapor Deposition (PVD) technique is used to form a buffer layer on a substrate.
Preferably, after growing the buffer layer on the substrate, the preparation method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
the undoped gallium nitride layer is grown on the buffer layer under a temperature of 1000 ℃ to 1200 ℃ (preferably 1100 ℃) and a pressure of 100torr to 500torr (preferably 300 torr).
Optionally, before the second step, the preparation method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Accordingly, an active layer is grown on the stress relieving layer.
Specifically, growing the stress relief layer on the N-type semiconductor layer may include:
the temperature is controlled to be 800 ℃ to 1100 ℃ (preferably 950 ℃) and the pressure is controlled to be 100torr to 500torr (preferably 300torr), and the stress release layer is grown on the N-type semiconductor layer.
Optionally, before the third step, the preparation method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
the temperature is controlled to be 850 ℃ to 1080 ℃ (preferably 960 ℃), the pressure is controlled to be 200torr to 500torr (preferably 350torr), and the electron blocking layer is grown on the active layer.
Preferably, before growing the electron blocking layer on the active layer, the preparation method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the third step, the preparation method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device. Can adopt high-purity H when in realization2Or N2As the carrier gas, TEGa or TMGa, TMAl, TMIn and NH were used, respectively3As Ga source, Al source, In source and N source, respectively, and SiH can be used respectively4And Cp2Mg as N-type and P-type dopants, TeESi (tetraethyl silicon) and Si can also be used2H6As a Si source.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. The light-emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate; the active layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a well layer and a barrier layer laminated on the well layer; the active layer is characterized in that a plurality of well layers closest to the P-type semiconductor layer in the active layer are first well layers, and the first well layers comprise a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked; the well layer except the first well layer in the active layer is a second well layer which comprises a fourth sub-layer, a fifth sub-layer and a sixth sub-layer which are sequentially laminated; the material of the second sub-layer and the material of the fifth sub-layer both adopt InxGa1-xN, the material of the first sublayer and the material of the third sublayer are both AlaInbGa1-a-bN, the material of the fourth sublayer and the material of the sixth sublayer are both AlcIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d); the thickness of the first sub-layer is smaller than that of the second sub-layer, and the thickness of the second sub-layer is larger than that of the third sub-layer; the thickness of the fourth sublayer is smaller than that of the fifth sublayer, and the thickness of the fifth sublayer is larger than that of the sixth sublayer.
2. The light emitting diode epitaxial wafer of claim 1, wherein (a/b) > (4/9).
3. The light-emitting diode epitaxial wafer according to claim 2, wherein the thickness of the second sub-layer is 5-10 times that of the first sub-layer, and the thickness of the second sub-layer is 5-10 times that of the third sub-layer; the thickness of the fifth sublayer is 5-10 times that of the fourth sublayer, and the thickness of the fifth sublayer is 5-10 times that of the sixth sublayer.
4. The light emitting diode epitaxial wafer of claim 3, wherein the thickness of the second sub-layer is greater than the thickness of the fifth sub-layer; the thickness of the first sublayer, the thickness of the third sublayer, the thickness of the fourth sublayer and the thickness of the sixth sublayer are equal.
5. The light-emitting diode epitaxial wafer as claimed in claim 1 or 2, wherein the number of the first well layers is 1/5-1/2 of the total number of the well layers in the active layer.
6. The light emitting diode epitaxial wafer according to claim 5, wherein the number of the first well layers is 1 to 5.
7. The light emitting diode epitaxial wafer of claim 6, wherein the number of the second well layers is 4 to 8.
8. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the active layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a well layer and a barrier layer laminated on the well layer; the well layers closest to the P-type semiconductor layer in the active layer are first well layers, and each first well layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked; the well layer except the first well layer in the active layer is a second well layer comprising sequentially laminated layersA fourth sublayer, a fifth sublayer and a sixth sublayer; the material of the second sub-layer and the material of the fifth sub-layer both adopt InxGa1-xN, the material of the first sublayer and the material of the third sublayer are both AlaInbGa1-a-bN, the material of the fourth sublayer and the material of the sixth sublayer are both AlcIndGa1-c-dN, x, a, b, c, d are all positive numbers less than 1, (a/b) < (c/d); the thickness of the first sub-layer is smaller than that of the second sub-layer, and the thickness of the second sub-layer is larger than that of the third sub-layer; the thickness of the fourth sublayer is smaller than that of the fifth sublayer, and the thickness of the fifth sublayer is larger than that of the sixth sublayer.
9. The method of claim 8, wherein the growth temperature of the second sublayer and the growth temperature of the fifth sublayer are T1, the growth temperature of the first sublayer and the growth temperature of the third sublayer are T2, the growth temperature of the fourth sublayer and the growth temperature of the sixth sublayer are T3, the growth temperature of the barrier layer is T4, and T1 ≦ T2 ≦ T3 < T4.
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