CN114695610B - GaN-based LED epitaxial wafer, epitaxial growth method and LED chip - Google Patents
GaN-based LED epitaxial wafer, epitaxial growth method and LED chip Download PDFInfo
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
Abstract
The invention provides a GaN-based LED epitaxial wafer, an epitaxial growth method and an LED chip, wherein the epitaxial wafer comprises a quantum well layer formed by sequentially depositing a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer and a fifth quantum well sublayer, the first two sublayers are GaN layers, the rest sublayers are InGaN layers, si is doped in the process of growing the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer, and the Si doping concentration in the first quantum well sublayer and the second quantum well sublayer is higher than that in the third quantum well sublayer, wherein the Si doping can reduce the polarization electric field effect of a quantum well, improve the overlapping of electron and hole wave functions, further improve the radiation recombination efficiency and improve the luminous efficiency of a light-emitting diode.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a GaN-based LED epitaxial wafer, an epitaxial growth method and an LED chip.
Background
In recent years, with rapid improvement of lighting effect, gaN-based LEDs have been widely used in general illumination, display, and other fields. How to further improve the luminous efficiency of the LED is still a focus of attention in the LED industry.
When InGaN quantum wells are grown on GaN barriers, the polarization electric field of the InGaN well layer may reach MV/cm according to theoretical calculation and experimental measurement, resulting in the energy band tilt of the quantum well region, and then when electrons and holes pass through the quantum well region, severe spatial separation may be caused, resulting in the so-called Quantum Confinement Stark Effect (QCSE). Due to the spatial separation of carriers, the overlap of wave functions in the quantum well is reduced, the radiative recombination is reduced, and the luminous efficiency of the LED device is seriously reduced. The InGaN quantum well layer is generally set to a thickness of about 3nm in order to prevent the wave functions of electrons and holes from being separated throughout the multiple quantum well active region. Another method for reducing the polarization electric field of the InGaN quantum well layer is to grow InGaN material on the nonpolar/semipolar surface, thereby avoiding the separation of carriers caused by interface charges. Although this method can eliminate the polarization effect from the source, it is currently difficult to obtain a high quality epitaxial layer on the non-polar/semi-polar plane, and epitaxial growth and chip fabrication require additional processes. Currently, the research on GaN-based LEDs with non-polar/semi-polar substrates is still in the laboratory stage and is not widely used commercially.
The high In component In the InGaN quantum well increases lattice mismatch with the GaN barrier, resulting In a large piezoelectric field In the InGaN quantum well, increasing the polarization effect of the quantum well, inclining the energy band of the quantum well region, and causing severe spatial separation of electrons and holes when passing through the quantum well region, thereby generating the Quantum Confinement Stark Effect (QCSE). The quantum confinement stark effect reduces the coupling degree between electrons and hole wave functions in the quantum well, thereby reducing the quantum efficiency in the light-emitting diode and reducing the light-emitting efficiency of the light-emitting diode.
Disclosure of Invention
Based on this, the invention aims to provide a GaN-based LED epitaxial wafer, an epitaxial growth method and an LED chip, and aims to reduce the polarization effect of a quantum well and improve the internal quantum efficiency of a light-emitting diode, so as to improve the light-emitting efficiency of the light-emitting diode.
According to the GaN-based LED epitaxial wafer in the embodiment of the invention, the active layer comprises a quantum well layer and a quantum barrier layer which are alternately stacked in sequence, wherein the quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer, a third quantum well sub-layer, a fourth quantum well sub-layer and a fifth quantum well sub-layer which are deposited in sequence;
the first quantum well sublayer and the second quantum well sublayer are both GaN layers, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are all InGaN layers, si is doped in the process of growing the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer, and the doping concentration of Si in the first quantum well sublayer and the second quantum well sublayer is higher than that of Si in the third quantum well sublayer.
Preferably, the doping concentration of Si in the first quantum well sublayer and the second quantum well sublayer is 1-5 times that of Si in the third quantum well sublayer.
Preferably, the thickness of the active layer is from 2nm to 5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer ranges from 1 to 2.
Preferably, the doping concentration of Si in the first quantum well sublayer is 2.5E16 atoms/cm 3 ~1.25E18atoms/cm 3 The doping concentration of Si in the second quantum well sub-layer is 2.5E16 atoms/cm 3 ~1.25E18atoms/cm 3 The doping concentration of Si in the third quantum well sub-layer is 2.5E16 atoms/cm 3 ~2.5E17 atoms/cm 3 。
Preferably, the In component In the third quantum well sublayer ranges from 0.01 to 0.5, the In component is controlled to gradually change from low to high, and the In component In the fourth quantum well sublayer and the In component In the fifth quantum well sublayer range from 0.05 to 0.5.
According to the LED epitaxial wafer epitaxial growth method in the embodiment of the invention, the GaN-based LED epitaxial wafer is prepared, and the epitaxial growth method comprises the following steps:
providing a substrate required by growth;
sequentially epitaxially growing a buffer layer, a non-doped GaN layer and an N-type GaN layer on the substrate;
alternately growing quantum well layers and quantum barrier layers with preset cycle number on the N-type GaN layer to form an active layer;
sequentially growing an electron barrier layer and a P-type GaN layer on the last quantum barrier layer;
the quantum well layer is formed by sequentially growing a first quantum well sub-layer, a second quantum well sub-layer, a third quantum well sub-layer, a fourth quantum well sub-layer and a fifth quantum well sub-layer, wherein the first quantum well sub-layer and the second quantum well sub-layer are GaN layers, and the third quantum well sub-layer, the fourth quantum well sub-layer and the fifth quantum well sub-layer are InGaN layers.
Preferably, the growth pressure of the quantum well layer is 50 to 500 torr, the growth temperature is controlled to be a first temperature in the process of growing the first quantum well sublayer, the growth temperature is gradually reduced from the first temperature to 20 to 50 ℃ to a second temperature in the process of growing the second quantum well sublayer, the growth temperature is gradually reduced from the second temperature to 20 to 50 ℃ to a third temperature in the process of growing the third quantum well sublayer, and the first temperature is 820 to 880 ℃;
and in the process of growing the fourth quantum well sub-layer, controlling the growth temperature to be a fourth temperature, and in the process of growing the fifth quantum well sub-layer, controlling the growth temperature to gradually increase from the fourth temperature to 50-100 ℃ to a fifth temperature, wherein the fourth temperature is 750-830 ℃.
Preferably, the growth temperature of the quantum barrier layer is 800-900 ℃, and the growth pressure is 100-500 torr.
Preferably, the quantum well layer is only accessed with N during growth 2 And NH 3 Wherein the introduction of N is controlled 2 And said NH 3 The ratio of (A) to (B) is 1 to 2.
According to the embodiment of the invention, the LED chip comprises the GaN-based LED epitaxial wafer.
Compared with the prior art: the quantum well layer comprises a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer and a fifth quantum well sublayer which are deposited in sequence, wherein the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are InGaN layers, si is doped in the process of growing the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer, the doping concentration of Si in the first quantum well sublayer and the second quantum well sublayer is higher than that of Si in the third quantum well sublayer, the doping of Si can reduce the polarization electric field effect of a quantum well, the overlapping of electron and hole wave functions is improved, the doping concentration of Si in the third quantum well sublayer close to the fourth quantum well sublayer is low, the fact that Si moves to the fourth quantum well sublayer through atoms can be reduced, the non-radiative recombination of the fourth quantum well sublayer is reduced, the radiation efficiency is improved, and the light emitting efficiency of the light emitting diode is improved.
Drawings
Fig. 1 is a schematic structural diagram of a GaN-based LED epitaxial wafer according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of an active layer structure according to a first embodiment of the present invention;
fig. 3 is a flowchart of an epitaxial growth method of a GaN-based LED epitaxial wafer in the second embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
Referring to fig. 1 and 2, fig. 1 shows a GaN-based LED epitaxial wafer according to a first embodiment of the present invention, and fig. 2 shows a schematic structural view of an active layer, in which the GaN-based LED epitaxial wafer includes a sapphire substrate 10, and a buffer layer 20, an undoped GaN layer 30, an N-type GaN layer 40, an active layer 50, an electron blocking layer 60, and a P-type GaN layer 70, which are sequentially epitaxially grown on the sapphire substrate 10.
The active layer 50 includes quantum well layers (not shown) and quantum barrier layers 506 which are alternately stacked in sequence, the quantum well layers include a first quantum well sublayer 501, a second quantum well sublayer 502, a third quantum well sublayer 503, a fourth quantum well sublayer 504 and a fifth quantum well sublayer 505 which are deposited in sequence, the thickness of the single-layer quantum well layer is 2nm to 5nm, specifically, the first quantum well sublayer 501 and the second quantum well sublayer 502 are GaN layers, the third quantum well sublayer 503, the fourth quantum well sublayer 504 and the fifth quantum well sublayer 505 are InGaN layers, and the thickness ratio of the first quantum well sublayer 501, the second quantum well sublayer 502, the third quantum well sublayer 503, the fourth quantum well sublayer 504 and the fifth quantum well sublayer 505 is 1.
By way of example and not limitation, in some preferred embodiments of the present embodiment, the thickness of the buffer layer 20 is 10nm to 50nm, such as 12nm, 14nm, 16nm, etc.; the thickness of the undoped GaN layer 30 is 1 μm to 5 μm, for example, 2.2um, 2.4um, 2.6um, etc.; the thickness of the N-type GaN layer 40 is 2um to 3um, for example, 2.2um, 2.4um, 2.6um, etc.; the thickness of the active layer 50 is 55nm to 255nm, for example, 100nm, 120nm, 140nm, or the like; the thickness of the electron blocking layer 60 is 10nm to 40nm, for example, 15nm, 20nm, 35nm, or the like; the thickness of the P-type GaN layer 70 is 10nm to 50nm, for example, 15nm, 20nm, 25nm, etc.
Specifically, the quantum barrier layer 506 in the active layer 50 is an AlGaN layer, and in some preferred embodiments of the present embodiment, the thickness of the single quantum well layer is 2nm to 5nm, for example, 2.5nm, 3nm, 3.5nm, or the like; the thickness of the single AlGaN layer is 9nm to 12nm, for example, 9.5nm, 10nm, 11nm, and the like, wherein the number of stacking cycles of the quantum well layer and the quantum barrier layer 506 in the active layer 50 is 5 to 15, for example, 9, that is, there are 9 quantum well layers and quantum barrier layers 506, respectively.
Example two
Referring to fig. 3, a method for epitaxial growth of a GaN-based LED epitaxial wafer according to a second embodiment of the present invention is shown, the method specifically includes steps S201 to S208, wherein:
in step S201, a substrate required for growth is provided.
Wherein the substrate can be sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate.
Specifically, the substrate is a sapphire substrate, and the sapphire substrate has a mature preparation process, is low in price, is easy to clean and treat and has good stability at high temperature.
In this example, medium-micro A7 MOCVD (Metal-organic Chemical Vapor Deposition, MOCVD for short) equipment is used for high-purity H 2 (Hydrogen gas), high purity N 2 (Nitrogen), high purity H 2 And high purity N 2 One of the mixed gases of (1) is used as a carrier gas, high-purity NH 3 As the N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, trimethyl aluminum (TMAl) as aluminum sources, silane (SiH) 4 ) As N-type dopant, magnesium dicocene (CP) 2 Mg) as a P-type dopant.
Step S202, a buffer layer is grown, and the growth thickness of the buffer layer is 10 nm-50 nm.
It should be noted that the buffer layer may be made of AlN or GaN, in this embodiment, the AlN buffer layer is deposited in PVD, and the AlN buffer layer has a thickness of 15nm, and the AlN buffer layer is used to control crystal defects, improve the quality of the subsequently grown crystal, and relieve stress between the substrate and the epitaxial layer due to lattice mismatch and thermal mismatch.
Step S203, pre-treating the sapphire substrate on which the buffer layer has been deposited.
Specifically, the sapphire substrate coated with the AlN buffer layer was transferred to an MOCVD apparatus at H 2 And (3) pretreating for 1min to 10min in the atmosphere at the temperature of 1000-1200 ℃, and then nitriding the sapphire substrate, so that the crystal quality of the AlN buffer layer is improved, and the crystal quality of the post-deposition GaN epitaxial layer can be effectively improved.
Step S204, growing the non-doped GaN layer with the growth thickness of 1-5 μm.
Specifically, the growth temperature of the undoped GaN layer is 1050-1200 ℃, the growth pressure is 100torr-600torr, in the embodiment, the growth temperature of the undoped GaN layer is 1100 ℃, the growth pressure is 150 torr, and the growth thickness is 2-3 μm.
And S205, growing an N-type GaN layer with the growth thickness of 2 um-3 um.
Specifically, the growth temperature of the N-type GaN layer is 1050-1200 ℃, the growth pressure is 100torr-600torr, si is doped in the growth process, and the doping concentration of Si is 1E19 atoms/cm 3 ~5E19 atoms/cm 3 In this example, the growth temperature of the N-type GaN layer was 1120 ℃, the growth pressure was 100torr, and the Si doping concentration was 2.5E19 atoms/cm 3 The interface resistance of the N-type GaN grown under the condition is 12 omega cm 2 The resistance value of the contact resistance of the P-type layer and the ITO is equivalent to that of the contact resistance of the P-type layer and the ITO, so that the current concentration effect is reduced, and the photoelectric efficiency of the light-emitting diode is improved.
Step S206, growing an active layer with the growth thickness of 55 nm-255 nm.
The active layer comprises a quantum well layer and a quantum barrier layer which alternately grow in sequence, the quantum well layer comprises a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer and a fifth quantum well sublayer which grow in sequence, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are InGaN layers, and the quantum barrier layer is an AlGaN layer.
Doping Si in the process of growing the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer, wherein the concentration of the doped Si in the growth process of the first quantum well sublayer and the second quantum well sublayer is controlled to be a first doping concentration, the concentration of the doped Si in the growth process of the third quantum well sublayer is controlled to be a second doping concentration, the first doping concentration is 1-5 times of the second doping concentration, and specifically, the first doping concentration is 2.5E16 atoms/cm 3 ~1.25E18atoms/cm 3 The second doping concentration is 2.5E16 atoms/cm 3 ~2.5E17 atoms/cm 3 。
The In component In the third quantum well sublayer ranges from 0.01 to 0.5, the In component In the fourth quantum well sublayer and the In component In the fifth quantum well sublayer ranges from 0.05 to 0.5, and the In component of the third quantum well sublayer is controlled to gradually change from low to high In the growth process.
Specifically, the growth pressure of the quantum well layer is 50-500 torr, and only the atmosphere N is introduced into the quantum well layer in the growth process 2 And NH 3 Controlling the introduction of said atmosphere N 2 And NH 3 The ratio of (1) 3 Without passing through the atmosphere H 2 The crystal quality of an InGaN layer can be improved, inGaN decomposition is reduced, and therefore the effect of reducing the quantum well polarization effect is achieved on the one hand, in addition, in the process of growing a first quantum well sub-layer, the growth temperature is controlled to be the first temperature, in the process of growing a second quantum well sub-layer, the growth temperature is controlled to be gradually reduced from the first temperature to 20-50 ℃ to the second temperature, in the process of growing a third quantum well sub-layer, the growth temperature is controlled to be gradually reduced from the second temperature to 20-50 ℃ to the third temperature, and the first temperature is 820-880 ℃.
And in the process of growing the fourth quantum well sub-layer, controlling the growth temperature to be a fourth temperature, and in the process of growing the fifth quantum well sub-layer, controlling the growth temperature to gradually increase from the fourth temperature to 50-100 ℃ to a fifth temperature, wherein the fourth temperature is 750-830 ℃.
It can be understood that, because the growth temperature of the first quantum well sublayer is higher, the growth temperature of the second quantum well sublayer is reduced on the basis of the growth temperature of the first quantum well sublayer, because the second quantum well sublayer is a GaN layer, the third quantum well sublayer and the fourth quantum well sublayer are InGaN layers, and then In the process of growing the third quantum well sublayer, the growth temperature and the gradual change of In components are controlled, the transition from the third quantum well sublayer to the fourth quantum well sublayer is completed, so that the lattice mismatch of InGaN of the quantum well layer is reduced, the InGaN crystal quality of the quantum well layer is ensured, the nonradiative recombination efficiency is reduced, and the effect of reducing the polarization effect of the quantum well is achieved on the other hand.
After the growth of the quantum well layer is finished, in the process of growing the quantum barrier layer, the growth temperature of the quantum barrier layer is controlled to be 800-900 ℃, the growth pressure is controlled to be 100-500 torr, and the concentration of the Al component is 0.01-0.2.
And step S207, growing the electron blocking layer with the growth thickness of 10 nm-40 nm.
Wherein the electron blocking layer is Al x In y Ga 1-x-y The growth temperature of the N layer is 900-1000 ℃, the growth pressure is 100torr-300torr, wherein the Al component is 0.005<x<0.1,in component concentration of 0.05<y<0.2。
Specifically, the electron blocking layer is Al 0.05 In 0.1 Ga 0.85 And the thickness of the N layer is 15nm, the growth temperature is 965 ℃, and the growth pressure is 200torr, so that the electron overflow can be effectively limited, and the blocking of holes can be reduced.
And S208, growing a P-type GaN layer with the growth thickness of 10 nm-50 nm.
Wherein the growth temperature of the P-type GaN layer is 900-1050 ℃, the growth pressure is 100torr-600torr, the Mg doping concentration is 1E19 atoms/cm 3 ~1E21 atoms/cm 3 。
Specifically, the growth temperature of the P-type GaN layer is 985 ℃, the thickness of the P-type GaN layer is 15nm, and the P-type GaN layer growsThe pressure is 200torr, and the Mg doping concentration is 2E20 atoms/cm 3 。
To sum up, in the epitaxial growth method of the LED epitaxial wafer in the embodiment of the present invention, the buffer layer, the undoped GaN layer, the N-type GaN layer, the active layer, the electron blocking layer and the P-type GaN layer are sequentially deposited on the substrate, the active layer includes the quantum well layer and the quantum barrier layer which are sequentially and alternately stacked, the quantum well layer includes the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer which are sequentially deposited, wherein the first quantum well sublayer and the second quantum well sublayer are GaN layers, and the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are InGaN layers 2 /NH 3 And the InGaN layer grows under low pressure, the crystal quality of the InGaN layer can be improved, in addition, the growth temperature of the InGaN layer In the growth process and the gradual change of In components further guarantee the InGaN crystal quality of a quantum well layer, so that the radiation recombination efficiency is improved, and the improvement of the light emitting efficiency of the light emitting diode is realized.
EXAMPLE III
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electronic barrier layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it should be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 Controlling the third quantum wellThe concentration of doped Si in the layer during growth is 2.5E17 atoms/cm 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that the quantum well layer is grown in the atmosphere N only 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The growth pressure is 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to be 850 ℃, the growth temperature of the second quantum well layer is controlled to be gradually reduced from the growth temperature of the first quantum well sublayer to 40 ℃ to 810 ℃, the growth temperature of the third quantum well layer is controlled to be gradually reduced from the growth temperature of the second quantum well layer to 15 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to be 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to be gradually increased from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
When the chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 1.5%, and other electrical properties are good.
Example four
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it is to be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 The concentration of doped Si of the third quantum well sub-layer in the growth process is controlled to be 1E17 atoms/cm 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that, during the growth of the quantum well layer, only the atmosphere N is introduced 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The growth pressure is 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to be 850 ℃, the growth temperature of the second quantum well layer is controlled to be gradually reduced from the growth temperature of the first quantum well sublayer to 40 ℃ to 810 ℃, the growth temperature of the third quantum well layer is controlled to be gradually reduced from the growth temperature of the second quantum well layer to 15 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to be 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to be gradually increased from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
When the chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 0.5%, and other electric properties are good.
EXAMPLE five
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it is to be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 1E17 atoms/cm 3 Controlling the concentration of doped Si of the third quantum well sub-layer to be 2.5E16 atoms/cm during the growth process 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that, during the growth of the quantum well layer, only the atmosphere N is introduced 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The growth pressure is 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to be 850 ℃, the growth temperature of the second quantum well layer is controlled to be gradually reduced from the growth temperature of the first quantum well sublayer to 40 ℃ to 810 ℃, the growth temperature of the third quantum well layer is controlled to be gradually reduced from the growth temperature of the second quantum well layer to 15 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to be 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to be gradually increased from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
When the chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 1%, and other electric properties are good.
Example six
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it is to be noted that the thickness of the quantum well layer is 3.2 nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 Controlling the concentration of doped Si of the third quantum well sub-layer to be 2.5E17 atoms/cm during the growth process 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that the quantum well layer is grown in the atmosphere N only 2 And NH 3 Wherein the atmosphere N is controlled to be introduced 2 And NH 3 The growth pressure is 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to 845 ℃, the growth temperature of the second quantum well layer is controlled to be gradually reduced from the growth temperature of the first quantum well sublayer to 30 ℃ to 815 ℃, the growth temperature of the third quantum well layer is controlled to be gradually reduced from the growth temperature of the second quantum well layer to 20 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to be 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to be gradually increased from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
The chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 0.8%, and other electric properties are good.
EXAMPLE seven
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electronic barrier layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it should be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 Controlling the concentration of doped Si of the third quantum well sub-layer to be 2.5E17 atoms/cm during the growth process 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that, during the growth of the quantum well layer, only the atmosphere N is introduced 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The ratio of (1) to (1.5) and the growth pressure of 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to 845 ℃, the growth temperature of the second quantum well layer is controlled to gradually decrease from the growth temperature of the first quantum well sublayer to 815 ℃, the growth temperature of the third quantum well layer is controlled to gradually decrease from the growth temperature of the second quantum well layer to 20 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to gradually increase from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
When the chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 1.2%, and other electric properties are good.
Example eight
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it is to be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 2.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 Controlling the concentration of doped Si of the third quantum well sub-layer to be 2.5E17 atoms/cm during the growth process 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.05 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that the quantum well layer is grown in the atmosphere N only 2 And NH 3 Wherein the atmosphere N is controlled to be introduced 2 And NH 3 The ratio of (1) to (1.5) and the growth pressure of 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to 845 ℃, the growth temperature of the second quantum well layer is controlled to gradually decrease from the growth temperature of the first quantum well sublayer to 815 ℃, the growth temperature of the third quantum well layer is controlled to gradually decrease from the growth temperature of the second quantum well layer to 20 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to gradually increase from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, the growth pressure is 200torr, and the Al component is 0.05.
When the chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 0.5%, and other electric properties are good.
Example nine
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it is to be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the concentration of doped Si in the growth process of the first quantum well sub-layer and the second quantum well sub-layer is controlled to be 5E17 atoms/cm 3 Controlling the concentration of doped Si in the third quantum well sub-layer in the growth process to be 2.5E17 atoms/cm 3 In addition, in the growth process of the third quantum well sub-layer, the In component is gradually changed from 0.1 to 0.25, the In component In the fourth quantum well sub-layer is 0.25, and the In component In the fifth quantum well sub-layer is 0.25.
It should be noted that the quantum well layer is grown in the atmosphere N only 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The ratio of (1) to (1.5) and the growth pressure of 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to 845 ℃, the growth temperature of the second quantum well layer is controlled to gradually decrease from the growth temperature of the first quantum well sublayer to 815 ℃, the growth temperature of the third quantum well layer is controlled to gradually decrease from the growth temperature of the second quantum well layer to 20 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to gradually increase from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. The quantum barrier layer is an AlGaN layer, the growth temperature is 855 ℃, the thickness is 9.8nm, and the growth pressure isThe force was 200torr and the Al composition was 0.05.
The chip prepared by the embodiment is tested under the current of 120 mA/60 mA, the photoelectric efficiency is improved by 1%, and other electric properties are good.
Example ten
In this embodiment, a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electronic barrier layer, and a P-type GaN layer are sequentially deposited on a sapphire substrate, where the active layer is a quantum well layer and a quantum barrier layer that are sequentially and alternately stacked, the number of stacking cycles is 10, the quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer, and a fifth quantum well sublayer that are sequentially grown, the first quantum well sublayer and the second quantum well sublayer are GaN layers, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer are InGaN layers, and it should be noted that the thickness of the quantum well layer is 3.5nm, and the thickness ratio of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer, and the fifth quantum well sublayer is 1.5.
Specifically, the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer are controlled not to be doped with Si In the growth process, in addition, in component is controlled to be gradually changed from 0.05 to 0.25 In the growth process of the third quantum well sublayer, in component In the fourth quantum well sublayer is 0.25, and In component In the fifth quantum well sublayer is 0.25.
It should be noted that the quantum well layer is grown in the atmosphere N only 2 And NH 3 Wherein the introduction of the atmosphere N is controlled 2 And NH 3 The growth pressure is 200torr, more specifically, the production temperature of the first quantum well sublayer is controlled to be 850 ℃, the growth temperature of the second quantum well layer is controlled to be gradually reduced from the growth temperature of the first quantum well sublayer to 40 ℃ to 810 ℃, the growth temperature of the third quantum well layer is controlled to be gradually reduced from the growth temperature of the second quantum well layer to 15 ℃ to 795 ℃, the growth temperature of the fourth quantum well layer is controlled to be 795 ℃, and the growth temperature of the fifth quantum well layer is controlled to be gradually increased from the growth temperature of the fourth quantum well layer to 75 ℃ to 870 ℃. Quantum barrierThe AlGaN layer has the growth temperature of 855 ℃, the thickness of 9.8nm, the growth pressure of 200torr and the Al component of 0.05.
The chip prepared by the embodiment is tested under the current of 120 mA/60 mA, and the photoelectric efficiency is not improved.
The photoelectric efficiency of the GaN-based LED chip in the prior art and the photoelectric efficiency of the GaN-based LED chip proposed by the present invention are respectively compared, as specifically shown in table 1:
TABLE 1
As can be seen from the table, the photoelectric efficiency of the GaN-based LED chip provided by the invention is greatly improved compared with that of the GaN-based LED chip in the prior art.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (7)
1. The GaN-based LED epitaxial wafer is characterized in that an active layer comprises a quantum well layer and a quantum barrier layer which are sequentially and alternately stacked, and the quantum well layer comprises a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer and a fifth quantum well sublayer which are sequentially deposited;
the first quantum well sublayer and the second quantum well sublayer are both GaN layers, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are all InGaN layers, si is doped in the process of growing the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer, and the first quantum well sublayer and the second quantum well sublayerThe doping concentration of Si in the sub-layer is 2.5E16 atoms/cm 3 ~1.25E18 atoms/cm 3 The doping concentration of Si in the third quantum well sub-layer is 2.5E16 atoms/cm 3 ~2.5E17 atoms/cm 3 And the doping concentration of Si in the first quantum well sublayer and the second quantum well sublayer is 1 to 2 times that of Si in the third quantum well sublayer, the thickness ratio ranges of the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are 1 to 2 2 And NH 3 And is introduced into said N 2 And said NH 3 The ratio of (A) to (B) is 1 to 2.
2. The GaN-based LED epitaxial wafer according to claim 1, wherein the thickness of the active layer is from 2nm to 5nm.
3. The GaN-based LED epitaxial wafer of claim 1, wherein the In composition In the third quantum well sub-layer is controlled to be 0.01 to 0.5, the In composition is controlled to be gradually changed from low to high, and the In composition In the fourth quantum well sub-layer and the In composition In the fifth quantum well sub-layer are both 0.05 to 0.5.
4. An epitaxial growth method of an LED epitaxial wafer for producing the GaN-based LED epitaxial wafer of any one of claims 1 to 3, the epitaxial growth method comprising:
providing a substrate required by growth;
sequentially epitaxially growing a buffer layer, a non-doped GaN layer and an N-type GaN layer on the substrate;
alternately growing quantum well layers and quantum barrier layers with preset period numbers on the N-type GaN layer to form an active layer;
sequentially growing an electron barrier layer and a P-type GaN layer on the last quantum barrier layer;
the quantum well structure comprises a substrate, a first quantum well sublayer, a second quantum well sublayer, a third quantum well sublayer, a fourth quantum well sublayer and a fifth quantum well sublayer, wherein the first quantum well sublayer, the second quantum well sublayer, the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are grown in sequence to form the quantum well layer, the first quantum well sublayer and the second quantum well sublayer are GaN layers, and the third quantum well sublayer, the fourth quantum well sublayer and the fifth quantum well sublayer are InGaN layers.
5. The epitaxial growth method of the LED epitaxial wafer according to claim 4, wherein the growth pressure of the quantum well layer is 50 to 500 torr, the growth temperature is controlled to be a first temperature in the process of growing the first quantum well sub-layer, the growth temperature is gradually reduced from the first temperature to a second temperature from 20 to 50 ℃ in the process of growing the second quantum well sub-layer, and the growth temperature is gradually reduced from the second temperature to 20 to 50 ℃ to a third temperature in the process of growing the third quantum well sub-layer, wherein the first temperature is 820 to 880 ℃;
and in the process of growing the fourth quantum well sub-layer, controlling the growth temperature to be a fourth temperature, and in the process of growing the fifth quantum well sub-layer, controlling the growth temperature to gradually increase from the fourth temperature to 50-100 ℃ to a fifth temperature, wherein the fourth temperature is 750-830 ℃.
6. The epitaxial growth method of the LED epitaxial wafer according to claim 4, wherein the growth temperature of the quantum barrier layer is 800 ℃ to 900 ℃, and the growth pressure is 100torr to 500 torr.
7. An LED chip comprising the GaN-based LED epitaxial wafer according to any one of claims 1 to 3.
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