CN116487493A - LED epitaxial wafer, preparation method thereof and LED chip - Google Patents
LED epitaxial wafer, preparation method thereof and LED chip Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a light-emitting diode epitaxial wafer, a preparation method thereof and an LED chip, wherein the light-emitting diode epitaxial wafer comprises the following components: the semiconductor device comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked, wherein the active layer comprises a composite quantum well layer and a quantum barrier layer which are periodically and alternately stacked, and the composite quantum well layer comprises an N-type InGaN quantum well preparation layer, an In quantum dot layer deposited on the N-type InGaN quantum well preparation layer, an InGananocluster layer deposited on the In quantum dot layer and an InGaN quantum well sub-layer deposited on the InGananocluster layer. The invention reduces In agglomeration, improves the crystal quality of the quantum well layer, improves the radiation recombination efficiency of the quantum well and improves the luminous efficiency of the light-emitting diode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and an LED chip.
Background
With the deep research of III-nitride materials and the mature device preparation process, the ultraviolet and blue LEDs have higher external quantum efficiency. However, as the In component of the InGaN well of the quantum well active layer increases, the light emission wavelength gradually goes deep into the yellow-green light band, and the external quantum efficiency of the LED is significantly reduced, especially the external quantum efficiency of the 550 nm green LED, which is most sensitive to the human eye, is lower than 10%, which is due to the reduction of the internal quantum efficiency caused by the material quality. Currently, commercial green LEDs are used at 50A/cm 2 The internal quantum efficiency under electric injection is only 30%.
At present, the commercial high-efficiency GaN-based blue-green LED generally adopts InGaN multiple quantum wells as active regions. Therefore, the high-quality InGaN multi-quantum well is a key for realizing the high-efficiency and high-brightness luminous tube. However, in agglomeration often occurs In the current process of depositing an InGaN quantum well layer, so that the crystal quality of the quantum well layer is low, and the luminous efficiency is affected.
Disclosure of Invention
Based on the above, the invention aims to provide a light-emitting diode epitaxial wafer, a preparation method thereof and an LED chip, and aims to reduce In agglomeration, improve the crystal quality of a quantum well layer, improve the radiation recombination efficiency of the quantum well and improve the luminous efficiency of the light-emitting diode.
The invention discloses a light-emitting diode epitaxial wafer, which comprises: the semiconductor device comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked, wherein the active layer comprises a composite quantum well layer and a quantum barrier layer which are periodically and alternately stacked, and the composite quantum well layer comprises an N-type InGaN quantum well preparation layer, an In quantum dot layer deposited on the N-type InGaN quantum well preparation layer, an InGananocluster layer deposited on the In quantum dot layer and an InGaN quantum well sub-layer deposited on the InGananocluster layer.
Further, in the light emitting diode epitaxial wafer, the thickness of the N-type InGaN quantum well preparation layer is 0.5 nm-5 nm, the thickness of the In quantum dot layer is 0.1 nm-1 nm, the thickness of the InGaN nanocluster layer is 0.2 nm-2 nm, and the thickness of the InGaN quantum well sub-layer is 1 nm-10 nm.
Further, in the light emitting diode epitaxial wafer, the In component of the N-type InGaN quantum well preparation layer is lower than the In component of the InGaN quantum well sub-layer.
Further, in the above light emitting diode epitaxial wafer, the In component of the InGaN quantum well sub-layer is 0.01-0.5.
Further, in the led epitaxial wafer, the Si doping concentration in the N-type InGaN quantum well preparation layer is 1E+16~1E+18 atoms/cm 3 。
Further, in the above light emitting diode epitaxial wafer, the first semiconductor layer includes a buffer layer, an undoped GaN layer and an N-type GaN layer sequentially deposited on the substrate, and the second semiconductor layer includes an electron blocking layer and a P-type GaN layer sequentially deposited on the active layer.
The invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
depositing a buffer layer on the substrate;
pretreating the substrate deposited with the buffer layer;
depositing an undoped GaN layer on the buffer layer;
depositing an N-type GaN layer on the undoped GaN layer;
depositing an active layer on the N-type GaN layer;
depositing an electron blocking layer on the active layer;
depositing a P-type GaN layer on the electron blocking layer;
the active layer comprises a composite quantum well layer and a quantum barrier layer which are periodically and alternately stacked, wherein the composite quantum well layer comprises an N-type InGaN quantum well preparation layer, an In quantum dot layer deposited on the N-type InGaN quantum well preparation layer, an InGananocluster layer deposited on the In quantum dot layer, and an InGaN quantum well sub-layer deposited on the InGananocluster layer.
Further, the preparation method of the light emitting diode epitaxial wafer, wherein the growing step of the composite quantum well layer comprises the following steps:
turn on N 2 And NH 3 At N 2 And NH 3 Introducing TEGa, TMIn and SiH into the mixed atmosphere of (a) 4 Depositing an N-type InGaN quantum well preparation layer;
shut off NH 3 And stopping the introduction of TEGa and SiH 4 Keep N 2 Opening and TMIn introducing, and depositing an In quantum dot layer;
keep N 2 Opening, introducing TMIn and TEGa, and depositing an InGananocluster layer;
turn on N 2 And NH 3 TMIn and TEGa are kept in, and InGaN quantum well sublayers are deposited.
Further, in the preparation method of the light-emitting diode epitaxial wafer, the growth temperature of the composite quantum well layer is 700-1000 ℃, and the growth pressure is 50-300 torr and N 2 And NH 3 N in the mixed atmosphere of (2) 2 And NH 3 The ratio of (2) is 10:1-1:10.
The invention also discloses an LED chip which is characterized by comprising the light-emitting diode epitaxial wafer.
According to the invention, through the design of the N-type InGaN quantum well preparation layer, the In quantum dot layer, the InGananocluster layer and the InGaN quantum well sub-layer, the In agglomeration is reduced, the crystal quality of the quantum well layer and the quantum well radiation recombination efficiency are improved, and the luminous efficiency of the light emitting diode is improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a composite quantum well layer according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a high light efficiency led epitaxial wafer according to an embodiment of the present invention.
Description of main reference numerals:
100: substrate, 200: buffer layer, 300: undoped GaN layer, 400: n-type GaN layer, 500: active layer, 510: composite quantum well layer, 520: quantum barrier layer, 600: electron blocking layer, 700: p-type GaN layer, 511: n-type InGaN quantum well preparation layer, 512: in quantum dot layer, 513: inGa nanocluster layer, 514: inGaN quantum well sublayers.
The following detailed description will further illustrate the invention in conjunction with the above-described drawings.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, an led epitaxial wafer in embodiment 1 of the present invention includes a substrate 100, a first semiconductor layer, an active layer 500, and a second semiconductor layer sequentially stacked. The first semiconductor layer includes a buffer layer 200, an undoped GaN layer 300, and an N-type GaN layer 400 sequentially deposited on a substrate 100. The second semiconductor layer includes an electron blocking layer 600 and a P-type GaN layer 700 sequentially deposited on the active layer 500.
The substrate 100 may be a sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate. Specifically, in this embodiment, the substrate 100 is a sapphire substrate, which is the most commonly used GaN-based LED substrate material at present, and has the advantages of mature preparation process, low price, easy cleaning and processing, and good stability at high temperature.
The buffer layer 200 has a thickness of 15 a nm a, and by using an AlN buffer layer, it can provide nucleation centers oriented in the same manner as the substrate 100, relieve stress caused by lattice mismatch between the undoped GaN layer 300 and the substrate and thermal stress caused by thermal expansion coefficient mismatch, and further growth provides a flat nucleation surface, reducing the contact angle of nucleation growth to enable island-grown GaN grains to be connected into planes in a smaller thickness, and converting into two-dimensional epitaxial growth.
The thickness of the undoped GaN layer 300 is 2. 2 um-3 um, and in this embodiment, the thickness is 2.5 um. Along with the increase of the GaN thickness, the compressive stress can be released through stacking faults, the line defects are reduced, the crystal quality is improved, the reverse leakage current is reduced, but the increase of the GaN layer thickness consumes a Ga source material greatly, and the epitaxial cost of an LED is greatly increased, so that the conventional LED epitaxial wafer is usually grown by undoped GaN for 2 um-3 um, the production cost is saved, and the GaN material has higher crystal quality.
The thickness of the N-type GaN layer 400 is 2 um-3 um, and the doping concentration of Si is 1E+19~5E+19 atoms/cm 3 . As in this embodiment, the N-type GaN layer has a growth thickness of 2.5um and a Si doping concentration of 2.5E+19 atoms/cm 3 . The N-type GaN layer 400 can provide sufficient electrons for LED light emission, and the resistivity of the N-type GaN layer 400 is higher than that of the transparent electrode on the p-GaN, so that the enough Si doping can effectively reduce the resistivity of the N-type GaN layer 400, and ensure that the N-type GaN hasThe sufficient thickness can effectively release the luminous efficiency of the stress led.
The active layer 500 includes a composite quantum well layer 510 and a quantum barrier layer 520 which are alternately stacked periodically, and the number of stacking periods is 1 to 20.
As shown In fig. 2, the composite quantum well layer 510 includes an N-type InGaN quantum well preparation layer 511, an In quantum dot layer 512 deposited on the N-type InGaN quantum well preparation layer 511, an InGa nanocluster layer 513 clad on the In quantum dot layer 512, and an InGa quantum well sub-layer 514 clad on the InGa nanocluster layer 513. The thickness of the N-type InGaN quantum well preparation layer 511 is 0.5 nm-5 nm, the thickness of the in quantum dot layer 512 is 0.1 nm-1 nm, the thickness of the InGaN nanocluster layer 513 is 0.2-nm-2 nm, and the thickness of the InGaN quantum well sub-layer 514 is 1 nm-10 nm. Specifically, in this embodiment, the thickness of the N-type InGaN quantum well preparation layer 511 is 1nm, the thickness of the in quantum dot layer 512 is 0.5 nm, the thickness of the InGaN nanocluster layer 513 is 1nm, and the thickness of the InGaN quantum well sub-layer 514 is 3.5 nm.
The In composition of the InGaN quantum well sub-layer 514 is 0.01-0.5, and the In composition of the N-type InGaN quantum well preparation layer 511 is lower than that of the InGaN quantum well sub-layer 514. The In composition of the N-type InGaN quantum well preparation layer 511 is 0.1 and the In composition of the InGaN quantum well sub-layer 514 is 0.15 as In the present embodiment. The InGaN quantum well preparation layer has an In component lower than that of the InGaN quantum well sub-layer, so that lattice mismatch of GaN and the InGaN quantum well can be reduced, and crystal quality of the InGaN quantum well sub-layer is improved, and radiation recombination efficiency of the quantum well is improved.
The Si doping concentration in the N-type InGaN quantum well preparation layer 511 is 1E+16~1E+18 atoms/cm 3 In the present embodiment, the Si doping concentration in the N-type InGaN quantum well preparation layer 511 is 1E+17 atoms/cm 3 . The doping of Si In the N-type InGaN quantum well preparation layer 511 can effectively shield the piezoelectric field caused by mismatch stress, alleviate the adverse effect of QCSE effect, improve the radiation recombination efficiency, provide a flat surface for the subsequent deposition of the In quantum dot layer 512, reduce the contact angle for the growth of the In quantum dot layer 512, and avoid agglomeration of the In quantum dot layer 512.
The In quantum dot layer 512 is deposited to ensure the density of the subsequently deposited InGa nanocluster layer 513, reducing the degradation of crystal quality caused by premature fusion of the InGa nanocluster layer 513. The InGaN nanocluster layer 513 not only improves the doping uniformity of In components In the InGaN quantum well sub-layer 514 deposited later, avoids In agglomeration, improves the quantum well localization effect of the InGaN quantum well sub-layer 514, but also can reduce lattice mismatch of the InGaN quantum well sub-layer deposited later and improve the crystal quality of the InGaN quantum well sub-layer 514.
The InGaN quantum well sub-layer 514 generally has a thickness of 2-3 nm, is less than the de broglie wavelength of electrons, has discrete quantized energy levels of electrons and holes, and has a significant quantum confinement effect.
In order to improve quantum confinement, the active layer is generally grown with multiple periodic structures, and under the condition of electric injection, electrons and holes are localized in the multiple quantum wells, so that overlapping of wave functions of the electrons and the holes is improved, and the radiation recombination rate is further improved.
Optionally, the electron blocking layer 600 is an AlInGaN layer with a thickness of 10-40 nm, and in this embodiment, the thickness of the electron blocking layer 600 is 15-nm. The electron blocking layer 600 has an Al component of 0.005< x <0.1 and an in component concentration of 0.01< y <0.2. As In the present embodiment, the In component concentration In the electron blocking layer 600 is 0.01, and the Al component concentration gradually changes from 0.01 to 0.05 along the epitaxial layer growth direction. The electron blocking layer 600 can not only effectively limit electron overflow, but also reduce blocking of holes, improve injection efficiency of holes into the quantum well, reduce carrier auger recombination, and improve luminous efficiency of the light emitting diode.
Optionally, the thickness of the P-type GaN layer 700 is 10-50 nm, and the doping concentration of Mg is 1E+19~1E+21 atoms/cm 3 . Specifically, the thickness of the P-type GaN layer in this embodiment is 15nm, and the Mg doping concentration is 2E+20 atoms/cm 3 . Too high a Mg doping concentration can damage the crystal quality, while a lower doping concentration can affect the hole concentration.
According to the composite quantum well layer, through the design of the N-type InGaN quantum well preparation layer, the In quantum dot layer, the InGananocluster layer and the InGaN quantum well sub-layer, in agglomeration is reduced, crystal quality of the quantum well layer and quantum well radiation composite efficiency are improved, and luminous efficiency of the light emitting diode is improved.
Referring to fig. 3, a method for preparing an led epitaxial wafer according to an embodiment of the present invention includes steps S01 to S08.
In step S01, a substrate is provided.
The substrate can be one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate.
Step S02, depositing a buffer layer on the substrate.
Specifically, an AlN buffer layer is deposited in the PVD (physical vapor deposition) application material, the thickness of the AlN buffer layer is 15nm, the AlN buffer layer provides a nucleation center which is the same as the substrate orientation, stress generated by lattice mismatch between GaN and the substrate and thermal stress generated by thermal expansion coefficient mismatch are released, a flat nucleation surface is provided by further growth, and the contact angle of nucleation growth is reduced, so that island-shaped GaN grains can be connected into a plane in a smaller thickness, and the island-shaped GaN grains are converted into two-dimensional epitaxial growth.
In the embodiment, a medium-micro A7 MOCVD (Metal-organic Chemical Vapor Deposition Metal organic vapor deposition, MOCVD for short) device is adopted to obtain high-purity H 2 (Hydrogen), high purity N 2 (Nitrogen) high purity H 2 And high purity N 2 Is used as carrier gas, high-purity NH 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, trimethylaluminum (TMAL) as aluminum source, silane (SiH) 4 ) As an N-type dopant, magnesium-bis-cyclopentadienyl (CP 2 Mg) was epitaxially grown as a P-type dopant.
Step S03, preprocessing the substrate deposited with the buffer layer.
Specifically, the sapphire substrate plated with the AlN buffer layer is transferred into MOCVD, and then is subjected to H 2 The atmosphere is preprocessed for 1-10 min, the processing temperature is 1000-1200 ℃, and then the sapphire substrate is nitrided, so that the crystal quality of the AlN buffer layer is improved, and the crystal quality of the subsequent deposited GaN epitaxial layer can be effectively improved.
Step S04, depositing an undoped GaN layer on the buffer layer.
Optionally, the growth temperature of the undoped GaN layer is 1050-1200 ℃, the pressure is 100-600 torr, and the thickness is 1 um-5 um.
Specifically, the growth temperature of the undoped GaN layer is 1100 ℃, the growth pressure is 150 torr, the growth thickness is 2.5um, the growth temperature of the undoped GaN layer is higher, the pressure is lower, and the quality of the prepared GaN crystal is better.
And S05, depositing an N-type GaN layer on the undoped GaN layer.
Optionally, the growth temperature of the N-type GaN layer is 1050-1200 ℃, the pressure is 100-600 torr, the thickness is 2-um-3 um, and the Si doping concentration is 1E+19~5E+19 atoms/cm 3 . Specifically, in this embodiment, the growth temperature of the N-type GaN layer is 1120 ℃, the growth pressure is 100 torr, the growth thickness is 2.5um, and the Si doping concentration is 2.5E+19 atoms/cm 3 。
And step S06, depositing an active layer on the N-type GaN layer.
The active layer comprises a plurality of composite quantum well layers and quantum barrier layers which are alternately stacked, wherein the composite quantum well layers comprise N-type InGaN quantum well preparation layers, in quantum dot layers deposited on the N-type InGaN quantum well preparation layers, inGaN nanocluster layers coated on the In quantum dot layers and InGaN quantum well sub-layers coated on the InGaN nanocluster layers.
The growth method of the active layer comprises the following steps:
turn on N 2 And NH 3 At N 2 And NH 3 Introducing TEGa, TMIn and SiH into the mixed atmosphere of (a) 4 Depositing an N-type InGaN quantum well preparation layer;
shut off NH 3 And stopping the introduction of TEGa and SiH 4 Keep N 2 Opening and TMIn introducing, and depositing an In quantum dot layer;
keep N 2 Opening, introducing TMIn and TEGa, and depositing an InGananocluster layer;
turn on N 2 And NH 3 TMIn and TEGa are kept in, and InGaN quantum well sublayers are deposited.
The growth temperature of the composite quantum well layer is 700-1000 ℃ and the growth pressure is 50-300 torr, as in the embodimentIn the composite quantum well layer, the growth temperature is 795 ℃. The growth pressure of the composite quantum well layer is 200torr. Each sub-layer in the composite quantum well layer grows in a hydrogen-free environment, and the growth atmosphere N of the quantum well preparation layer and the InGaN quantum well sub-layer 2 /NH 3 The ratio was 2:3.
Optionally, the quantum barrier layer is an AlGaN layer, the growth temperature is 800-1000 ℃, the thickness is 1-50 nm, the growth pressure is 50-300 torr, and the Al component is 0.05-0.5. Specifically, in this embodiment, the quantum barrier layer is an AlGaN layer, the growth temperature is 870 ℃, the thickness is 10 nm, the growth pressure is 200torr, and the al component content is 0.1.
Step S07, depositing an electron blocking layer on the active layer.
Optionally, the growth temperature of the electron blocking layer is 900-1000 ℃, and the growth pressure is 100-300 torr. Specifically, in this embodiment, the growth temperature of the electron blocking layer is 965 ℃ and the growth pressure is 200torr.
And step S08, depositing a P-type GaN layer on the electron blocking layer.
Optionally, the growth temperature of the P-type GaN layer is 900-1050 ℃, and the growth pressure is 100-600 torr.
Specifically, the growth temperature of the P-type GaN layer is 985 ℃, the thickness is 15nm, the growth pressure is 200torr, and for an LED structure containing V-shaped pits, the higher growth temperature of the P-type GaN layer is favorable for combining the V-shaped pits, so that the LED epitaxial wafer with a smooth surface is obtained.
Example 2
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the thickness of the N-type InGaN quantum well preparation layer is 0.5 nm, the thickness of the in quantum dot layer is 0.1nm, the thickness of the InGaN nanocluster layer is 0.5 nm, and the thickness of the InGaN quantum well sub-layer is 2.5 nm.
Example 3
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the thickness of the N-type InGaN quantum well preparation layer is 2 nm, the thickness of the in quantum dot layer is 1nm, the thickness of the InGaN nanocluster layer is 2 nm, and the thickness of the InGaN quantum well sub-layer is 5 nm.
Example 4
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the InGaN quantum well sub-layer has an In component concentration of 0.25, and the N-type InGaN quantum well preparation layer has a Si doping concentration of 1E+16 atoms/cm 3 。
Example 5
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the In component concentration of the N-type InGaN quantum well preparation layer is 0.07, the In component concentration of the InGaN quantum well sub-layer is 0.1, and the Si doping concentration of the N-type InGaN quantum well preparation layer is 1E+18 atoms/cm 3 。
Example 6
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the In composition concentration In the N-type InGaN quantum well preparation layer was 0.05.
Example 7
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the In composition concentration In the N-type InGaN quantum well preparation layer was 0.13.
Example 8
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the number of lamination cycles of the active layer was 5, and the In component concentration of the ingan quantum well sub-layer was 0.25.
Example 9
The light emitting diode epitaxial wafer in this embodiment has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the number of lamination cycles of the active layer was 15.
Comparative example
The light emitting diode epitaxial wafer in this comparative example has substantially the same structure as the light emitting diode epitaxial wafer in embodiment 1, except that:
the active layer includes InGaN quantum well layers and quantum barrier layers, which are periodically and alternately stacked, the thickness of the InGaN quantum well layers being 3.5nm, and the structure of the quantum barrier layers being the same as in example 1.
The products of examples 1 through 9, and the comparative example were prepared as 10mil by 24 mil chips using the same chip process conditions, and the resulting chips of each example were each extracted 300 LED chips and tested at 120 mA/60 mA current, and the light efficiency improvement over conventional chips was measured as shown in table 1. As can be clearly seen by combining the data in table 1, the technical schemes in examples 1 to 9 can significantly improve the light efficiency, and compared with the conventional chip, the embodiment of the invention can improve the light efficiency by 0.5% -5%, and other items have good electrical properties, while the comparison example has no light effect improvement compared with the conventional chip.
TABLE 1
Through the design of the structure of the active layer In the embodiment of the invention, the light-emitting diode can reduce In aggregation, improve the crystal quality of the quantum well layer and the quantum well radiation recombination efficiency, and improve the light-emitting efficiency of the light-emitting diode.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A light emitting diode epitaxial wafer, comprising: the semiconductor device comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked, wherein the active layer comprises a composite quantum well layer and a quantum barrier layer which are periodically and alternately stacked, and the composite quantum well layer comprises an N-type InGaN quantum well preparation layer, an In quantum dot layer deposited on the N-type InGaN quantum well preparation layer, an InGananocluster layer deposited on the In quantum dot layer and an InGaN quantum well sub-layer deposited on the InGananocluster layer.
2. The light emitting diode epitaxial wafer of claim 1, wherein the N-type InGaN quantum well preparation layer has a thickness of 0.5 nm-5 nm, the In quantum dot layer has a thickness of 0.1 nm-1 nm, the InGaN nanocluster layer has a thickness of 0.2 nm-2 nm, and the InGaN quantum well sub-layer has a thickness of 1 nm-10 nm.
3. The light emitting diode epitaxial wafer of claim 1, wherein an In composition of the N-type InGaN quantum well preparation layer is lower than an In composition of the InGaN quantum well sub-layer.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the InGaN quantum well sub-layer has an In composition of 0.01-0.5.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the N-type InGaN quantum wellThe Si doping concentration in the preparation layer is 1E+16~1E+18 atoms/cm 3 。
6. The light emitting diode epitaxial wafer of claim 1, wherein the first semiconductor layer comprises a buffer layer, an undoped GaN layer, and an N-type GaN layer sequentially deposited on the substrate, and the second semiconductor layer comprises an electron blocking layer and a P-type GaN layer sequentially deposited on the active layer.
7. The preparation method of the light-emitting diode epitaxial wafer is characterized by comprising the following steps of:
providing a substrate;
depositing a buffer layer on the substrate;
pretreating the substrate deposited with the buffer layer;
depositing an undoped GaN layer on the buffer layer;
depositing an N-type GaN layer on the undoped GaN layer;
depositing an active layer on the N-type GaN layer;
depositing an electron blocking layer on the active layer;
depositing a P-type GaN layer on the electron blocking layer;
the active layer comprises a composite quantum well layer and a quantum barrier layer which are periodically and alternately stacked, wherein the composite quantum well layer comprises an N-type InGaN quantum well preparation layer, an In quantum dot layer deposited on the N-type InGaN quantum well preparation layer, an InGananocluster layer deposited on the In quantum dot layer, and an InGaN quantum well sub-layer deposited on the InGananocluster layer.
8. The method of manufacturing a light emitting diode epitaxial wafer of claim 7, wherein the step of growing the composite quantum well layer comprises:
turn on N 2 And NH 3 At N 2 And NH 3 Introducing TEGa, TMIn and SiH into the mixed atmosphere of (a) 4 Depositing an N-type InGaN quantum well preparation layer;
shut off NH 3 And stopIntroducing TEGa and SiH 4 Keep N 2 Opening and TMIn introducing, and depositing an In quantum dot layer;
keep N 2 Opening, introducing TMIn and TEGa, and depositing an InGananocluster layer;
turn on N 2 And NH 3 TMIn and TEGa are kept in, and InGaN quantum well sublayers are deposited.
9. The method for preparing a light-emitting diode epitaxial wafer according to claim 8, wherein the growth temperature of the composite quantum well layer is 700-1000 ℃, and the growth pressure is 50-300 torr, and N 2 And NH 3 N in the mixed atmosphere of (2) 2 And NH 3 The ratio of (2) is 10:1-1:10.
10. An LED chip comprising the light emitting diode epitaxial wafer of any one of claims 1 to 6.
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