CN115458649A - Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode - Google Patents
Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode Download PDFInfo
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- 239000000463 material Substances 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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Abstract
The invention discloses a light emitting diode epitaxial wafer, a preparation method thereof and a light emitting diode, wherein the light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate; the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer. The method can relieve the segregation of In the quantum well layer, so that the distribution of In is more uniform, the uniformity of the light-emitting wavelength of the epitaxial wafer is improved, and the light-emitting efficiency of multiple quantum wells is improved.
Description
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a light emitting diode epitaxial wafer, a preparation method of the light emitting diode epitaxial wafer and a light emitting diode.
Background
At present, gaN-based light emitting diodes have been widely applied to the solid state lighting field and the display field, and attract more and more people to pay attention. GaN-based leds have been produced industrially and have applications in backlights, lighting, landscape lamps, and the like.
The mqw layer is an active region, and is the most core structure of the light emitting diode, and has received much attention from researchers. Since the emission wavelength of the LED can be made to cover a wide wavelength range from near infrared to near ultraviolet by adjusting the In content of the InGaN well layer, the uniformity of the distribution of the In component has a crucial influence on the uniformity of the emission wavelength.
However, because the InN thermal stability of the quantum well layer In the superlattice structure of the InGaN quantum well layer and the GaN quantum barrier layer of the traditional multilayer quantum well is low, an InN vacancy which is decomposed by heating is easily caused, so that the segregation and enrichment phenomena of In the InGaN layer are intensified, and the stress among heterojunction materials In the superlattice structure of the InGaN layer and the GaN layer In the multilayer quantum well is uneven, so that the problems of poor wavelength uniformity, low luminous efficiency and the like are caused. Moreover, due to the fact that serious lattice mismatch exists between the GaN quantum barrier layer and the InGaN quantum well layer heterogeneous material, the stress of a quantum well region is increased, defects are increased, in segregation is aggravated, and the problems of poor wavelength uniformity, low light emitting efficiency and the like can be caused. This phenomenon is more serious especially In long-wavelength-band leds with a high In content, such as green and yellow light.
Disclosure of Invention
The invention aims to provide a light emitting diode epitaxial wafer, which can relieve In segregation In a quantum well layer, enables In distribution to be more uniform, improves the uniformity of light emitting wavelength of the epitaxial wafer, and also improves the light emitting efficiency of multiple quantum wells.
The technical problem to be solved by the invention is to provide a method for preparing a light-emitting diode epitaxial wafer, which has a simple process and can stably prepare the light-emitting diode epitaxial wafer with uniform light-emitting wavelength and good light-emitting efficiency.
In order to solve the technical problem, the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
In one embodiment, the In adjustment layer includes an Al layer, al, and a metal layer sequentially stacked x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z And the N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.
In one embodiment, the Al layer has a thickness of about 0.1nm to about 1nm;
the Al is x N 1-x The thickness of the three-dimensional layer is about 0.5nm-2nm;
said In y N 1-y The thickness of the three-dimensional layer is about 0.5nm-2nm;
said In z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.
In one embodiment, the In adjustment layer has a thickness of 1.5nm to 7nm;
the thickness of the quantum well layer is 2nm-5nm;
the thickness of the quantum barrier layer is 3nm-15nm;
the repeated lamination period of the In regulating layer, the quantum well layer and the quantum barrier layer is 3-15.
In one embodiment, the buffer layer has a thickness of 20nm to 100nm;
the thickness of the intrinsic GaN layer is 300nm-800nm;
the thickness of the N-type GaN layer is 1-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of the Si is 5 x 10 18 -1×10 19 cm -3 ；
The thickness of the P-type GaN layer is 200nm-300nm, the P-type GaN layer is Mg doped, and the doping concentration of Mg is 5 multiplied by 10 17 -1×10 20 cm -3 。
In one embodiment, the electron blocking layer includes Al stacked alternately a Ga 1-a N layer and In b Ga 1-b N layers, wherein the stacking period number is 3-15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;
the Al is a Ga 1-a The thickness of the N layer is 5nm-7nm;
said In b Ga 1-b The thickness of the N layer is 5nm-7nm;
the thickness of the electron blocking layer is 20nm-50nm.
In order to solve the above problems, the present invention further provides a method for preparing an led epitaxial wafer, comprising the following steps:
preparing a substrate;
depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate in sequence;
the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
In one embodiment, the deposition of the In tuning layer is accomplished using the following method:
depositing Al layer and Al in sequence x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z The N buffer layer forms the In adjusting layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.
In one embodiment, the deposition of the Al layer is accomplished using the following method:
controlling the temperature of the reaction chamber at 800-900 ℃, and introducing TMAl as an Al source to finish deposition;
and/or, the following method is adopted to complete the methodAl x N 1-x Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMAl as an Al source, and introducing NH 3 As N source, completing deposition;
and/or, completing the In by the following method y N 1-y Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMIn as an In source, and introducing NH 3 As an N source, completing the deposition;
and/or, completing the In by the following method z Ga 1-z And (3) deposition of N:
controlling the temperature of the reaction chamber at 800-900 ℃, introducing TMIn as an In source, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
In one embodiment, the deposition of the multiple quantum well layer is accomplished using the following method:
an In regulating layer, a quantum well layer and a quantum barrier layer are repeatedly laminated on the N-type GaN layer In sequence, wherein the repeated lamination period is 3-15;
wherein the deposition of the quantum well layer is accomplished using:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMIn as an In source, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
And/or, completing the deposition of the quantum barrier layer by adopting the following method:
controlling the temperature of the reaction chamber to be 800-900 ℃, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
In one embodiment, depositing the buffer layer on the front side of the substrate is accomplished using the following method:
controlling the temperature of the reaction chamber at 500-700 ℃, introducing TMAl as an Al source, and introducing NH 3 As an N source, finishing the deposition of a buffer layer on the front surface of the substrate;
and/or, depositing the intrinsic GaN layer on the buffer layer is accomplished using the following method:
the reaction was cooled to room temperatureThe temperature is controlled between 1100 ℃ and 1150 ℃, NH is introduced 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the intrinsic GaN layer on the buffer layer;
and/or, depositing the N-type GaN layer on the intrinsic GaN layer is completed by the following method:
controlling the temperature of the reaction chamber at 1100-1150 ℃, and introducing SiN 4 As a source of Si, NH was introduced 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the N-type GaN layer on the intrinsic GaN layer;
and/or, depositing the P-type GaN layer on the electron blocking layer is completed by adopting the following method:
controlling the temperature of the reaction chamber at 800-1000 ℃, and introducing NH 3 Introducing TMGa as Ga source and CP as N source 2 And Mg is used as a Mg source to finish the deposition of the P-type GaN layer on the electron blocking layer.
In one embodiment, depositing the electron blocking layer on the multiple quantum well layer is accomplished using the following method:
alternately depositing Al on the MQW layer a Ga 1-a N layer and In b Ga 1-b N layers, wherein the number of the stacked layers is 3-15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;
wherein said Al is a Ga 1-a The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber at 900-1000 ℃, introducing TMAL as an Al source and NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
said In b Ga 1-b The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber at 900-1000 ℃, introducing TMIn as an In source and NH 3 And (4) introducing TMGa as an N source to finish deposition.
Correspondingly, the invention further provides a light-emitting diode which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
according to the light emitting diode epitaxial wafer provided by the invention, the multiple quantum well layer comprises the In adjusting layer, the quantum well layer and the quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer. The In component adjusting layer slows down the stress of the quantum well layer and reduces the lattice mismatch between the quantum barrier layer and the quantum well layer, so that excessive defects are prevented from being generated to become an 'In cluster' center. And the distribution of In components In the quantum well layer is effectively adjusted, the segregation of In the quantum well is relieved, the distribution is more uniform, the uniformity of the light-emitting wavelength of the epitaxial wafer is improved, and the light-emitting efficiency of the multiple quantum wells is improved.
Drawings
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode provided by the present invention, wherein a substrate is 1, a buffer layer is 2, an intrinsic GaN layer is 3, an N-type GaN layer is 4, a multi-quantum well layer is 5, an electron blocking layer is 6, and a P-type GaN layer is 7.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below.
Unless otherwise stated or contradicted, terms or phrases used herein have the following meanings:
in the present invention, the terms "combination thereof", "any combination thereof", and the like used herein include all suitable combinations of any two or more of the listed items.
In the present invention, "preferred" is only an embodiment or an example for better description, and it should be understood that the scope of the present invention is not limited thereto.
In the present invention, the technical features described in the open type include a closed technical solution composed of the listed features, and also include an open technical solution including the listed features.
In the present invention, the numerical range is defined to include both endpoints of the numerical range unless otherwise specified.
The traditional multilayer quantum well InGaN quantum well layer and GaN quantum barrier layer superlattice structures have serious In segregation, and due to well barrier lattice mismatch, the quantum well layer has large stress and poor lattice quality, and the wavelength uniformity and the light emitting efficiency are influenced.
In order to solve the above problems, the present invention provides an led epitaxial wafer, as shown in fig. 1, including a substrate 1, and a buffer layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a multi-quantum well layer 5, an electron blocking layer 6, and a P-type GaN layer 7 sequentially stacked on the substrate 1;
the multiple quantum well layer 5 comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
According to the light emitting diode epitaxial wafer provided by the invention, the multiple quantum well layer comprises the In adjusting layer, the quantum well layer and the quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer. The In component adjusting layer slows down the stress of the quantum well layer and reduces the lattice mismatch between the quantum barrier layer and the quantum well layer, so that excessive defects are prevented from being generated to become an 'In cluster' center. And the distribution of In components In the quantum well layer is effectively adjusted, the segregation of In the quantum well is relieved, the distribution is more uniform, the uniformity of the light-emitting wavelength of the epitaxial wafer is improved, and the light-emitting efficiency of the multiple quantum wells is improved.
The multiple quantum well layer is a core structure of light emitting of the light emitting diode. In one embodiment, the In adjustment layer has a thickness of 1.5nm to 7nm; the thickness of the quantum well layer is 2nm-5nm; the thickness of the quantum barrier layer is 3nm-15nm; the repeated lamination period of the In regulating layer, the quantum well layer and the quantum barrier layer is 3-15.
In one embodiment, the In adjustment layer includes an Al layer, al, and a metal layer sequentially stacked x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z And the N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1. In one embodiment, the Al layer has a thickness of about 0.1nm to about 1nm; the Al is x N 1-x The thickness of the three-dimensional layer is about 0.5nm-2nm; said In y N 1-y The thickness of the three-dimensional layer is about 0.5nm-2nm; said In z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.
It should be noted that, in the present invention, the Al layer is adsorbed thinly on the surface of the epitaxial layer; the Al is x N 1-x The three-dimensional layer grows into island shapes which are uniformly distributed on the surface of the epitaxial layer; said In y N 1-y The three-dimensional layer preferentially adsorbs the uniformly distributed Al x N 1-x On the island, the three-dimensional island continues to grow up, and In is formed at this time y N 1-y The distribution of In atoms In the three-dimensional layer is very uniform; said In z Ga 1-z In atoms In the N buffer layer are also preferentially adsorbed In y N 1-y On the island, in at the same time z Ga 1-z N gradually filling In y N 1-y Three-dimensional layer, the distribution of In atoms is also more even. In one aspect, the In z Ga 1-z The N buffer layer also serves as a preparation layer for the growth of the quantum well layer, the lattice mismatch between the N buffer layer and the quantum well layer is small, the stress of the multiple quantum well layer can be relieved, the lattice mismatch during the growth of the quantum barrier layer and the quantum well layer is reduced, excessive defects are prevented from being generated to form In cluster centers, and on the other hand, in atoms are uniformly distributed and have low In components z Ga 1-z And a quantum well layer is grown on the N buffer layer, in atoms of the quantum well layer are easier to adsorb and grow on the In component uniformly distributed on the In component adjusting layer, and therefore the distribution of In the grown quantum well layer is more uniform.
In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. The buffer layer is mainly used for providing crystal seeds, relieving lattice mismatch of the substrate and the epitaxial layer and improving the lattice quality of the epitaxial wafer. In one embodiment, the buffer layer has a thickness of 20nm to 100nm.
The intrinsic GaN layer is an undoped GaN layer, and in one embodiment, the intrinsic GaN layer has a thickness of 300nm to 800nm.
The N-type GaN layer mainly provides electrons, and in one embodiment, the thickness of the N-type GaN layer is 1-3 μm, and the N-type GaN layer isDoping Si with the doping concentration of 5 x 10 18 -1×10 19 cm -3 (ii) a The P-type GaN layer mainly provides holes, and in one embodiment, the thickness of the P-type GaN layer is 200nm-300nm, the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5 x 10 17 -1×10 20 cm -3 。
The electron blocking layer is mainly used for blocking electrons and preventing the electrons from overflowing, and in one embodiment, the electron blocking layer comprises Al which is alternately stacked a Ga 1-a N layer and In b Ga 1-b N layers, wherein the stacking period number is 3-15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;
the Al is a Ga 1-a The thickness of the N layer is 5nm-7nm;
said In b Ga 1-b The thickness of the N layer is 5nm-7nm;
the thickness of the electron blocking layer is 20nm-50nm.
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s1, preparing a substrate;
in one embodiment, the substrate is a sapphire substrate. Then, the temperature of the reaction chamber is controlled to be 1000 ℃ to 1200 ℃, the pressure of the reaction chamber is controlled to be 200Torr to 600Torr, and the reaction temperature is controlled to be H 2 And carrying out high-temperature annealing on the substrate for 5-8 min under the atmosphere, and cleaning particles and oxides on the surface of the substrate.
S2, sequentially depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate;
the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
In one embodiment, the step S2 comprises the steps of:
s21, depositing the buffer layer on the front surface of the substrate by adopting the following method:
at one endIn one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer is an AlN buffer layer, and the AlN buffer layer is prepared by the following method: controlling the temperature of the reaction chamber at 500-700 ℃, introducing TMAl as an Al source and NH 3 And as an N source, finishing the deposition of a buffer layer on the front surface of the substrate.
S22, depositing the intrinsic GaN layer on the buffer layer by adopting the following method:
controlling the temperature of the reaction chamber at 1100-1150 ℃, and introducing NH 3 And (3) introducing TMGa as an N source to finish the deposition of the intrinsic GaN layer on the buffer layer.
S23, depositing the N-type GaN layer on the intrinsic GaN layer by adopting the following method:
controlling the temperature of the reaction chamber at 1100-1150 ℃, and introducing SiN 4 As a source of Si, NH is introduced 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the N-type GaN layer on the insertion layer;
s24, depositing the multi-quantum well layer on the N-type GaN layer by adopting the following method:
an In regulating layer, a quantum well layer and a quantum barrier layer are repeatedly laminated on the N-type GaN layer In sequence, wherein the repeated lamination period is 3-15;
wherein the deposition of the quantum well layer is accomplished using:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMIn as an In source, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
And/or, completing the deposition of the quantum barrier layer by adopting the following method:
controlling the temperature of the reaction chamber to be 800-900 ℃, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
In one embodiment, the deposition of the In adjustment layer is accomplished using the following method:
depositing an Al layer and Al in sequence x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z Formation of N buffer layerIn the In regulating layer, the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.
Preferably, the deposition of the Al layer is accomplished using the following method:
controlling the temperature of the reaction chamber at 800-900 ℃, and introducing TMAl as an Al source to finish deposition;
and/or, the Al is completed by the following method x N 1-x Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMAl as an Al source, and introducing NH 3 As an N source, completing the deposition;
and/or, completing the In by the following method y N 1-y Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMIn as an In source, and introducing NH 3 As an N source, completing the deposition;
and/or, completing the In by the following method z Ga 1-z And (3) deposition of N:
controlling the temperature of the reaction chamber at 800-900 ℃, introducing TMIn as an In source, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
It is noted that the In adjusting layer of the invention firstly deposits the Al layer, and the Al atom is temporarily adsorbed on the surface of the epitaxial layer because the introduction time of the Al atom is short In the process; then growing the Al x N 1-x Three-dimensional layer, introducing Al source and NH into the reaction chamber 3 。NH 3 Reacts with Al atoms on the Al layer to generate AlN nucleation points, and continuously absorbs AlN in the atmosphere to grow into small islands. The Al thus grown x N 1-x And in the three-dimensional layer, alN islands are uniformly distributed and have strong size consistency. Then in said Al x N 1-x Growing In on the three-dimensional layer y N 1-y And after an In source and an N source are introduced into the three-dimensional layer, inN is preferentially adsorbed on the ALN small islands which are uniformly distributed, the three-dimensional small islands continue to grow, and the In atoms of the formed InN layer are uniformly distributed. Finally, the In is grown z Ga 1-z And an N buffer layer. When InGaN material grows, in atoms are also more compatibleThe indium tin oxide is easy to adsorb and grow on InN small islands, and when InGaN is used for gradually filling up a three-dimensional layer, the distribution of In atoms is more uniform. In one aspect, the In z Ga 1-z The N buffer layer is a preparation layer for the growth of the quantum well layer, the lattice mismatch with the InGaN quantum well layer is small, the stress of the multiple quantum well layer can be relieved, the lattice mismatch during the growth of the quantum barrier layer and the quantum well layer is reduced, and the phenomenon that excessive defects are generated to form an 'In cluster' center is avoided. On the other hand, in of a low In composition In which In atoms are uniformly distributed z Ga 1-z The InGaN quantum well layer is grown on the N buffer layer, in atoms of the quantum well layer are easier to adsorb and grow on the In composition which is uniformly distributed on the In composition adjusting layer, and therefore the distribution of In the grown quantum well layer is more uniform.
In addition, the growth temperature of the Al layer is 800-900 ℃, and the Al layer is made of Al x N 1-x The growth temperature of the three-dimensional layer is 700-800 ℃, and In is y N 1-y The growth temperature of the three-dimensional layer is 700-800 ℃, and In is z Ga 1-z The growth temperature of the N buffer layer is 800-900 ℃; the Al is x N 1-x Three-dimensional layer and said In y N 1-y The growth temperature of the three-dimensional layer is relatively low, and the low temperature is favorable for three-dimensional growth. The temperature of the Al layer is relatively high, so that the migration of Al atoms on the surface of the epitaxial wafer is mainly facilitated, and the distribution of the Al atoms is more uniform. Said In z Ga 1-z The relatively high temperature of the N buffer layer is for the epitaxial layer surface to be more smooth, the lattice quality is good, and the formation defect is less.
S25, depositing the electron barrier layer on the multi-quantum well layer by adopting the following method:
alternately depositing Al on the MQW layer a Ga 1-a N layer and In b Ga 1-b N layers, the number of the stacked layers is 3-15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;
wherein said Al is a Ga 1-a The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber at 900-1000 ℃, introducing TMAL as an Al source and NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
said In b Ga 1-b The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber to 900-1000 ℃, introducing TMIn as an In source and NH 3 And (4) as an N source, introducing TMGa as a Ga source, and finishing the deposition.
S26, depositing the P-type GaN layer on the electron blocking layer by adopting the following method:
controlling the temperature of the reaction chamber at 800-1000 ℃, and introducing NH 3 Introducing TMGa as Ga source and CP as N source 2 And Mg is used as a Mg source to finish the deposition of the P-type GaN layer on the electron blocking layer.
Correspondingly, the invention also provides a light-emitting diode which comprises the light-emitting diode epitaxial wafer.
The deposition process is completed by using MOCVD equipment or PVD equipment, and the deposition method is not limited in the invention. The Al source, N source, ga source, si source, mg source, sc source, and In source are exemplary ones, and are not limited to the above.
The invention is further illustrated by the following specific examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially laminated on the substrate;
the multi-quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multi-quantum well layer;
the In regulating layer comprises an Al layer and Al which are sequentially laminated x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z And an N buffer layer, wherein x is 0.07, y is 0.15, z is 0.07, and a repeated lamination period of the In adjusting layer, the quantum well layer and the quantum barrier layer is 10.
The preparation method of the light-emitting diode epitaxial wafer comprises the following steps:
s1, preparing a substrate; the substrate is a sapphire substrate.
S2, a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer;
specifically, S2 includes the steps of:
s21, depositing the buffer layer on the front surface of the substrate by adopting the following method:
controlling the temperature of the reaction chamber at 600 ℃, introducing TMAl as an Al source, and introducing NH 3 And as an N source, depositing a buffer layer on the front surface of the substrate, completing the deposition and controlling the thickness of the deposited buffer layer to be 30nm.
S22, depositing the intrinsic GaN layer on the buffer layer by adopting the following method:
the temperature of the reaction chamber is controlled at 1150 ℃, NH is introduced 3 As an N source, introducing TMGa as a Ga source to finish deposition and control the deposition thickness to be 400nm;
s23, depositing the N-type GaN layer on the intrinsic GaN layer by adopting the following method:
the temperature of the reaction chamber is controlled at 1050 ℃, and SiN is introduced into the reaction chamber 4 As a source of Si, NH was introduced 3 As N source, introducing TMGa as Ga source, completing deposition and controlling the deposition thickness to be 2 μm, and the doping concentration of Si to be 1 x 10 19 cm -3 ；
S24, depositing the multi-quantum well layer on the N-type GaN layer by adopting the following method:
an In regulating layer, a quantum well layer and a quantum barrier layer are repeatedly laminated on the N-type GaN layer In sequence, wherein the repeated lamination period is 10;
wherein the deposition of the In adjustment layer is accomplished using the following method:
depositing an Al layer and Al in sequence x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z The N buffer layer formed the In adjustment layer, wherein x was 0.07, y was 0.15, and z was 0.07.
The deposition of the Al layer was accomplished using the following method:
controlling the temperature of the reaction chamber at 850 ℃, introducing TMAl as an Al source, finishing deposition and controlling the deposition thickness to be 0.5nm;
the Al is completed by the following method x N 1-x Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 750 ℃, introducing TMAl as an Al source, and introducing NH 3 As an N source, completing deposition and controlling the deposition thickness to be 1nm;
the In was accomplished by the following method y N 1-y Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 750 ℃, introducing TMIn as an In source, and introducing NH 3 As an N source, completing deposition and controlling the deposition thickness to be 1nm;
the In was accomplished by the following method z Ga 1-z And N deposition:
controlling the temperature of the reaction chamber at 850 ℃, introducing TMIn as an In source, and introducing NH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the deposition thickness to be 1nm.
Then, the deposition of the quantum well layer was completed using the following method:
controlling the temperature of the reaction chamber at 750 ℃, introducing TMIn as an In source, and introducing NH 3 As N source, TMGa is introduced as Ga source to complete deposition and control the deposition thickness to be 3 nm.
The deposition of the quantum barrier layer is completed by adopting the following method:
controlling the temperature of the reaction chamber at 850 ℃, and introducing NH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the deposition thickness to be 10nm.
S25, depositing the electron barrier layer on the multi-quantum well layer by adopting the following method:
alternately depositing Al on the MQW layer a Ga 1-a N layer and In b Ga 1-b N layers, the number of the stacked layers is 3-15, the value range of a is 0.1, and the value range of b is 0.3;
wherein said Al is a Ga 1-a The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber at 950 ℃, introducing TMAL as an Al source, and introducingNH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the deposition thickness to be 6nm. (ii) a
Said In b Ga 1-b The deposition step of the N layer comprises the following steps:
controlling the temperature of the reaction chamber at 950 ℃, introducing TMIn as an In source and NH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the deposition thickness to be 6nm. .
S26, depositing the P-type GaN layer on the electron blocking layer by adopting the following method:
controlling the temperature of the reaction chamber at 850 ℃, introducing Mg source as a doping source, and introducing NH 3 As an N source, introducing TMGa as a Ga source, finishing deposition, controlling the deposition thickness to be 4nm and the Mg doping concentration to be 5 x 10 19 cm -3 。
Example 2
The embodiment provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the multi-quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multi-quantum well layer;
the In regulating layer comprises an Al layer and Al which are sequentially laminated x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z And an N buffer layer, wherein x is 0.07, y is 0.2, z is 0.07, and a repeated lamination period of the In adjusting layer, the quantum well layer and the quantum barrier layer is 15.
The method for preparing the epitaxial wafer of the light emitting diode is as in example 1.
Comparative example 1
The comparative example provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the multi-quantum well layer comprises a quantum well layer and a quantum barrier layer, and the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multi-quantum well layer;
the above-described method for fabricating an epitaxial wafer for a light emitting diode is referred to example 1, and at the same time, the multiple quantum well layer is controlled so that the emission wavelength is the same as example 1.
Comparative example 2
The comparative example provides an epitaxial wafer of a light-emitting diode, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially laminated on the substrate;
the multiple quantum well layer comprises a quantum well layer and a quantum barrier layer, and the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer;
the above-described method for fabricating an epitaxial wafer for a light emitting diode is referred to example 1, and at the same time, the multiple quantum well layer is controlled so that the emission wavelength is the same as example 2.
Chips were fabricated by using the light emitting diode epitaxial wafers obtained in examples 1 to 3 and comparative examples 1 to 2, wherein the epitaxial wafers obtained in example 1 and comparative example 1 were fabricated into 10 × 24mil chips and the luminance test current was 120mA, and the epitaxial wafers obtained in example 2 and comparative example 2 were fabricated into 5 × 7mil chips and the luminance test current was 6mA, and the results of the performance tests are shown in table 1.
Table 1 shows the results of the performance tests of the light emitting diode epitaxial wafers obtained in examples 1 to 2 and comparative examples 1 to 2
From the above results, it can be seen that, with the epitaxial structure added with the In component adjustment layer proposed by the present invention, since the In component distribution is more uniform, the wavelength uniformity is improved significantly, especially for long wavelength light emitting diodes with higher In component, the wavelength uniformity is improved to 0.3nm, and the light emitting luminance also shows great advantages.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially laminated on the substrate;
the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
2. The light emitting diode epitaxial wafer as claimed In claim 1, wherein the In adjustment layer comprises an Al layer, and an In adjustment layer sequentially stacked x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z And the N buffer layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.
3. The light emitting diode epitaxial wafer of claim 2, wherein the thickness of the Al layer is between about 0.1nm and 1nm;
the Al is x N 1-x The thickness of the three-dimensional layer is about 0.5nm-2nm;
said In y N 1-y The thickness of the three-dimensional layer is about 0.5nm-2nm;
said In z Ga 1-z The thickness of the N buffer layer is 0.5nm-2nm.
4. The light-emitting diode epitaxial wafer according to claim 1, wherein the In adjusting layer has a thickness of 1.5nm to 7nm;
the thickness of the quantum well layer is 2nm-5nm;
the thickness of the quantum barrier layer is 3nm-15nm;
the repeated lamination period of the In regulating layer, the quantum well layer and the quantum barrier layer is 3-15.
5. The light emitting diode epitaxial wafer of claim 1, wherein the buffer layer has a thickness of 20nm to 100nm;
the thickness of the intrinsic GaN layer is 300nm-800nm;
the thickness of the N-type GaN layer is 1-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of the Si is 5 x 10 18 -1×10 19 cm -3 ；
The thickness of the P-type GaN layer is 200nm-300nm, the P-type GaN layer is Mg doped, and the doping concentration of Mg is 5 multiplied by 10 17 -1×10 20 cm -3 。
6. The light emitting diode epitaxial wafer of claim 1, wherein the electron blocking layer comprises an alternating stack of Al a Ga 1-a N layer and In b Ga 1-b N layers, wherein the stacking period number is 3-15, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5;
the Al is a Ga 1-a The thickness of the N layer is 5nm-7nm;
said In b Ga 1-b The thickness of the N layer is 5nm-7nm;
the thickness of the electron blocking layer is 20nm-50nm.
7. A method for preparing a light-emitting diode epitaxial wafer according to any one of claims 1 to 6, characterized by comprising the following steps:
preparing a substrate;
depositing a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate in sequence;
the multiple quantum well layer comprises an In adjusting layer, a quantum well layer and a quantum barrier layer, and the In adjusting layer, the quantum well layer and the quantum barrier layer are sequentially and repeatedly laminated to form the multiple quantum well layer.
8. The method for preparing a light emitting diode epitaxial wafer according to claim 7, wherein the deposition of the In adjustment layer is performed by the following method:
depositing Al layer and Al in sequence x N 1-x Three-dimensional layer of In y N 1-y Three-dimensional layer and In z Ga 1-z The N buffer layer forms the In adjusting layer, wherein the value range of x is 0.05-0.1, the value range of y is 0.1-0.2, and the value range of z is 0.05-0.1.
9. The method for preparing an epitaxial wafer for light-emitting diodes according to claim 8, wherein the deposition of the Al layer is carried out by:
controlling the temperature of the reaction chamber at 800-900 ℃, and introducing TMAl as an Al source to finish deposition;
and/or, the Al is completed by the following method x N 1-x Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMAl as an Al source, and introducing NH 3 As N source, completing deposition;
and/or, completing the In by the following method y N 1-y Deposition of three-dimensional layers:
controlling the temperature of the reaction chamber at 700-800 ℃, introducing TMIn as an In source, and introducing NH 3 As N source, completing deposition;
and/or, completing the In by the following method z Ga 1-z And N deposition:
controlling the temperature of the reaction chamber at 800-900 ℃, introducing TMIn as an In source, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
10. A light emitting diode comprising the light emitting diode epitaxial wafer as claimed in any one of claims 1 to 6.
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| CN116072780A (en) * | 2023-03-09 | 2023-05-05 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
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| CN116072780A (en) * | 2023-03-09 | 2023-05-05 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
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