CN116314513A - Light-emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light-emitting diode epitaxial wafer and preparation method thereof Download PDF

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CN116314513A
CN116314513A CN202310559032.4A CN202310559032A CN116314513A CN 116314513 A CN116314513 A CN 116314513A CN 202310559032 A CN202310559032 A CN 202310559032A CN 116314513 A CN116314513 A CN 116314513A
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electron
sub
epitaxial wafer
forbidden bandwidth
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张彩霞
印从飞
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a light-emitting diode epitaxial wafer and a preparation method thereof, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guide layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer are sequentially arranged on the substrate along the epitaxial direction; the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction; the forbidden bandwidth of the second electron interception layer is larger than the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer. The epitaxial wafer disclosed by the invention has uniform light-emitting wavelength and light-emitting brightness distribution and good antistatic capability.

Description

Light-emitting diode epitaxial wafer and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
Currently, gaN-based light emitting diodes have been widely used in the field of solid state lighting as well as in the field of display, attracting more and more attention. The GaN-based light emitting diode has been industrially produced and has been used in backlight, illumination, landscape lamp, and the like.
The conventional GaN-based light emitting diode epitaxial wafer includes: the substrate, and the nucleation layer, the intrinsic GaN layer, the N-type semiconductor layer, the multiple quantum well layer, the electron blocking layer and the P-type semiconductor layer which are sequentially grown on the substrate, have the defects that the electron mobility is far larger than that of holes, so that the electron expansion capability is poor, carriers cannot be well expanded in the multiple quantum well region, the light emitting wavelength and the brightness uniformity are poor, the carrier expansion is poor, and the antistatic capability of the light emitting diode is poor.
Disclosure of Invention
The invention aims at providing a light-emitting diode epitaxial wafer with uniform light-emitting wavelength and light-emitting brightness distribution and good antistatic capability and a preparation method thereof.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the invention provides a light-emitting diode epitaxial wafer, which comprises a substrate, wherein a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guide layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer are sequentially arranged on the substrate along the epitaxial direction;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer.
In some embodiments, the first electron storage layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are periodically stacked, the third sub-layer having a forbidden band width Eg 3 Forbidden bandwidth Eg of > second sub-layer 2 Forbidden band width Eg of > first sublayer 1 And Eg 3 /Eg 1 More than 3, the forbidden bandwidth of the second electron blocking layer is more than 1.5 xEg 3 。
In some embodiments, the first electron storage layer is In x N 1-x /In y Ga 1-y An N/GaN layer, wherein the second electron interception layer is B m Ga 1-m N/B n N 1-n A third electron expansion layer of In a Ga 1-a N/N type B b Ga 1-b And N layers.
In some embodiments, 0.6. Gtoreq.x. Gtoreq. 0.4,0.3. Gtoreq.y. Gtoreq.0.1 in the first electron storage layer.
In some embodiments, the first electron storage layer comprises periodically stacked In x N 1-x Sublayer, in y Ga 1-y N sub-layer and GaN sub-layer, wherein, single In x N 1-x The thickness of the sub-layer is 1 nm-5 nm, and single In y Ga 1-y The thickness of the N sub-layer is 1 nm-5 nm, the thickness of a single GaN sub-layer is 6 nm-10 nm, the number of cycles of the first electron storage layer is 2-6, and the growth temperature is 800-900 ℃.
In some embodiments, in the second electron blocking layer, 0.3.gtoreq.m.gtoreq.0.1, 0.5.gtoreq.n.gtoreq.0.3.
In some embodiments, the second electron blocking layer comprises a periodically layered B m Ga 1-m N sub-layer and B n N 1-n A sublayer, wherein a single B m Ga 1-m The thickness of the N sub-layer is 6 nm-10 nm, and a single B n N 1-n The thickness of the sub-layer is 2 nm-5 nm, the number of cycles of the second electron interception layer is 2-6, and the growth temperature is 1000-1100 ℃.
In some embodiments, in the third electron expansion layer, 0.3. Gtoreq.a. Gtoreq.0.1, 0.3. Gtoreq.b. Gtoreq.0.1, and Si at a doping concentration of 1×10 16 cm -3 ~1×10 17 cm -3 。
In some embodiments, the third electron expansion layer comprises periodically stacked In a Ga 1-a N sub-layer and N type B b Ga 1-b N sublayers, wherein a single In a Ga 1-a The thickness of the N sub-layer is 1 nm-10 nm, and the single N type B b Ga 1-b The thickness of the N sub-layer is 10 nm-20 nm, and the third electron expansion layer growsThe temperature is 900-1000 ℃.
The invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guiding layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer on the substrate;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than the forbidden bandwidth of the third electron expansion layer, and the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer.
The invention has the beneficial effects that:
in the invention, an electron guiding layer is arranged between an N-type semiconductor layer and a multiple quantum well layer, and in the electron guiding layer, firstly, a first electron storage layer is arranged for storing electrons generated from the N-type semiconductor layer, secondly, a second electron interception layer with a forbidden bandwidth higher than that of the first electron storage layer is utilized to form an energy level barrier, the electrons are intercepted, the electron moving speed is forced to be slowed down, the mobility of the electrons crossing the second electron interception layer is greatly reduced, meanwhile, the electrons are further expanded through a third electron expansion layer with the forbidden bandwidth higher than that of the first electron storage layer and lower than that of the second electron interception layer, the electrons are guided through the combined action of the first electron storage layer, the second electron interception layer and the third electron expansion layer, the electron mobility is reduced, the electron expansion capacity of the multiple quantum well region is increased, the antistatic capacity is effectively improved, the light emitting wavelength and the light emitting brightness are distributed more uniformly, and the light emitting efficiency is higher.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to the present invention.
Fig. 2 is a schematic structural view of an electronic guiding layer according to the present invention.
Fig. 3 is a schematic structural diagram of a first electron storage layer according to the present invention.
Fig. 4 is a schematic structural diagram of a second electron blocking layer according to the present invention.
Fig. 5 is a schematic structural view of a third electron expansion layer according to the present invention.
Fig. 6 is a flowchart of a method for manufacturing a light emitting diode epitaxial wafer according to the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate 1, wherein a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electronic guiding layer 5, a multiple quantum well layer 6, an electronic blocking layer 7 and a P-type semiconductor layer 8 are sequentially arranged on the substrate 1 along the epitaxial direction;
the electron guiding layer 5 includes a first electron storage layer 51, a second electron blocking layer 52, and a third electron expansion layer 53 sequentially arranged in the epitaxial direction;
the second electron blocking layer 52 has a forbidden bandwidth > the third electron expansion layer 53 has a maximum forbidden bandwidth > the first electron storage layer 51.
In the present invention, an electron guiding layer 5 is disposed between an N-type semiconductor layer 4 and a multiple quantum well layer 6, and in the electron guiding layer 5, first, a first electron storage layer 51 is disposed for storing electrons generated from the N-type semiconductor layer 4, and second, an energy barrier is formed by using a second electron blocking layer 52 having a higher forbidden bandwidth than the first electron storage layer 51, so as to block electrons, thereby forcing the electron movement rate to be slow, and the electron expansion itself is reinforced due to the great decrease of the mobility across the second electron blocking layer 52, and meanwhile, the electrons are further expanded by a third electron expansion layer 53 having a higher maximum forbidden bandwidth than the first electron storage layer 51 and lower than the second electron blocking layer 52, thereby guiding the electrons by the combined action of the first electron storage layer 51, the second electron blocking layer 52 and the third electron expansion layer 53, so that the electron mobility is reduced, the electron expansion capability of the multiple quantum well region is increased, the antistatic capability is effectively improved, the light emission wavelength and the light emission luminance distribution are more uniform, and the light emission efficiency is higher.
The first electron storage layer 51 includes a first sub-layer, a second sub-layer and a third sub-layer, which are periodically stacked, and the forbidden bandwidth Eg of the third sub-layer 3 Forbidden bandwidth Eg of > second sub-layer 2 Forbidden band width Eg of > first sublayer 1 And Eg 3 /Eg 1 More than 3, the forbidden bandwidth of the second electron blocking layer 52 is more than 1.5 xEg 3 。
In the present invention, in the first electron storage layer 51, by providing the first sub-layer having a relatively reduced band gap and the third sub-layer having a band gap which is far higher than that of the first sub-layer, and providing the second sub-layer having a band gap which is interposed between the first sub-layer and the third sub-layer, a "band trap" is formed in the first electron storage layer 51, and electrons generated from the N-type semiconductor layer 4 are stored by the "band trap".
At the same time, the forbidden bandwidth of the second electron blocking layer 52 is far higher than that of the third sub-layer, so as to ensure that the forbidden bandwidth of the second electron blocking layer 52 is far higher than that of the first electron storage layer 51, thereby forming an energy level barrier, wherein Eg 3 /Eg 1 (forbidden band width Eg of third sublayer) 3 Forbidden band width Eg with the first sub-layer 1 Ratio between them) cannot be too low, eg 3 /Eg 1 Too low an extent is detrimental to the formation of "band traps" which make it difficult to store electrons, eg 3 /Eg 1 Too high an electron is difficult to cross the third sub-layer, and the ratio of the forbidden bandwidth of the second electron blocking layer 52 to the forbidden bandwidth of the third sub-layer should not be too low, otherwise, it is difficult for the second electron blocking layer 52 to form an energy barrier due to a sufficient forbidden bandwidth difference between the first electron storage layer 51 and the second electron blocking layer 52.
Referring to FIG. 2, the first electron storage layer 51 is In x N 1-x /In y Ga 1-y An N/GaN layer, a second electron blocking layer 52 of B m Ga 1-m N/B n N 1-n A third electron expansion layer 53 of In a Ga 1-a N/N type B b Ga 1-b And N layers.
In the present invention, the first electron storage layer 51 is In x N 1-x /In y Ga 1-y An N/GaN layer In which In x N 1-x Sub-layer 511 is the first sub-layer, in y Ga 1-y N sub-layer 512 is a second sub-layer, gaN sub-layer 513 is a third sub-layer, in x N 1-x The bandgap of the sub-layer 511 is about 0.7eV, and the bandgap of the gan sub-layer 513 is about 3.4eV, thereby forming "band traps" in the first electron storage layer 51, storing electrons generated from the N-type semiconductor layer 4.
In addition, in x N 1-x Sub-layer 511 and In y Ga 1-y The N sub-layer 512 introduces In component to reduce the barrier height, thereby forming a barrier difference with the GaN sub-layer 513, and In x N 1-x Sub-layer 511 and In y Ga 1-y The GaN sub-layer 513 is introduced after the N sub-layer 512, and In can be repaired during the growth process x N 1-x Sub-layer 511 and In y Ga 1-y The N sub-layer 512 is low temperature and is highly doped with defects generated by the In composition.
Second, in the second electron blocking layer 52, the band gap of the BN layer is about 6.4eV, which is far higher than that of the first electron storage layer 51, and the energy level of this layer is far higher than that of the first electron storage layer 51, forming an energy level barrier to forcibly slow down the electron movement rate, and at the same time, since the boron atoms are small, B m Ga 1-m N/B n N 1-n The atomic lattice matching is good, so that a high-quality lattice can be formed In this layer, and defects generated by the high-doped In component of the first electron storage layer 51 can be repaired.
The third electron expansion layer 53 is In a Ga 1-a N/N type B b Ga 1-b N layers, on the one hand, since the maximum forbidden bandwidth of this layer is higher than the first electron storage layer 51 and lower than the second electron interception layer 52, the energy level is between the first electron storage layer 51 and the second electron interception layer 52, the mobility across the second electron interception layer 52 is greatly reduced, the electron expansion is enhanced, and secondly, in a Ga 1-a N and N type B b Ga 1-b The lattice mismatch between N materials is serious, and the repeatedly laminated heterostructure generates two-dimensional electron gas, thereby increasing the expansion of carriersFor use, and B b Ga 1-b The incorporation of low N-type doping in the N material reduces the bulk resistance of the material, making the electron expansion better.
Therefore, through the common coordination of the first electron storage layer 51, the second electron interception layer 52 and the third electron expansion layer 53, electrons are guided, so that the electron mobility is reduced, the balance of electron hole pairs in the multiple quantum well regions is increased, the electron expansion capacity is increased, the antistatic capacity is further effectively improved, the light-emitting wavelength and the light-emitting brightness are distributed more uniformly, and the light-emitting efficiency is higher.
In the first electron storage layer 51, 0.6. Gtoreq.x.gtoreq. 0.4,0.3. Gtoreq.y.gtoreq.0.1, and x is exemplified by, but not limited to, 0.4, 0.5, or 0.6, when x is too large, lattice quality may be deteriorated due to too much In component, and when x is too small, that is, too little In component, it is difficult to form a barrier difference with the GaN sub-layer 513, and it is difficult to store enough electrons; illustratively, y is 0.1, 0.2 or 0.3, but not limited thereto, when y is too large, defects may increase due to a continuously high In composition, crystal quality may deteriorate, and when y is too small, electrons may not be efficiently stored.
Referring to fig. 3, wherein the first electron storage layer 51 includes In periodically stacked x N 1-x Sub-layer 511, in y Ga 1- y N sub-layer 512 and GaN sub-layer 513, wherein a single In x N 1-x The sub-layer 511 has a thickness of 1nm to 5nm, and is a single In y Ga 1-y The thickness of the N sub-layer 512 is 1 nm-5 nm, the thickness of the single GaN sub-layer 513 is 6 nm-10 nm, the number of cycles of the first electron storage layer 51 is 2-6, the growth temperature is 800-900 ℃, preferably, the thickness of the single GaN sub-layer 513 is 8 nm-10 nm, the GaN sub-layer 513 is thicker, and In repair is facilitated x N 1-x Sub-layer 511 and In y Ga 1-y The N sub-layer 512 has defects generated by high doping of the In component, and the growth temperature is, for example, 800 ℃, 830 ℃, 860 ℃ or 900 ℃, but is not limited thereto, and the growth temperature is not too high, and the too high growth temperature easily causes diffusion of the In component, and the growth temperature is not too low, and the too low growth temperature affects incorporation of the In component.
Wherein the secondIn the electron blocking layer 52, 0.3.gtoreq.m.gtoreq.0.1, 0.5.gtoreq.n.gtoreq.0.3, and exemplary, but not limited thereto, m is 0.1, 0.2 or 0.3, within this range, not only B can be ensured m Ga 1-m N sublayers 521 and B n N 1-n The sub-layer 522 has a good lattice match and ensures that no cracks are created; exemplary, n is 0.3, 0.4 or 0.5, but is not limited thereto, when n>At 0.5, cracks are liable to occur, resulting in a decrease in lattice quality, when n<At 0.3, the electron interception effect is reduced.
Referring to fig. 4, wherein the second electron blocking layer 52 comprises a periodically layered B m Ga 1-m N sublayer 521 and B n N 1-n Sub-layer 522, where a single B m Ga 1-m The N sub-layer 521 has a thickness of 6nm to 10nm, and is a single B n N 1-n The thickness of the sub-layer 522 is 2nm to 5nm, the number of cycles of the second electron blocking layer 52 is 2 to 6, the growth temperature is 1000 ℃ to 1100 ℃, and the growth temperature is 1000 ℃, 1030 ℃, 1080 ℃ or 1100 ℃ by way of example, but not limited thereto, the higher growth temperature is beneficial to improving the lattice quality and better repairing the defects caused by the high-In component of the first electron storage layer 51.
Wherein in the third electron extension layer 53, 0.3 is greater than or equal to 0.1, and the doping concentration of Si is 1×10 16 cm -3 ~1×10 17 cm -3 Exemplary, a is 0.1, 0.2 or 0.3, but not limited thereto, and when a is too large, the In composition is too large, so that the lattice quality is easily lowered, and when a is too small, the In composition is too small, so that it is difficult to form a barrier difference with the second electron blocking layer 52, and b is 0.1, 0.2 or 0.3, but not limited thereto, and when b is too large, it is easy to generate cracks, so that the lattice quality is lowered, and when b is too small, it is difficult to form a barrier difference with the first electron storage layer 51, and the doping concentration of Si is 1×10 16 cm -3 、3×10 16 cm -3 、5×10 16 cm -3 、8×10 16 cm -3 Or 1X 10 17 cm -3 But not limited thereto, by incorporation of low N-doped Si, the bulk resistance of the material is reduced, making the electron expansion better.
Referring to fig. 5, wherein the third electron expansion layer 53 comprises a periodIn of sexual stack a Ga 1-a N sub-layer 531 and N type B b Ga 1-b N sublayers, wherein a single In a Ga 1-a The thickness of the N sub-layer 531 is 1 nm-10 nm, and the single N type B b Ga 1-b The thickness of the N sub-layer is 10-20 nm, the growth temperature of the third electron expansion layer 53 is 900-1000 ℃, and preferably, a single N type B b Ga 1-b The thickness of the N sub-layer is 15-20 nm, and through the thickness setting and the growth temperature setting of each sub-layer, the incorporation of In components can be ensured, the better lattice quality can be ensured, the bottom layer defect is blocked, and the non-radiative recombination caused by the extension of the defect to the multi-quantum well layer 6 is avoided.
Wherein the nucleation layer 2 has a thickness of 20nm to 100nm, the intrinsic GaN layer 3 has a thickness of 300nm to 800nm, the N-type semiconductor layer 4 has a thickness of 1 μm to 3 μm, the multiple quantum well layer 6 has a thickness of 2nm to 5nm in a single period, the electron blocking layer 7 has a thickness of 20nm to 100nm in a single period, and the P-type semiconductor layer 8 has a thickness of 200nm to 300nm.
Referring to fig. 6, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate 1;
s200, sequentially depositing a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electronic guide layer 5, a multiple quantum well layer 6, an electronic barrier layer 7 and a P-type semiconductor layer 8 on a substrate 1;
the electron guiding layer 5 includes a first electron storage layer 51, a second electron blocking layer 52, and a third electron expansion layer 53 sequentially arranged in the epitaxial direction;
the forbidden bandwidth of the second electron blocking layer 52 > the forbidden bandwidth of the third electron expansion layer 53 > the forbidden bandwidth of the first electron storage layer 51.
In step S100, the substrate 1 may be a Si substrate, a sapphire substrate, or the like, but is not limited thereto, and the specific steps thereof are as follows:
controlling the temperature of the reaction chamber to be 1000-1200 ℃, controlling the pressure of the reaction chamber to be 200-600 Torr, and controlling the temperature of the reaction chamber to be H 2 And (3) carrying out high-temperature annealing for 5-8 min on the substrate 1 in the atmosphere, and cleaning particles and oxides on the surface of the substrate 1.
The specific steps of step S200 are as follows:
s210, depositing a nucleation layer 2 on a substrate 1:
the nucleation layer 2 can be an AlGaN layer or an AlN layer, and is mainly used for providing seed crystals, relieving lattice mismatch of the substrate 1 and the epitaxial layer and improving the lattice quality of the epitaxial wafer.
Controlling the temperature of the reaction chamber to be 500-700 ℃, controlling the pressure of the reaction chamber to be 200-400 Torr, and controlling the temperature of the reaction chamber to be N 2 And H 2 As carrier gas, NH is introduced 3 Providing an N source, introducing TMGa as a Ga source, and introducing TMAL as an Al source, wherein the thickness is 20-100 nm.
S220, depositing an intrinsic GaN layer 3 on the nucleation layer 2:
the temperature of the reaction chamber is controlled between 1100 ℃ and 1150 ℃ and the pressure is between 100Torr and 500Torr, N 2 And H 2 As carrier gas, NH is introduced 3 And (3) introducing TMGa as a Ga source as an N source, wherein the thickness is 300-800 nm.
S230, depositing an N-type semiconductor layer 4 on the intrinsic GaN layer 3:
the temperature of the reaction chamber is controlled between 1100 ℃ and 1150 ℃ and the pressure is between 100Torr and 500Torr, N 2 And H 2 As carrier gas, NH is introduced 3 As N source, TMGa is introduced as Ga source, siH is introduced 4 As an N-type dopant, the thickness is 1 μm to 3 μm.
S240, depositing an electronic guide layer 5 on the N-type semiconductor layer 4, wherein the specific steps are as follows:
s241 depositing a first electron storage layer 51 on the N-type semiconductor layer 4:
1) Deposition of In x N 1-x A sub-layer 511;
2) Deposition of In y Ga 1-y N sub-layer 512;
3) Depositing a GaN sub-layer 513;
wherein x is more than or equal to 0.6 and more than or equal to 0.4,0.3 and y is more than or equal to 0.1;
single In x N 1-x The sub-layer 511 has a thickness of 1nm to 5nm, and is a single In y Ga 1-y The N sub-layer 512 has a thickness of 1nm to 5nm, the single GaN sub-layer 513 has a thickness of 6nm to 10nm, the first electron storage layer 51 has 2 to 6 cycles, the growth temperature is 800 ℃ to 900 ℃, and the pressure is 100Torr to 300Torr.
S242 depositing a second electron blocking layer 52 on the first electron storage layer 51:
1) Deposit B m Ga 1-m N sub-layer 521;
2) Deposit B n N 1-n A sub-layer 522;
wherein, m is more than or equal to 0.3 and more than or equal to 0.1, n is more than or equal to 0.5 and more than or equal to 0.3;
single B m Ga 1-m The N sub-layer 521 has a thickness of 6nm to 10nm, and is a single B n N 1-n The thickness of the sub-layer 522 is 2nm to 5nm, the number of cycles of the second electron blocking layer 52 is 2 to 6, the growth temperature is 1000 ℃ to 1100 ℃, and the pressure is 100Torr to 300Torr.
S243. depositing a third electron expansion layer 53 on the second electron interception layer 52:
1) Deposition of In a Ga 1-a N sub-layer 531;
2) Depositing N type B b Ga 1-b An N sub-layer 532;
wherein 0.3 is more than or equal to a is more than or equal to 0.1,0.3 is more than or equal to b is more than or equal to 0.1, and the doping concentration of Si is 1 multiplied by 10 16 cm -3 ~1×10 17 cm -3 ；
Single In a Ga 1-a The thickness of the N sub-layer 531 is 1 nm-10 nm, and the single N type B b Ga 1-b The thickness of the N sub-layer is 10 nm-20 nm, the growth temperature of the third electron expansion layer 53 is 900-1000 ℃, the number of cycles is 2-6, and the pressure is 100 Torr-300 Torr.
S250. depositing a multiple quantum well layer 6 on the electron guiding layer 5:
the multi-quantum well layer 6 is an InGaN/GaN layer, the number of cycles is 3-15, the temperature of the reaction chamber is controlled to be 700-900 ℃, the pressure is 100-500 Torr, and the thickness of the multi-quantum well layer 6 in a single cycle is 2-5 nm.
S260, depositing an electron blocking layer 7 on the multiple quantum well layer 6:
the electron blocking layer 7 is an AlGaN/InGaN layer, the number of cycles is 3-15, the temperature of the reaction chamber is controlled to be 900-1000 ℃, the pressure is 100 Torr-500 Torr, the thickness of the electron blocking layer 7 In a single cycle is 20 nm-100 nm, wherein TMGa is used as a Ga source, TMAL is used as an Al source, and TMIn is used as an In source.
S270. depositing a P-type semiconductor layer 8 on the electron blocking layer 7:
the temperature of the reaction chamber is controlled to be 800-1000 ℃, the pressure is 100 Torr-300 Torr, and NH is introduced 3 As N source, TMGa as Ga source and CP 2 Mg as a P-type dopant, wherein the doping concentration of Mg is 5×10 17 ~1×10 20 cm -3 The thickness is 200 nm-300 nm.
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
example 1
Referring to fig. 1, the embodiment discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, wherein a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electronic guiding layer 5, a multiple quantum well layer 6, an electronic blocking layer 7 and a P-type semiconductor layer 8 are sequentially arranged on the substrate 1 along the epitaxial direction;
the electron guiding layer 5 includes a first electron storage layer 51, a second electron blocking layer 52, and a third electron expansion layer 53 sequentially arranged in the epitaxial direction;
the second electron blocking layer 52 has a forbidden bandwidth > the third electron expansion layer 53 has a maximum forbidden bandwidth > the first electron storage layer 51.
The first electron storage layer 51 includes a first sub-layer, a second sub-layer and a third sub-layer, which are periodically stacked, and the forbidden bandwidth Eg of the third sub-layer 3 Forbidden bandwidth Eg of > second sub-layer 2 Forbidden band width Eg of > first sublayer 1 And Eg 3 /Eg 1 More than 3, the forbidden bandwidth of the second electron blocking layer 52 is more than 1.5 xEg 3 。
Referring to FIG. 2, the first electron storage layer 51 is In x N 1-x /In y Ga 1-y An N/GaN layer, a second electron blocking layer 52 of B m Ga 1-m N/B n N 1-n A third electron expansion layer 53 of In a Ga 1-a N/N type B b Ga 1-b And N layers.
In the first electron storage layer 51, x is 0.6 and y is 0.3.
Referring to fig. 3, wherein the first electron storage layer 51 includes In periodically stacked x N 1-x A sub-layer 511,In y Ga 1- y N sub-layer 512 and GaN sub-layer 513, wherein a single In x N 1-x The sub-layer 511 has a thickness of 3nm, a single In y Ga 1-y The thickness of the N sub-layer 512 was 3nm, the thickness of the single GaN sub-layer 513 was 8nm, the number of cycles of the first electron storage layer 51 was 3, and the growth temperature was 900 ℃.
In the second electron blocking layer 52, m is 0.3 and n is 0.5.
Referring to fig. 4, wherein the second electron blocking layer 52 comprises a periodically layered B m Ga 1-m N sublayer 521 and B n N 1-n Sub-layer 522, where a single B m Ga 1-m N sub-layer 521 has a thickness of 8nm, single B n N 1-n The thickness of the sub-layer 522 is 3nm, the number of periods of the second electron blocking layer 52 is 4, and the growth temperature is 1100 ℃.
Wherein, in the third electron extension layer 53, a is 0.3, b is 0.3, and the doping concentration of Si is 5×10 16 cm -3 。
Referring to fig. 5, wherein the third electron extension layer 53 comprises In periodically layered a Ga 1-a N sub-layer 531 and N type B b Ga 1-b An N sub-layer 532 In which a single In a Ga 1-a N sub-layer 531 has a thickness of 5nm, a single N type B b Ga 1-b The thickness of the N sub-layer 532 was 15nm, and the growth temperature of the third electron expansion layer 53 was 1000 ℃.
Referring to fig. 6, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate 1;
s200, sequentially depositing a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, an electronic guide layer 5, a multiple quantum well layer 6, an electronic barrier layer 7 and a P-type semiconductor layer 8 on a substrate 1;
the electron guiding layer 5 includes a first electron storage layer 51, a second electron blocking layer 52, and a third electron expansion layer 53 sequentially arranged in the epitaxial direction;
the forbidden bandwidth of the second electron blocking layer 52 > the forbidden bandwidth of the third electron expansion layer 53 > the forbidden bandwidth of the first electron storage layer 51.
The specific steps of step S200 are as follows:
s210, depositing a nucleation layer 2 on the substrate 1;
s220, depositing an intrinsic GaN layer 3 on the nucleation layer 2;
s230, depositing an N-type semiconductor layer 4 on the intrinsic GaN layer 3;
s240, depositing an electronic guide layer 5 on the N-type semiconductor layer 4;
s250, depositing a multi-quantum well layer 6 on the electronic guide layer 5;
s260, depositing an electron blocking layer 7 on the multiple quantum well layer 6;
and S270, depositing a P-type semiconductor layer 8 on the electron blocking layer 7.
The specific steps of step S240 are as follows:
s241 depositing a first electron storage layer 51 on the N-type semiconductor layer 4:
1) Deposition of In x N 1-x A sub-layer 511;
2) Deposition of In y Ga 1-y N sub-layer 512;
3) A GaN sub-layer 513 is deposited.
S242 depositing a second electron blocking layer 52 on the first electron storage layer 51:
1) Deposit B m Ga 1-m N sub-layer 521;
2) Deposit B n N 1-n A sub-layer 522.
S243. depositing a third electron expansion layer 53 on the second electron interception layer 52:
1) Deposition of In a Ga 1-a N sub-layer 531;
2) Depositing N type B b Ga 1-b N sublayer 532.
Example 2
The embodiment discloses a light-emitting diode epitaxial wafer, which comprises a substrate, wherein a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guide layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer are sequentially arranged on the substrate along the epitaxial direction;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than the forbidden bandwidth of the third electron expansion layer, and the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer.
The first electron storage layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are periodically stacked, and the forbidden bandwidth Eg of the third sub-layer 3 Forbidden bandwidth Eg of > second sub-layer 2 Forbidden band width Eg of > first sublayer 1 And Eg 3 /Eg 1 More than 3, the forbidden bandwidth of the second electron blocking layer is more than 1.5 xEg 3 。
Wherein the first electron storage layer is In x N 1-x /In y Ga 1-y An N/GaN layer, a second electron interception layer B m Ga 1-m N/B n N 1-n A third electron expansion layer of In a Ga 1-a N/N type B b Ga 1-b And N layers.
In the first electron storage layer, x is 0.4 and y is 0.1.
Wherein the first electron storage layer comprises In laminated periodically x N 1-x Sublayer, in y Ga 1-y N sub-layer and GaN sub-layer, wherein, single In x N 1-x The thickness of the sub-layer is 3nm, single In y Ga 1-y The thickness of the N sub-layer is 3nm, the thickness of the single GaN sub-layer is 8nm, the number of cycles of the first electron storage layer is 3, and the growth temperature is 900 ℃.
In the second electron interception layer, m is 0.1, and n is 0.3.
Wherein the second electron blocking layer comprises periodically layered B m Ga 1-m N sub-layer and B n N 1-n A sublayer, wherein a single B m Ga 1-m The thickness of the N sub-layer is 8nm, single B n N 1-n The thickness of the sub-layer is 3nm, the number of periods of the second electron interception layer is 4, and the growth temperature is 1100 ℃.
Wherein, in the third electron expansion layer, a is 0.1, b is 0.1, and the doping concentration of Si is 5×10 16 cm -3 。
Wherein the third electron expansion layer comprises In which is periodically layered a Ga 1-a N-pieceLayer and N type B b Ga 1-b N sublayers, wherein a single In a Ga 1-a The thickness of the N sub-layer is 5nm, and single N type B b Ga 1-b The thickness of the N sub-layer is 15nm, and the growth temperature of the third electron expansion layer is 1000 ℃.
The invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate;
s200, sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guide layer, a multiple quantum well layer, an electronic barrier layer and a P-type semiconductor layer on a substrate;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than that of the third electron expansion layer and larger than that of the first electron storage layer.
The specific steps of step S200 are as follows:
s210, depositing a nucleation layer on a substrate;
s220, depositing an intrinsic GaN layer on the nucleation layer;
s230, depositing an N-type semiconductor layer on the intrinsic GaN layer;
s240, depositing an electronic guide layer on the N-type semiconductor layer;
s250, depositing a multi-quantum well layer on the electronic guide layer;
s260, depositing an electron blocking layer on the multiple quantum well layer;
and S270, depositing a P-type semiconductor layer on the electron blocking layer.
The specific steps of step S240 are as follows:
s241, depositing a first electron storage layer on the N-type semiconductor layer:
1) Deposition of In x N 1-x A sub-layer;
2) Deposition of In y Ga 1-y An N sub-layer;
3) And depositing a GaN sub-layer.
S242, depositing a second electron interception layer on the first electron storage layer:
1) Deposit B m Ga 1-m An N sub-layer;
2) Deposit B n N 1-n A sub-layer.
S243, depositing a third electron expansion layer on the second electron interception layer:
1) Deposition of In a Ga 1-a An N sub-layer;
2) Depositing N type B b Ga 1-b N sub-layers.
Comparative example 1
The present comparative example is different from example 1 in that the epitaxial wafer of the present comparative example does not include an electronic guiding layer and the production method does not include a production step of the corresponding material layer.
Comparative example 2
The present comparative example is different from example 1 in that the electronic guide layer of the present comparative example does not include the first electron storage layer and the preparation method does not include the preparation step of the corresponding material layer.
Comparative example 3
The present comparative example is different from example 1 In that the first electron storage layer of the present comparative example is In y Ga 1-y The N/GaN layer, i.e. the first electron storage layer, does not contain In x N 1-x The preparation method of the sub-layer does not comprise the preparation steps of the corresponding material layer.
Comparative example 4
The present comparative example is different from example 1 in that the electron guiding layer of the present comparative example does not include the second electron blocking layer and the preparation method does not include the preparation step of the corresponding material layer.
Comparative example 5
The present comparative example is different from example 1 in that the second electron blocking layer of the present comparative example is B m Ga 1-m N sublayers, i.e. the second electron-blocking layer does not contain B n N 1-n The preparation method of the sub-layer does not comprise the preparation steps of the corresponding material layer.
Comparative example 6
The present comparative example is different from example 1 in that the electronic guiding layer of the present comparative example does not include the third electronic expansion layer, and the preparation method does not include the preparation step of the corresponding material layer.
Comparative example 7
This comparative example is different from example 1 In that the third electron extension layer of this comparative example is periodically laminated with In a Ga 1-a N sub-layer and undoped B b Ga 1-b N sublayers, i.e. B b Ga 1-b The N sub-layer is not N-doped.
Photoelectric performance test:
the testing method comprises the following steps: the epitaxial wafers prepared in examples 1 to 2 and comparative examples 1 to 7 were prepared into 10×24mil chips, and then subjected to a photoelectric performance test.
Wherein, the smaller the brightness uniformity value, the more uniform the brightness distribution, the smaller the wavelength uniformity value, and the more uniform the wavelength distribution.
The test results were as follows:
Figure SMS_1
from the test results, examples 1 to 2 and comparative examples 2 to 7 were improved in antistatic ability, luminous efficiency, luminance uniformity and wavelength uniformity to different degrees from comparative example 1, wherein examples 1 to 2 were significantly improved in performance in various aspects, and the first electron storage layer and specific material layer structure thereof were seen to have an influence on the luminous efficiency, luminance uniformity and wavelength uniformity, and the second electron blocking layer and specific material layer structure thereof were seen to have an influence on the antistatic ability, luminance uniformity and wavelength uniformity, and the third electron expansion layer and specific material layer structure thereof were seen to have an influence on the antistatic ability, luminance efficiency, luminance uniformity and wavelength uniformity, and the third electron blocking layer and specific material layer structure thereof were seen to have an influence on the antistatic ability, luminance efficiency, luminance uniformity and wavelength uniformity, and the comparative examples 1, 6 and 7.
The foregoing description is only illustrative of the preferred embodiment of the present invention, and is not to be construed as limiting the invention, but is to be construed as limiting the invention to any and all simple modifications, equivalent variations and adaptations of the embodiments described above, which are within the scope of the invention, may be made by those skilled in the art without departing from the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer comprises a substrate and is characterized in that a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guide layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer are sequentially arranged on the substrate along the epitaxial direction;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer.
2. The led epitaxial wafer of claim 1, wherein the first electron storage layer comprises a first sub-layer, a second sub-layer, and a third sub-layer, which are periodically stacked, the third sub-layer having a forbidden band width Eg 3 Forbidden bandwidth Eg of > second sub-layer 2 Forbidden band width Eg of > first sublayer 1 And Eg 3 /Eg 1 More than 3, the forbidden bandwidth of the second electron blocking layer is more than 1.5 xEg 3 。
3. The light emitting diode epitaxial wafer of claim 1, wherein the first electron storage layer is In x N 1-x /In y Ga 1-y An N/GaN layer, wherein the second electron interception layer is B m Ga 1-m N/B n N 1-n A third electron expansion layer of In a Ga 1-a N/N type B b Ga 1-b And N layers.
4. The light-emitting diode epitaxial wafer of claim 3, wherein 0.6 x 0.4,0.3 y 0.1 in the first electron storage layer.
5. The light emitting diode epitaxial wafer of claim 4, wherein the first electron storage layer comprises periodically stacked In x N 1-x Sublayer, in y Ga 1-y N sub-layer and GaN sub-layer, wherein, single In x N 1-x The thickness of the sub-layer is 1 nm-5 nm, and single In y Ga 1-y The thickness of the N sub-layer is 1 nm-5 nm, the thickness of a single GaN sub-layer is 6 nm-10 nm, the number of cycles of the first electron storage layer is 2-6, and the growth temperature is 800-900 ℃.
6. A light emitting diode epitaxial wafer according to claim 3 wherein in said second electron blocking layer 0.3.gtoreq.0.1 and 0.5.gtoreq.n.gtoreq.0.3.
7. The led epitaxial wafer of claim 6, wherein the second electron blocking layer comprises a periodically layered B m Ga 1-m N sub-layer and B n N 1-n A sublayer, wherein a single B m Ga 1-m The thickness of the N sub-layer is 6 nm-10 nm, and a single B n N 1-n The thickness of the sub-layer is 2 nm-5 nm, the number of cycles of the second electron interception layer is 2-6, and the growth temperature is 1000-1100 ℃.
8. The light-emitting diode epitaxial wafer according to claim 3, wherein in the third electron expansion layer, 0.3.gtoreq.a.gtoreq.0.1, 0.3.gtoreq.b.gtoreq.0.1, and the doping concentration of Si is 1×10 16 cm -3 ~1×10 17 cm -3 。
9. The light emitting diode epitaxial wafer of claim 8, wherein the third electron expansion layer comprises periodically stacked In a Ga 1-a N sub-layer and N type B b Ga 1-b N sublayers, wherein a single In a Ga 1-a The thickness of the N sub-layer is 1 nm-10 nm, and the single N type B b Ga 1-b The thickness of the N sub-layer is 10 nm-20 nm, and the growth temperature of the third electron expansion layer is 900-1000 ℃.
10. The preparation method of the light-emitting diode epitaxial wafer is characterized by comprising the following steps of:
providing a substrate;
sequentially depositing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, an electronic guiding layer, a multiple quantum well layer, an electronic blocking layer and a P-type semiconductor layer on the substrate;
the electron guide layer comprises a first electron storage layer, a second electron interception layer and a third electron expansion layer which are sequentially arranged along the epitaxial direction;
the forbidden bandwidth of the second electron interception layer is larger than the forbidden bandwidth of the third electron expansion layer, and the maximum forbidden bandwidth of the third electron expansion layer is larger than the forbidden bandwidth of the first electron storage layer.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117352537A (en) * 2023-12-06 2024-01-05 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method thereof, HEMT
CN117352537B (en) * 2023-12-06 2024-03-08 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method thereof, HEMT

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