CN116646431A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN116646431A
CN116646431A CN202310769277.XA CN202310769277A CN116646431A CN 116646431 A CN116646431 A CN 116646431A CN 202310769277 A CN202310769277 A CN 202310769277A CN 116646431 A CN116646431 A CN 116646431A
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layer
emitting diode
gan
light
composite interface
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印从飞
张彩霞
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and a light-emitting diode, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multiple quantum well active layer, a P-type epitaxial layer and a contact layer which are sequentially laminated on the substrate; the first composite interface layer comprises first Al which are laminated in sequence x Ga 1‑x N layerFirst B y Ga 1‑ y An N layer and a first GaN layer; the second composite interface layer comprises a second Al which is laminated in sequence x Ga 1‑x N layer, second B y Ga 1‑y An N layer and a second GaN layer; the third composite interface layer comprises a third Al which is laminated in sequence x Ga 1‑x N layer, third B y Ga 1‑y N layer and third In z Ga 1‑z And N layers. By implementing the invention, the luminous efficiency and antistatic capability of the light-emitting diode can be improved.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In order to solve the lattice mismatch problem between the substrate and the GaN epitaxial layer, the prior art generally adopts a PVD (physical vapor deposition) method to plate an AlN buffer layer on the substrate, and then sequentially deposits an intrinsic GaN layer, a U/N type GaN layer, a multiple quantum well active layer, a P type GaN layer and a contact layer on the buffer layer. However, the AlN buffer layer obtained by PVD coating is too compact, which is unfavorable for the three-dimensional growth of the intrinsic GaN layer; in addition, although the AlN buffer layer may alleviate lattice mismatch between the substrate and GaN to a certain extent, more dislocations, defects and voids may still be generated, which not only affects the crystal quality of the N-type epitaxial layer, but also affects the light-emitting efficiency of the active region and the antistatic capability of the light-emitting diode after upward derivative migration.
Disclosure of Invention
The invention aims to solve the technical problem of providing the light-emitting diode epitaxial wafer which can improve the light-emitting efficiency and antistatic capability of a light-emitting diode.
The invention also aims to solve the technical problem of providing the preparation method of the light-emitting diode epitaxial wafer, which has simple process and high light-emitting efficiency.
In order to achieve the technical effects, the invention provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multiple quantum well active layer, a P-shaped epitaxial layer and a contact layer which are sequentially laminated on the substrate;
the first composite interface layer comprises first Al which are laminated in sequence x Ga 1-x N layer, first B y Ga 1-y An N layer and a first GaN layer;
the second composite interface layer comprises a second Al which is laminated in sequence x Ga 1-x N layer, second B y Ga 1-y An N layer and a second GaN layer;
the third composite interface layer comprises a third Al which is laminated in sequence x Ga 1-x N layer, third B y Ga 1-y N layer and third In z Ga 1-z And N layers.
As an improvement of the above technical scheme, the first Al x Ga 1-x The value range of x in the N layer is 0.3-0.6, and the second Al x Ga 1-x The value range of x in the N layer is 0.2-0.4, and the third Al x Ga 1-x The value range of x in the N layer is 0.1-0.3.
As an improvement of the above technical scheme, the first B y Ga 1-y The value range of y in the N layer is 0.3-0.8, and the second B y Ga 1-y The value range of y in the N layer is 0.1-0.3, and the third B y Ga 1-y The value range of y in the N layer is 0.1-0.3.
As an improvement of the above technical scheme, the third In z Ga 1-z The value range of z in the N layer is 0.1-0.2.
As an improvement of the above technical scheme, the first Al x Ga 1-x N layer, first B y Ga 1-y The N layer and the first GaN layer are undoped layers;
the second Al x Ga 1-x N layer, second B y Ga 1-y The N layer and the second GaN layer are N-type doped layers;
the third Al x Ga 1-x N layer and third B y Ga 1-y The N layer is an N-type doped layer, and the third In z Ga 1-z The N layer is an undoped layer.
As an improvement of the above technical scheme, the second Al x Ga 1-x The doping concentration of the N layer is 2 multiplied by 10 16 -6×10 16 cm -3 The second B y Ga 1-y The doping concentration of the N layer is 2 multiplied by 10 16 -6×10 16 cm -3 The doping concentration of the second GaN layer is 5×10 17 -1×10 18 cm -3 ；
The third Al x Ga 1-x The doping concentration of the N layer is 2 multiplied by 10 17 -6×10 17 cm -3 The third B y Ga 1-y The doping concentration of the N layer is 1 multiplied by 10 16 -3×10 16 cm -3 。
As an improvement of the above technical scheme, the first Al x Ga 1-x The thickness of the N layer is 5-10nm, the first B y Ga 1-y The thickness of the N layer is 3-6nm, and the thickness of the first GaN layer is 20-60nm;
the second Al x Ga 1-x The thickness of the N layer is 50-100nm, the second B y Ga 1-y The thickness of the N layer is 50-100nm, and the thickness of the second GaN layer is 100-200nm;
the third Al x Ga 1-x The thickness of the N layer is 20-60nm, the third B y Ga 1-y The thickness of the N layer is 20-60nm, the third In z Ga 1-z The thickness of the N layer is 10-30nm.
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps of:
providing a substrate, and sequentially growing a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multi-quantum well active layer, a P-type epitaxial layer and a contact layer on the substrate;
wherein the first composite interface layer comprises a first Al layer laminated in sequence x Ga 1-x N layer, first B y Ga 1-y An N layer and a first GaN layer;
the second composite interface layer comprises a second Al which is laminated in sequence x Ga 1-x N layer, second B y Ga 1-y An N layer and a second GaN layer;
the third composite interface layer comprises a third Al which is laminated in sequence x Ga 1-x N layer, third B y Ga 1-y N layer and third In z Ga 1-z And N layers.
As an improvement to the above-described technical solution,
the growth temperature of the first composite interface layer is 800-900 ℃, and the growth pressure is 100-200Torr;
the growth temperature of the second composite interface layer is 1000-1150 ℃ and the growth pressure is 100-150Torr;
the growth temperature of the third interface composite layer is 850-1050 ℃, and the growth pressure is 100-150Torr.
Correspondingly, the invention also provides a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The embodiment of the invention has the following beneficial effects:
the light-emitting diode epitaxial wafer provided by the invention grows a first composite interface layer, a second composite interface layer and a third composite interface layer between the buffer layer and the intrinsic GaN layer, between the U-shaped GaN layer and the N-shaped GaN layer and between the N-shaped GaN layer and the multiple quantum well active layer respectively. The first composite interface layer can relieve lattice mismatch between the buffer layer and the intrinsic GaN layer and reduce dislocation; the second composite interface layer not only can provide a channel for electron migration, but also can reduce the defect density, reduce the leakage channel and improve the antistatic capability; the third composite interface layer can release stress in advance while increasing the composite probability of electrons and holes, reduce mismatch stress in an active region and comprehensively improve the luminous efficiency and antistatic capability.
Drawings
Fig. 1 is a schematic structural view of a light emitting diode epitaxial wafer in embodiment 1 of the present invention;
fig. 2 is a schematic structural view of a first composite interfacial layer in example 1 of the present invention;
fig. 3 is a schematic structural view of a second composite interfacial layer in example 1 of the present invention;
fig. 4 is a schematic structural view of a third composite interfacial layer in example 1 of the present invention;
fig. 5 is a flowchart of a method for manufacturing a light emitting diode epitaxial wafer in embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
As shown in fig. 1 to 4, the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate 1, and a buffer layer 2, a first composite interface layer 3, an intrinsic GaN layer 4, a U-shaped GaN layer 5, a second composite interface layer 6, an N-type GaN layer 7, a third composite interface layer 8, a multiple quantum well active layer 9, a P-type epitaxial layer 10 and a contact layer 11 which are sequentially stacked on the substrate 1.
Wherein the first composite interface layer 3 comprises a first Al layer laminated in sequence x Ga 1-x N layer 31, first B y Ga 1-y An N layer 32 and a first GaN layer 33. First Al x Ga 1-x The N layer 31 is mainly used for relieving mismatch stress between the buffer layer 2 and the intrinsic GaN layer 4; first B y Ga 1-y The B atoms in the N layer 32 are smaller, so that defects of the bottom layer can be partially filled, and the defect density is reduced; the first GaN layer 33 is a repair fill to the surface of the buffer layer 2 while providing a partial nucleation seed for the three-dimensionally grown intrinsic GaN.
The second composite interface layer 6 comprises a second Al laminated in sequence x Ga 1-x N layer 61, second B y Ga 1-y An N layer 62 and a second GaN layer 63. Second Al in a second composite interface layer x Ga 1-x N layer 61 and second B y Ga 1-y The N layer 62 can not only provide a channel for electron migration, but also reduce defect density, reduce leakage channels, and improve antistatic ability.
The third composite interfacial layer 8 comprises a third Al sequentially laminated x Ga 1-x N layer 81, third B y Ga 1-y N layer 82 and third In z Ga 1-z N layer 83. Third Al of third composite interface layer 8 x Ga 1-x N layer 81 and third B y Ga 1-y N layer 82 primarily serves to slow the flow of electronsThe effect of the method is beneficial to improving the electron density in the first active areas and increasing the recombination probability of electrons and holes; at the same time third Al x Ga 1-x N layer 81, third B y Ga 1-y N layer 82 and third In z Ga 1-z The N layers 83 can release stress in advance, reduce mismatch stress in the active region, and comprehensively improve luminous efficiency and antistatic capability.
In one embodiment, the first Al x Ga 1-x Al concentration in N layer 31 > second Al x Ga 1-x N layer 61 > third Al x Ga 1-x N layer 81. Since the first composite interfacial layer 3 is used for relieving lattice mismatch between the buffer layer and the subsequent epitaxial structure, the first Al x Ga 1-x The concentration of Al in the N layer 31 is highest, and the second composite interface layer 6 and the third composite interface layer 8 are mainly used for preventing defects from spreading upwards along with the lamination of the epitaxial structure, so that a lower concentration of Al and a third Al can be selected x Ga 1-x The low Al composition in the N layer 81 also contributes to a reduction in operating voltage. Preferably, the first Al x Ga 1-x The value of x in the N layer 31 ranges from 0.3 to 0.6, and the second Al x Ga 1-x The value of x in the N layer 61 ranges from 0.2 to 0.4, and the third Al x Ga 1-x The value of x in the N layer 81 ranges from 0.1 to 0.3.
In one embodiment, the first B y Ga 1-y Y in the N layer 32 has a value ranging from 0.3 to 0.8, and the second B y Ga 1-y The value of y in the N layer 62 ranges from 0.1 to 0.3, the third B y Ga 1-y The value of y in the N layer 82 ranges from 0.1 to 0.3. The B atoms have smaller relative volume and can be inserted or filled into vacancies generated by the dislocation, fill the defect and inhibit dislocation extension.
In one embodiment, the first Al x Ga 1-x N layer 31, first B y Ga 1-y The N layer 32 and the first GaN layer 33 are undoped layers. The first composite interface layer 3 is mainly used for relieving mismatch stress between the buffer layer and the GaN layer, so that doping is not required.
The second Al x Ga 1-x N layer 61, second B y Ga 1-y The N layer 62 and the second GaN layer 63 are N-type doped layers. Preferably, the N-type doping may be Si doping. Second Al x Ga 1-x N layer 61 and second B y Ga 1-y The high barrier after doping of the N layer 62 annihilates or diverts defects of the underlying layer, further reducing the defect density of the underlying layer.
The third Al x Ga 1-x N layer 81 and third B y Ga 1-y N layer 82 is an N-type doped layer, the third In z Ga 1-z The N layer 83 is an undoped layer. Preferably, the N-type doping may be Si doping. Third Al x Ga 1-x N layer 81 and third B y Ga 1-y The N layer 82 may further reduce the electron flow rate of the N-type GaN layer 7 after doping with Si.
In one embodiment, the second Al x Ga 1-x The doping concentration of the N layer 61 is 2×10 16 -6×10 16 cm -3 The second B y Ga 1-y The doping concentration of the N layer 62 is 2×10 16 -6×10 16 cm -3 The second GaN layer 63 has a doping concentration of 5×10 17 -1×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The third Al x Ga 1-x The doping concentration of the N layer 81 is 2×10 17 -6×10 17 cm -3 The third B y Ga 1-y The doping concentration of the N layer 82 is 1×10 16 -3×10 16 cm -3 . Too small a doping concentration may result in too low an electron concentration in the second and third composite interface layers 6 and 8 and too large a doping concentration may cause excessive defects.
In one embodiment, a first Al x Ga 1-x The thickness of the N layer 31 is 5-10nm, the first B y Ga 1-y The thickness of the N layer 32 is 3-6nm and the thickness of the first GaN layer 33 is 20-60nm. Preferably, the total thickness of the first composite interface layer 3 is 30-75nm, if the total thickness of the first composite interface layer 3 is less than 30nm, the effect of relieving lattice mismatch is weak, and if the total thickness of the first composite interface layer 3 is more than 75nm, the crystal quality is reduced and the resource is wasted due to the excessively thick growth temperature.
The second Al x Ga 1-x The thickness of the N layer 61 is 50-100nm, the second B y Ga 1-y The thickness of the N layer 62 is 50-100nm and the thickness of the second GaN layer 63 is 100-200nm. Preferably, the total thickness of the second composite interfacial layer 6 is 0.25-0.4 μm, and if the total thickness of the second composite interfacial layer 6 is less than 0.25 μm, the filling effect on defects is small, and if the total thickness of the second composite interfacial layer 6 is more than 0.4 μm, subsequent growth defects are caused.
The third Al x Ga 1-x The thickness of the N layer 81 is 20-60nm, the third B y Ga 1-y The thickness of the N layer 82 is 20-60nm, the third In z Ga 1-z The thickness of the N layer 83 is 10-30nm. Preferably, the total thickness of the third composite interfacial layer 8 is 50-120nm, if the total thickness of the third composite interfacial layer 8 is less than 50nm, the effect of reducing the flow rate of electrons is smaller, and if the total thickness of the third composite interfacial layer 8 is more than 120nm, surface roughening is caused, and the yield of the epitaxial wafer is affected.
In addition to the above-described composite interface layer, other layered structures of the present invention are characterized as follows:
in one embodiment, the substrate 1 is one of a sapphire substrate, a silicon carbide substrate, or a silicon substrate. Preferably, the substrate 1 is a sapphire substrate.
In one embodiment, the buffer layer 2 is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer 2 is an AlN buffer layer. The thickness of the buffer layer 2 is 25-75nm.
In one embodiment, the intrinsic GaN layer 4 has a thickness of 1.5-2 μm.
In one embodiment, the U-shaped GaN layer 5 is doped with Si having a concentration of 5×10 17 -1×10 18 cm -3 The thickness of the U-shaped GaN layer 5 is 0.3-0.6 μm.
In one embodiment, the N-type GaN layer 7 is doped with Si having a concentration of 3×10 18 -8×10 18 cm -3 The thickness of the N-type GaN layer 7 is 1-2 μm.
In one embodiment, the multi-quantum well active layer 9 includes a periodically stacked InGaN quantum well layer, a quantum well low temperature GaN cap layer and a GaN quantum barrier layer, the number of periods is 6-12, the In component In the single InGaN quantum well layer accounts for 25-40%, the thickness of the single InGaN quantum well layer is 2-5nm, the thickness of the single quantum well low temperature GaN cap layer is 0.4-0.8nm, and the thickness of the single GaN quantum barrier layer is 9-19nm.
In one embodiment, the P-type epitaxial layer 10 is a P-GaN layer, the P-type doping is Mg doping, and the Mg doping concentration is 8X10% 18 -1×10 20 cm -3 The thickness of the P-type epitaxial layer 10 is 60-200nm.
In one embodiment, the contact layer 11 is a P-InGaN layer, the P-type doping is Mg doping, and the Mg doping concentration is 1×10 19 -1×10 20 cm -3 In doping concentration of 1.1X10 20 -8×10 20 cm -3 The thickness of the contact layer 11 is 10-50nm.
As shown in fig. 5, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s100 provides a substrate:
in one embodiment, the substrate is a Patterned Sapphire Substrate (PSS).
S101 growth of a buffer layer:
in one embodiment, the substrate is placed in PVD with Ar as the sputtering gas, N 2 The precursor and the Al target are used as target materials, and a small amount of O is introduced 2 Adjusting the quality of the crystal, wherein the sputtering temperature is 500-600 ℃, and the sputtering power is 3000-5000W, thus obtaining the AlN buffer layer.
In one embodiment, the AlN buffer layer-plated wafer is placed in MOCVD, and H is passed through 2 As carrier gas, the temperature is controlled to be 1100-1200 ℃, the heat treatment time is 2-6min, and impurities such as water oxygen and the like on the substrate are mainly removed in the step, so that preparation is made for subsequent growth.
S102 growing a first composite interface layer:
controlling the temperature of the reaction cavity to be 800-900 ℃, controlling the pressure to be 100-200Torr, and introducing N 2 Is carrier gas, TMGa is Ga source, TMAL is Al source, NH 3 Growth of first Al as N source x Ga 1-x An N layer; closing TMAL and introducing B 2 H 6 The first B is continuously grown under the condition of B source, other source gases and the like y Ga 1-y An N layer; close B 2 H 6 The rest remains unchanged, and the first GaN layer continues to grow. The layer is mainly used for relieving lattice mismatch between the AlN buffer layer and the GaN layer and reducing dislocation.
S103, growing an intrinsic GaN layer:
controlling the temperature of the reaction cavity to 1110-1160 ℃ and the pressure to 100-300Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 Is N source, wherein N 2 And H 2 The volume ratio of (2) is 1 (20-40).
S104, growing a U-shaped GaN layer:
controlling the temperature of the reaction cavity to 1120-1200 ℃, the pressure to 180-300Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 As N source, siH 4 Doping is provided.
S105 growing a second composite interface layer:
controlling the temperature of the reaction cavity to be 1000-1150 ℃ and the pressure to be 100-150Torr, and introducing N 2 Is carrier gas, TMAL is Al source, TMGa is Ga source, NH 3 As N source, siH 4 Providing doping, growing a second Al x Ga 1-x An N layer; closing TMAL and introducing B 2 H 6 The conditions of B source, other source gases and the like are unchanged, and the second B is continuously grown y Ga 1-y An N layer; close B 2 H 6 The rest remains unchanged, and the second GaN layer continues to grow. The layer is mainly used for preventing defects of the bottom layer from spreading upwards and reducing defect density.
S106, growing an N-type GaN layer:
controlling the temperature of the reaction cavity to 1130-1200 ℃, the pressure to 200-300Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 As N source, siH 4 Doping is provided. The layer mainly provides electrons.
S107 growing a third composite interfacial layer:
controlling the temperature of the reaction cavity to be 1000-1050 ℃, controlling the pressure to be 100-150Torr, and introducing N 2 Is carrier gas, TMAL is Al source, TMGa is Ga source, NH 3 As N source, siH 4 Providing doping and growing a third Al x Ga 1-x An N layer; closing TMAL and introducing B 2 H 6 The conditions of B source, other source gases and the like are unchanged, the temperature of the reaction cavity is controlled to be 950-1000 ℃, and the third B is continuously grown y Ga 1-y An N layer; close B 2 H 6 Controlling the temperature of the reaction cavity to be 800-900 ℃, introducing TMIn as an In source, keeping the rest unchanged, and continuing to grow a third In z Ga 1-z And N layers. The layer is mainly used for blocking defects of the bottom layer, slowing down the flow speed of electrons and relieving the stress between the bottom layer and the quantum well.
S108 growing multiple quantum well active layer
Controlling the temperature of the reaction cavity to be 700-750 ℃, controlling the pressure to be 100-150Torr, and introducing N 2 As carrier gas, NH 3 An InGaN quantum well layer is grown by taking an N source, TMIn as an In source and TEGa as a Ga source; closing an In source, keeping the other source gases and other conditions unchanged, and continuing to grow a quantum well low-temperature GaN cap layer; all sources are then turned off, turning on N only 2 Pulling up to 830-850 ℃ and baking for 10s; after baking, controlling the temperature of the reaction cavity to 850-900 ℃, and then introducing H again 2 And N 2 As carrier gas, NH 3 Is N source, TMIn is In source, TEGa is Ga source, siH 4 Providing doping and growing a GaN quantum barrier layer; and periodically and circularly growing an InGaN quantum well layer, a quantum well low-temperature GaN cap layer and a GaN quantum barrier layer.
S109, growing a P-type epitaxial layer:
controlling the temperature of the reaction cavity to be 920-1000 ℃, controlling the pressure to be 260-400Torr, and introducing N 2 And H 2 As carrier gas, NH 3 Is N source, TEGa is Ga source, cp 2 Mg provides doping.
S110 growth of the contact layer:
controlling the temperature of the reaction cavity to 850-950 ℃ and the pressure to 150-300Torr, and introducing N 2 And H 2 As carrier gas, NH 3 Is N source, TEGa is Ga source, TMIn is In source, cp 2 Mg provides doping.
Correspondingly, the invention also provides a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The invention is further illustrated by the following specific examples.
Example 1
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multiple quantum well active layer, a P-type epitaxial layer and a contact layer which are sequentially laminated on the substrate.
Wherein the substrate is a sapphire substrate.
The buffer layer is an AlN layer with a thickness of 30nm.
The first composite interface layer comprises first Al which are laminated in sequence 0.55 Ga 0.45 N layer, first B 0.5 Ga 0.5 An N layer and a first GaN layer. First Al 0.55 Ga 0.45 The thickness of the N layer is 6nm, the first B 0.5 Ga 0.5 The thickness of the N layer was 4nm, and the thickness of the first GaN layer was 35nm.
The thickness of the intrinsic GaN layer was 1.6 μm.
The doping concentration of Si in the U-shaped GaN layer is 7 multiplied by 10 18 cm -3 The thickness was 0.45. Mu.m.
The second composite interface layer comprises a second Al which is laminated in sequence 0.3 Ga 0.7 N layer, second B 0.2 Ga 0.8 An N layer and a second GaN layer. Second Al 0.3 Ga 0.7 The doping concentration of Si in the N layer is 4.5X10 16 cm -3 Thickness of 66nm, second B 0.2 Ga 0.8 The doping concentration of Si in the N layer is 4.5X10 16 cm -3 The thickness was 50nm, and the doping concentration of Si in the second GaN layer was 5.5X10 17 cm -3 The thickness was 150nm.
The doping concentration of Si in the N-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 1.55. Mu.m.
The third composite interface layer comprises a third Al which is laminated in sequence 0.25 Ga 0.75 N layer, third B 0.22 Ga 0.78 N layer and third In 0.18 Ga 0.82 And N layers. Third Al 0.25 Ga 0.75 The doping concentration of Si in the N layer is 5×10 17 cm -3 Thickness of 40nm, third B 0.22 Ga 0.78 The doping concentration of Si in the N layer is 2×10 16 cm -3 Thickness of 30nm, third In 0.18 Ga 0.82 The thickness of the N layer was 20nm.
The multi-quantum well layer comprises an InGaN quantum well layer, a quantum well low-temperature GaN cap layer and a GaN quantum barrier layer which are grown periodically and alternately, and the cycle number is 9. The thickness of the InGaN quantum well layer is 3nm, the thickness of the quantum well low-temperature GaN cap layer is 0.45nm, and the thickness of the GaN quantum barrier layer is 15nm.
The doping concentration of Mg in the P-type epitaxial layer is 5 multiplied by 10 19 cm -3 The thickness was 85nm.
The doping concentration of Mg in the contact layer is 8×10 19 cm -3 The doping concentration of In was 5×10 20 cm -3 The thickness was 25nm.
The preparation method of the LED epitaxial wafer comprises the following steps:
s100 provides a substrate:
a sapphire substrate is selected.
S101 growth of a buffer layer:
placing the substrate in PVD, using Ar as sputtering gas, N 2 The precursor and the Al target are used as target materials, and a small amount of O is introduced 2 The AlN buffer layer is obtained by adjusting the quality of the crystal, the sputtering temperature is 550 ℃, and the sputtering power is 4000W.
Placing the wafer plated with the AlN buffer layer in MOCVD, and introducing H 2 The carrier gas was heat treated at 1150 c for 4min.
S102 growing a first composite interface layer:
controlling the temperature of the reaction cavity to 850 ℃, the pressure to 150Torr, and introducing N 2 Is carrier gas, TMGa is Ga source, TMAL is Al source, NH 3 Growth of first Al as N source 0.55 Ga 0.45 An N layer; closing TMAL and introducing B 2 H 6 The first B is continuously grown under the condition of B source, other source gases and the like 0.5 Ga 0.5 An N layer; close B 2 H 6 The rest remains unchanged, and the first GaN layer continues to grow.
S103, growing an intrinsic GaN layer:
controlling the temperature of the reaction cavity to 1120 ℃, the pressure to 200Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 Is N source, wherein N 2 And H 2 Is 1:30 by volume.
S104, growing a U-shaped GaN layer:
controlling the temperature of the reaction cavity to 1150 ℃ and the pressure to 220Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 As N source, siH 4 Doping is provided.
S105 growing a second composite interface layer:
controlling the temperature of the reaction cavity to 1050 ℃, controlling the pressure to 120Torr, and introducing N 2 Is carrier gas, TMAL is Al source, TMGa is Ga source, NH 3 As N source, siH 4 Providing doping, growing a second Al 0.3 Ga 0.7 An N layer; closing TMAL and introducing B 2 H 6 The conditions of B source, other source gases and the like are unchanged, and the second B is continuously grown 0.2 Ga 0.8 An N layer; close B 2 H 6 The rest remains unchanged, and the second GaN layer continues to grow.
S106, growing an N-type GaN layer:
controlling the temperature of the reaction cavity to 1150 ℃ and the pressure to 220Torr, and introducing N 2 And H 2 Is carrier gas, TMGa is Ga source, NH 3 As N source, siH 4 Doping is provided.
S107 growing a third composite interfacial layer:
controlling the temperature of the reaction cavity to 1020 ℃, the pressure to 120Torr, and introducing N 2 Is carrier gas, TMAL is Al source, TMGa is Ga source, NH 3 As N source, siH 4 Providing doping and growing a third Al 0.25 Ga 0.75 An N layer; closing TMAL and introducing B 2 H 6 The conditions of B source, other source gases and the like are unchanged, the temperature of the reaction cavity is controlled to be 950 ℃, and the third B is continuously grown 0.22 Ga 0.78 An N layer; close B 2 H 6 Controlling the temperature of the reaction cavity to 850 ℃, introducing TMIn as an In source, keeping the rest unchanged, and continuing to grow a third In 0.18 Ga 0.82 And N layers.
S108 growing a multiple quantum well active layer:
controlling the temperature of the reaction cavity to 720 ℃, the pressure to 120Torr, and introducing N 2 As carrier gas, NH 3 An InGaN quantum well layer is grown by taking an N source, TMIn as an In source and TEGa as a Ga source; closing an In source, keeping the other source gases and other conditions unchanged, and continuing to grow a quantum well low-temperature GaN cap layer; all sources are then turned off, turning on N only 2 Pulling up to 840 ℃ and baking for 10s; after baking, the temperature of the reaction cavity is controlled to be 880 ℃, and H is introduced again 2 And N 2 As carrier gas, NH 3 Is N source, TMIn is In source, TEGa is Ga source, siH 4 Providing doping and growing a GaN quantum barrier layer; and periodically and circularly growing an InGaN quantum well layer, a quantum well low-temperature GaN cap layer and a GaN quantum barrier layer.
S109, growing a P-type epitaxial layer:
controlling the temperature of the reaction cavity to 950 ℃ and the pressure to 300Torr, and introducing N 2 And H 2 As carrier gas, NH 3 Is N source, TEGa is Ga source, cp 2 Mg provides doping.
S110 growth of the contact layer:
controlling the temperature of the reaction cavity to 900 ℃, the pressure to 180Torr, and introducing N 2 And H 2 As carrier gas, NH 3 Is N source, TEGa is Ga source, TMIn is In source, cp 2 Mg provides doping.
Example 2
The present example provides a light emitting diode epitaxial wafer that differs from example 1 in the composition and doping concentration of the first, second, and third composite interface layers.
Specifically, the first composite interface layer includes a first Al layer laminated in sequence 0.53 Ga 0.47 N layer, first B 0.52 Ga 0.48 An N layer and a first GaN layer.
The second composite interface layer comprises a second Al which is laminated in sequence 0.33 Ga 0.67 N layer, second B 0.18 Ga 0.82 An N layer and a second GaN layer. Second Al 0.33 Ga 0.67 The doping concentration of Si in the N layer is 4.8X10 16 cm -3 Second B 0.18 Ga 0.82 The doping concentration of Si in the N layer is 4.8X10 16 cm -3 In the second GaN layerSi doping concentration of 5.8X10 17 cm -3 。
The third composite interface layer comprises a third Al which is laminated in sequence 0.27 Ga 0.73 N layer, third B 0.23 Ga 0.77 N layer and third In 0.2 Ga 0.8 And N layers. Third Al 0.27 Ga 0.73 The doping concentration of Si in the N layer is 5.4X10 17 cm -3 Third B 0.23 Ga 0.77 The doping concentration of Si in the N layer was 2.5X10 16 cm -3 。
Example 3
The present example provides a light emitting diode epitaxial wafer that differs from example 1 in the composition and doping concentration of the first, second, and third composite interface layers.
Specifically, the first composite interface layer includes a first Al layer laminated in sequence 0.55 Ga 0.45 N layer, first B 0.53 Ga 0.47 An N layer and a first GaN layer.
The second composite interface layer comprises a second Al which is laminated in sequence 0.35 Ga 0.65 N layer, second B 0.22 Ga 0.78 An N layer and a second GaN layer. Second Al 0.35 Ga 0.65 The doping concentration of Si in the N layer is 4.8X10 16 cm -3 Second B 0.22 Ga 0.78 The doping concentration of Si in the N layer is 4.8X10 16 cm -3 The doping concentration of Si in the second GaN layer is 5.8X10 17 cm -3 。
The third composite interface layer comprises a third Al which is laminated in sequence 0.26 Ga 0.74 N layer, third B 0.24 Ga 0.76 N layer and third In 0.2 Ga 0.8 And N layers. Third Al 0.26 Ga 0.74 The doping concentration of Si in the N layer is 5.4X10 17 cm -3 Third B 0.24 Ga 0.76 The doping concentration of Si in the N layer was 2.5X10 16 cm -3 。
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the first, second, and third composite interface layers are not provided.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that only the first composite interface layer is provided, and the second and third composite interface layers are not provided.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that only the second composite interface layer is provided, and the first and third composite interface layers are not provided.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that only the third composite interface layer is provided, and the first and second composite interface layers are not provided.
Performance test:
the LED chips of 10mil by 24mil horizontal structure were fabricated from the LED epitaxial wafers prepared in examples 1-3 and comparative examples 1-4, and tested for light-emitting brightness (test current 120 mA), antistatic properties (-8 kV), and operating voltage. The test results are shown in Table 1.
Table 1 results of testing the photoelectric properties of led epitaxial wafers
As can be seen from the results in table 1, the light-emitting brightness and antistatic performance of the chip prepared from the led epitaxial wafer according to example 1 of the present invention are improved, and the operating voltage is reduced. As can be seen from the comparison of comparative examples 1-4 with example 1, it is difficult to effectively improve the photoelectric properties when the composite interfacial layer provided in example 1 of the present invention is not employed.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multiple quantum well active layer, a P-type epitaxial layer and a contact layer which are sequentially laminated on the substrate;
the first composite interface layer comprises first Al which are laminated in sequence x Ga 1-x N layer, first B y Ga 1-y An N layer and a first GaN layer;
the second composite interface layer comprises a second Al which is laminated in sequence x Ga 1-x N layer, second B y Ga 1-y An N layer and a second GaN layer;
the third composite interface layer comprises a third Al which is laminated in sequence x Ga 1-x N layer, third B y Ga 1-y N layer and third In z Ga 1-z And N layers.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the first Al x Ga 1-x The value range of x in the N layer is 0.3-0.6, and the second Al x Ga 1-x The value range of x in the N layer is 0.2-0.4, and the third Al x Ga 1-x The value range of x in the N layer is 0.1-0.3.
3. The light-emitting diode epitaxial wafer of claim 1, wherein the first B y Ga 1-y The value range of y in the N layer is 0.3-0.8, and the second B y Ga 1-y The value range of y in the N layer is 0.1-0.3, and the third B y Ga 1-y The value range of y in the N layer is 0.1-0.3.
4. The light-emitting diode epitaxial wafer of claim 1, wherein theThird In z Ga 1-z The value range of z in the N layer is 0.1-0.2.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the first Al x Ga 1-x N layer, first B y Ga 1-y The N layer and the first GaN layer are undoped layers;
the second Al x Ga 1-x N layer, second B y Ga 1-y The N layer and the second GaN layer are N-type doped layers;
the third Al x Ga 1-x N layer and third B y Ga 1-y The N layer is an N-type doped layer, and the third In z Ga 1-z The N layer is an undoped layer.
6. The light-emitting diode epitaxial wafer of claim 5, wherein the second Al x Ga 1-x The doping concentration of the N layer is 2 multiplied by 10 16 -6×10 16 cm -3 The second B y Ga 1-y The doping concentration of the N layer is 2 multiplied by 10 16 -6×10 16 cm -3 The doping concentration of the second GaN layer is 5×10 17 -1×10 18 cm -3 ；
The third Al x Ga 1-x The doping concentration of the N layer is 2 multiplied by 10 17 -6×10 17 cm -3 The third B y Ga 1-y The doping concentration of the N layer is 1 multiplied by 10 16 -3×10 16 cm -3 。
7. The light-emitting diode epitaxial wafer of claim 1, wherein the first Al x Ga 1-x The thickness of the N layer is 5-10nm, the first B y Ga 1-y The thickness of the N layer is 3-6nm, and the thickness of the first GaN layer is 20-60nm;
the second Al x Ga 1-x The thickness of the N layer is 50-100nm, the second B y Ga 1-y The thickness of the N layer is 50-100nm, and the thickness of the second GaN layer is 100-200nm;
the third Al x Ga 1-x The thickness of the N layer is 20-60nm, the third B y Ga 1-y The thickness of the N layer is 20-60nm, the third In z Ga 1- z The thickness of the N layer is 10-30nm.
8. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 7, and is characterized by comprising the following steps:
providing a substrate, and sequentially growing a buffer layer, a first composite interface layer, an intrinsic GaN layer, a U-shaped GaN layer, a second composite interface layer, an N-shaped GaN layer, a third composite interface layer, a multi-quantum well active layer, a P-type epitaxial layer and a contact layer on the substrate;
wherein the first composite interface layer comprises a first Al layer laminated in sequence x Ga 1-x N layer, first B y Ga 1-y An N layer and a first GaN layer;
the second composite interface layer comprises a second Al which is laminated in sequence x Ga 1-x N layer, second B y Ga 1-y An N layer and a second GaN layer;
the third composite interface layer comprises a third Al which is laminated in sequence x Ga 1-x N layer, third B y Ga 1-y N layer and third In z Ga 1-z And N layers.
9. The method for manufacturing a light-emitting diode epitaxial wafer according to claim 8, wherein,
the growth temperature of the first composite interface layer is 800-900 ℃, and the growth pressure is 100-200Torr;
the growth temperature of the second composite interface layer is 1000-1150 ℃ and the growth pressure is 100-150Torr;
the growth temperature of the third interface composite layer is 800-1050 ℃, and the growth pressure is 100-150Torr.
10. A light emitting diode, characterized in that the light emitting diode comprises a light emitting diode epitaxial wafer according to any one of claims 1-7.
CN202310769277.XA 2023-06-27 2023-06-27 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Pending CN116646431A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978997A (en) * 2023-09-25 2023-10-31 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117691017A (en) * 2024-02-04 2024-03-12 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978997A (en) * 2023-09-25 2023-10-31 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116978997B (en) * 2023-09-25 2023-12-15 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117691017A (en) * 2024-02-04 2024-03-12 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117691017B (en) * 2024-02-04 2024-05-03 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

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