CN116525734A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN116525734A
CN116525734A CN202310577589.0A CN202310577589A CN116525734A CN 116525734 A CN116525734 A CN 116525734A CN 202310577589 A CN202310577589 A CN 202310577589A CN 116525734 A CN116525734 A CN 116525734A
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layer
emitting diode
light
epitaxial wafer
thickness
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张彩霞
印从飞
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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Abstract

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type semiconductor layer which are sequentially laminated on the substrate; the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu. The invention can lighten the piezoelectric polarization of the multi-quantum well layer, balance electrons and holes in the multi-quantum well layer and improve the luminous efficiency of the light-emitting diode.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
At present, gaN-based light emitting diodes are widely used in the fields of backlight sources, illumination, landscape lamps and the like, and attract more and more attention.
In the light emitting diode, the multiple quantum well layer is taken as an active region and is a very important structure for epitaxial growth, the multiple quantum well layer is a periodic structure which is formed by repeatedly laminating an InGaN quantum well layer and a GaN quantum barrier layer, however, as In atoms are larger, the multiple quantum well is subjected to compressive stress, and serious piezoelectric polarization exists In the multiple quantum well, so that the multiple quantum well energy band is inclined, and electrons and holes can cause serious spatial separation when passing through the quantum well region, the light emitting efficiency of the light emitting diode is reduced, and In atoms effectively incorporated into a GaN lattice are limited due to larger In atoms, and the light emitting efficiency of the light emitting diode is also influenced;
in addition, since Mg is difficult to activate, resulting in a low hole concentration and slower hole mobility than electrons, in the multiple quantum well layer, unbalance between electrons and holes is one of the key reasons for limiting the improvement of the light emitting efficiency of the light emitting diode.
Disclosure of Invention
The invention aims to solve the technical problem of providing the light-emitting diode epitaxial wafer, which reduces the piezoelectric polarization of a multi-quantum well layer, balances electrons and holes in the multi-quantum well layer and improves the light-emitting efficiency of the light-emitting diode epitaxial wafer.
The invention also aims to solve the technical problem of providing the preparation method of the light-emitting diode epitaxial wafer, which has simple process and high light-emitting efficiency.
In order to achieve the technical effects, the invention provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.
As an improvement of the technical scheme, the thickness of the first insertion layer is 20-200nm; the thickness of the second insertion layer is 20-200nm.
As an improvement of the technical scheme, the thickness ratio of the first insertion layer to the second insertion layer is 1 (1-2).
As an improvement of the above technical solution, the doping concentration of Sc in the first insertion layer is 1×10 3 -1×10 6 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of Lu in the second insertion layer is 1×10 3 -1×10 6 cm -3 。
As an improvement of the above technical solution, the doping concentration of Sc in the first insertion layer is 5×10 4 -5×10 5 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of Si in the N-type GaN layer is 5 multiplied by 10 17 -1×10 18 cm -3 。
As an improvement of the above technical solution, the doping concentration of Lu in the second insertion layer is 1×10 5 -1×10 6 cm -3 ；
The electron blocking layer is Al a Ga 1-a An N layer, wherein a is 0.2-0.4; the thickness of the electron blocking layer is 30-50nm.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer on the substrate;
the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.
As an improvement of the technical scheme, the growth temperature of the first insertion layer is 900-1100 ℃, and the growth pressure is 100-300Torr;
the growth temperature of the second insertion layer is 850-950 ℃, and the growth pressure is 100-300Torr.
As an improvement of the technical scheme, the growth temperature of the N-type GaN layer is 1100-1150 ℃ and the growth pressure is 100-500Torr;
the growth temperature of the electron blocking layer is 900-1100 ℃, and the growth pressure is 100-500Torr.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The embodiment of the invention has the following beneficial effects:
1. according to the method, the first insertion layer and the second insertion layer are respectively grown before and after the multiple quantum well layer, and the lattice constant of the super cell can be improved by Lu element doping and Sc element doping, so that tensile stress is provided for the multiple quantum well layer. Under the action of tensile stress, the multiple quantum well layer can incorporate more In atoms, so that the lattice quality of the quantum well layer is improved; correspondingly, the compressive stress of the multi-quantum well layer is reduced, the piezoelectric polarization effect is weakened, the superposition of electron and hole wave functions of the multi-quantum well layer is increased, and the first insertion layer and the second insertion layer are beneficial to improving the luminous efficiency of the light-emitting diode; in addition, after the Lu and Sc elements are doped, the static dielectric constant of GaN is improved, and the high voltage resistance of the system is enhanced, so that the antistatic capability of the light emitting diode is enhanced.
2. The first insertion layer and the N-type GaN layer are higher in lattice matching degree, so that the doping concentration of Si in the N-type GaN layer can be reduced, the lattice quality is improved, and the luminous efficiency is improved.
3. The second insertion layer also has a certain electron blocking effect, so that the thickness of the electron blocking layer and the Al component in the electron blocking layer can be reduced, correspondingly, the potential barrier peak caused by the electron blocking layer is reduced, the probability that holes enter the multi-quantum well layer is further increased, and the luminous efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
As shown in fig. 1, the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a first insertion layer 5, a multiple quantum well layer 6, a second insertion layer 7, an electron blocking layer 8 and a P-type GaN layer 9 which are sequentially stacked on the substrate 1;
wherein the first insertion layer 5 is a Sc-doped GaN layer; the second insertion layer 7 is a Lu-doped GaN layer.
Because the atomic radius of Lu and Sc is larger than that of Ga, the lattice constant of the superlattice is increased after Lu and Sc are doped, and tensile stress is provided for the multiple quantum well. Under the action of tensile stress, the multiple quantum well layer can incorporate more In atoms, so that the incorporation of In components In the multiple quantum well layer is greatly increased, and the luminous efficiency is increased; the piezoelectric polarization of the multi-quantum well is weakened due to the reduction of the compressive stress of the multi-quantum well after the addition of the Lu and Sc elements, so that the superposition of electron and hole wave functions of the multi-quantum well layer is increased, and the luminous efficiency is improved; the static dielectric constants of GaN doped with Lu and Sc are improved, and the high voltage resistance of the system can be improved by the GaN layer doped with Lu and Sc, so that the antistatic capability of the light-emitting diode is improved.
The first insertion layer 5 grows on the N-type semiconductor layer 4, and the band gap becomes large after Sc element doping, so that an electron barrier with high energy level is formed in front of the quantum well, the effect of slowing down the electron migration rate is achieved, balance of electron hole pairs in the multi-quantum well is facilitated, and the luminous efficiency is improved;
the thickness of the first insertion layer 5 is 20-200nm, and if the growth thickness is less than 20nm, the effect of the first insertion layer 5 is smaller, and if the growth thickness is more than 200nm, the resource waste is caused. The thickness of the first insertion layer 5 is, but not limited to, 20nm, 25nm, 50nm, 75nm, 100nm, 150nm, or 200nm, for example.
Sc doping concentration of 1×10 3 -1×10 6 cm -3 If the doping concentration is less than 1×10 3 cm -3 Cannot play a role in slowing down the electron mobility, if the doping concentration is more than 1×10 6 cm -3 The lattice quality is reduced. The first intercalating layer 5 has an Sc doping concentration of 1X 10 3 cm -3 、1×10 4 cm -3 、1×10 5 cm -3 Or 1X 10 6 cm -3 But is not limited thereto.
After the second insertion layer 7 grows on the multiple quantum well layer 6 and Lu element is doped, shallow energy level impurities are induced, so that a conduction band is shifted to a low energy direction, a valence band is shifted upwards, injection of holes is facilitated, the problem of insufficient holes in the multiple quantum well is solved, and luminous efficiency is improved;
the thickness of the second insertion layer 7 is 20-200nm, and if the growth thickness is less than 20nm, the effect of the second insertion layer 7 is smaller, and if the growth thickness is more than 200nm, the resource waste is caused. The thickness of the second intercalating layer 7 is exemplified, but not limited to, 20nm, 25nm, 50nm, 75nm, 100nm, 150nm or 200nm.
Lu doping concentration of 1×10 3 -1×10 6 cm -3 If the doping concentration is less than 1×10 3 cm -3 Is unfavorable for hole injection into the multi-quantum well layer, if the doping concentration is more than 1 multiplied by 10 6 cm -3 The lattice quality is reduced. The second intercalating layer 7 has a Lu doping concentration of 1X 10 3 cm -3 、1×10 4 cm -3 、1×10 5 cm -3 Or 1X 10 6 cm -3 But is not limited thereto.
Preferably, the thickness ratio of the first insertion layer 5 to the second insertion layer 7 is 1 (1-2), the thickness ratio of the first insertion layer 5 to the second insertion layer 7 is controlled within the range, and the blocking of electrons by the first insertion layer 5 and the injection of holes by the second insertion layer 7 jointly act, so that the balance of electrons and holes in the multi-quantum well layer is facilitated, and the luminous efficiency is further improved. The thickness ratio of the first insertion layer 5 to the second insertion layer 7 is exemplified by, but not limited to, 1:1, 1:1.4, 1:1.5, 1:1.8, or 1:2.
Further, the Sc doping concentration in the first intercalating layer 5 is 5X 10 4 -5×10 5 cm -3 The doping concentration of Si in the N-type GaN layer 4 is 5 multiplied by 10 17- 1×10 18 cm -3 . At this Sc doping concentration, the lattice matching degree of the N-type GaN layer 4 and the first insertion layer 5 is higher, so that the Si doping concentration in the N-type GaN layer can be further reduced.
The doping concentration of Lu in the second insertion layer was 1×10 5 -1×10 6 cm -3 The electron blocking layer is Al a Ga 1-a An N layer, wherein a is 0.2-0.4; the thickness of the electron blocking layer is 30-50nm. The second insertion layer 7 also has a certain function of blocking electrons, so that the structure of the electron blocking layer 8 can be simplified, and the Al component in the electron blocking layer 8 and the thickness of the electron blocking layer 8 can be reduced. Correspondingly, the potential barrier peak caused by the electron blocking layer 8 is reduced, the probability of holes entering the multi-quantum well layer is further optimized, and the luminous efficiency is further improved.
In addition, the thickness of the nucleation layer 2 is 20-100nm;
the thickness of the intrinsic GaN layer 3 is 0.3-2 mu m;
the thickness of the N-type GaN layer 4 is 1-3 mu m;
the multiple quantum well layer 6 comprises a quantum well layer and a quantum barrier layer which are periodically stacked, wherein the stacking period is 3-15, the thickness of the quantum well layer is 2-5nm, and the thickness of the quantum barrier layer is 8-12nm.
The thickness of the P-type GaN layer 9 is 200-300nm, and the doping concentration of the P-type GaN layer 9 is 5 multiplied by 10 17 -1×10 20 cm -3 。
Correspondingly, as shown in fig. 2, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s101 providing a substrate
Selecting sapphire substrate, controlling the temperature of the reaction chamber to be 1000-1200 ℃, controlling the pressure to be 200-600Torr, and controlling the temperature of the reaction chamber to be H 2 High-temperature annealing is carried out on the sapphire substrate for 5-8min under the atmosphere, and particles and oxidization are carried out on the surface of the sapphire substrateThe object is cleaned.
S102 growing nucleation layer
The nucleation layer may be made of AlGaN or AlN.
Controlling the temperature of the reaction chamber to be 500-700 ℃ and the pressure to be 200-400Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source.
S103 growing an intrinsic GaN layer
Controlling the temperature of the reaction chamber to be 1100-1150 ℃ and the pressure to be 100-500Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source.
S104 growing N-type GaN layer
Controlling the temperature of the reaction chamber to be 1100-1150 ℃ and the pressure to be 100-500Torr, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, siH is introduced 4 As a doping source.
S105 growth of first insertion layer
Controlling the temperature of the reaction chamber to 900-1100 ℃, controlling the pressure to 100-300Torr, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, N 2 And H 2 The volume ratio of (1-5), TMGa as Ga source and Sc (TMHD) are introduced 3 As a doping source.
S106 growing multiple quantum well layers
Controlling the temperature of the reaction chamber to be 700-800 ℃, controlling the pressure to be 100-500Torr, and introducing NH 3 As N source, N 2 As carrier gas, introducing TEGa as Ga source, introducing TMIn as In source, and growing quantum well layer;
controlling the temperature of the reaction chamber to be 800-900 ℃, keeping the pressure unchanged, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, introducing TEGa as Ga source to grow quantum barrier layer;
the periodically grown quantum well layer and the quantum barrier layer are repeatedly stacked.
S107 growth of a second insertion layer
Controlling the temperature of the reaction chamber to 850-950 ℃ and the pressure to 100-300Torr, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, N 2 And H 2 The volume ratio of (1-5), TMGa as Ga source and Lu (TMHD) are introduced 3 As a doping source.
S108 growing an electron blocking layer
Controlling the temperature of the reaction chamber to 900-1100 ℃, controlling the pressure to 100-500Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source.
S109 growth of P-type GaN layer
Controlling the temperature of the reaction chamber to be 800-1000 ℃, controlling the pressure to be 100-300Torr, and introducing NH 3 As N source, TMGa as Ga source and CP 2 Mg is used as a doping source.
The invention is further illustrated by the following specific examples.
In an embodiment of the present invention, growth of epitaxial wafers is achieved using a Veeco C4 MOCVD (Metal Organic Chemical Vapor Deposition ) apparatus. Adopts high-purity H 2 And/or high purity N 2 As carrier gas, high purity NH 3 TMGa (trimethylgallium) and/or TEGa (triethylgallium) as the N source, TMAL (trimethylaluminum) as the aluminum source, TMIn (trimethylindium) as the indium source, siH 4 (silane) as N-type dopant, CP 2 Mg (magnesium-dicyclopentadiene) as a P-type dopant, sc (TMHD) 3 As a source of Sc doping, lu (TMHD) 3 As Lu doping sources, the above selections are exemplary illustrations and are not limited to the above list.
Example 1
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
wherein the substrate is a sapphire substrate;
the nucleation layer is an AlGaN layer with the thickness of 30nm;
the thickness of the intrinsic GaN layer is 600nm;
doping concentration of Si in N-type GaN layerIs 7X 10 18 cm -3 Thickness is 2 μm;
the multi-quantum well layer is formed by alternately stacking a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, the thickness is 3nm, the quantum barrier layer is a GaN layer, the thickness is 10nm, and the stacking period number is 10;
the first insertion layer is a GaN layer doped with Sc with a doping concentration of 1×10 4 cm -3 The thickness is 80nm;
the second insertion layer is a GaN layer doped with Lu, and the doping concentration of Lu is 1×10 4 cm -3 The thickness is 50nm;
the electron blocking layer is Al 0.45 Ga 0.55 N layers with a thickness of 100nm;
the doping concentration of Mg in the P-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 4nm.
The preparation method of the LED epitaxial wafer comprises the following steps:
s101 providing a substrate
Selecting sapphire substrate, controlling the temperature of the reaction chamber to be 1000 ℃, controlling the pressure to be 400Torr, and controlling the temperature and the pressure in H 2 And carrying out high-temperature annealing on the sapphire substrate for 6min under the atmosphere.
S102 growing nucleation layer
Controlling the temperature of the reaction chamber to 500 ℃, the pressure to 200Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source.
S103 growing an intrinsic GaN layer
Controlling the temperature of the reaction chamber to 1100 ℃, the pressure to 200Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source.
S104 growing N-type semiconductor layer
Controlling the temperature of the reaction chamber to 1150 ℃ and the pressure to 300Torr, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, siH is introduced 4 As a doping source.
S105 growth of first insertion layer
Controlling the reaction room temperatureThe temperature is 1000 ℃, the pressure is 200Torr, and NH is introduced 3 As N source, N 2 And H 2 As carrier gas, N 2 And H 2 Is introduced into TMGa as Ga source and Sc (TMHD) as Ga source in a volume ratio of 1:2 3 As a doping source.
S106 growing multiple quantum well layers
Controlling the temperature of the reaction chamber to 700 ℃, the pressure to 200Torr, and introducing NH 3 As N source, N 2 As carrier gas, introducing TEGa as Ga source, introducing TMIn as In source, and growing quantum well layer;
controlling the temperature of the reaction chamber to 800 ℃, keeping the pressure unchanged, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, introducing TEGa as Ga source to grow quantum barrier layer;
the periodically grown quantum well layer and the quantum barrier layer are repeatedly stacked.
S107 growth of a second insertion layer
Controlling the temperature of the reaction chamber to 900 ℃, the pressure to 200Torr, and introducing NH 3 As N source, N 2 And H 2 As carrier gas, N 2 And H 2 Is introduced into TMGa as Ga source and into Lu (TMHD) at a volume ratio of 1:2 3 As a doping source.
S108 growing an electron blocking layer
Controlling the temperature of the reaction chamber to 1000 ℃, the pressure to 200Torr, and introducing NH 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source.
S109 growth of P-type GaN layer
Controlling the temperature of the reaction chamber to 1000 ℃, the pressure to 200Torr, and introducing NH 3 As N source, TMGa as Ga source and CP 2 Mg is used as a doping source.
Example 2
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
wherein the substrate is a sapphire substrate;
the nucleation layer is an AlGaN layer with the thickness of 30nm;
the thickness of the intrinsic GaN layer is 600nm;
the doping concentration of Si in the N-type GaN layer is 7×10 18 cm -3 Thickness is 2 μm;
the multi-quantum well layer is formed by alternately stacking a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, the thickness is 3nm, the quantum barrier layer is a GaN layer, the thickness is 10nm, and the stacking period number is 10;
the first insertion layer is a GaN layer doped with Sc with a doping concentration of 1×10 4 cm -3 The thickness is 50nm;
the second insertion layer is a GaN layer doped with Lu, and the doping concentration of Lu is 1×10 4 cm -3 The thickness is 50nm;
the electron blocking layer is Al 0.45 Ga 0.55 N layers with a thickness of 100nm;
the doping concentration of Mg in the P-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 4nm.
The method for preparing the light-emitting diode epitaxial wafer is the same as that of the embodiment 1.
Example 3
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
wherein the substrate is a sapphire substrate;
the nucleation layer is an AlGaN layer with the thickness of 30nm;
the thickness of the intrinsic GaN layer is 600nm;
the doping concentration of Si in the N-type GaN layer is 7×10 17 cm -3 Thickness is 2 μm;
the multi-quantum well layer is formed by alternately stacking a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, the thickness is 3nm, the quantum barrier layer is a GaN layer, the thickness is 10nm, and the stacking period number is 10;
the first insertion layer is a GaN layer doped with Sc with a doping concentration of 1×10 5 cm -3 The thickness is 50nm;
the second insertion layer is a GaN layer doped with Lu, and the doping concentration of Lu is 1×10 4 cm -3 The thickness is 50nm;
the electron blocking layer is Al 0.45 Ga 0.55 N layers with a thickness of 100nm;
the doping concentration of Mg in the P-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 4nm.
The method for preparing the light-emitting diode epitaxial wafer is the same as that of the embodiment 1.
Example 4
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
wherein the substrate is a sapphire substrate;
the nucleation layer is an AlGaN layer with the thickness of 30nm;
the thickness of the intrinsic GaN layer is 600nm;
the doping concentration of Si in the N-type GaN layer is 7×10 18 cm -3 Thickness is 2 μm;
the multi-quantum well layer is formed by alternately stacking a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, the thickness is 3nm, the quantum barrier layer is a GaN layer, the thickness is 10nm, and the stacking period number is 10;
the first insertion layer is a GaN layer doped with Sc with a doping concentration of 1×10 4 cm -3 The thickness is 50nm;
the second insertion layer is a GaN layer doped with Lu, and the doping concentration of Lu is 5×10 5 cm -3 The thickness is 50nm;
the electron blocking layer is Al 0.3 Ga 0.7 An N layer with the thickness of 40nm;
the doping concentration of Mg in the P-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 4nm.
The method for preparing the light-emitting diode epitaxial wafer is the same as that of the embodiment 1.
Example 5
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
wherein the substrate is a sapphire substrate;
the nucleation layer is an AlGaN layer with the thickness of 30nm;
the thickness of the intrinsic GaN layer is 600nm;
the doping concentration of Si in the N-type GaN layer is 7×10 17 cm -3 Thickness is 2 μm;
the multi-quantum well layer is formed by alternately stacking a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, the thickness is 3nm, the quantum barrier layer is a GaN layer, the thickness is 10nm, and the stacking period number is 10;
the first insertion layer is a GaN layer doped with Sc with a doping concentration of 1×10 5 cm -3 The thickness is 50nm;
the second insertion layer is a GaN layer doped with Lu, and the doping concentration of Lu is 5×10 5 cm -3 The thickness is 50nm;
the electron blocking layer is Al 0.3 Ga 0.7 An N layer with the thickness of 40nm;
the doping concentration of Mg in the P-type GaN layer is 5 multiplied by 10 18 cm -3 The thickness was 4nm.
The method for preparing the light-emitting diode epitaxial wafer is the same as that of the embodiment 1.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the first and second insertion layers are not included. Accordingly, the preparation steps of the above two layers were not included in the preparation method, and the rest was the same as in example 1.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the first insertion layer is not included. Accordingly, the preparation process also did not include the preparation step of the first insertion layer, and the rest was the same as in example 1.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the second insertion layer is not included. Accordingly, the preparation process also did not include the preparation step of the second insertion layer, and the rest was the same as in example 1.
Performance test:
the led epitaxial wafers prepared in examples 1 to 5 and comparative examples 1 to 3 were subjected to a test for photoelectric properties by making a 10mil x 24mil chip,
(1) Brightness: testing brightness on the same LED spot tester under the condition of 200mA driving current;
(2) Antistatic ability: and (3) on the same LED spot tester, carrying out antistatic capability test on the sample by adopting 8KV pulse.
The test results are shown in Table 1.
Table 1 results of testing the photoelectric properties of led epitaxial wafers
Brightness (mW) 8kV antistatic passing rate (%)
Example 1 197.3 97.2
Example 2 197.4 97.4
Example 3 197.9 98.4
Example 4 198.0 98.6
Example 5 198.3 99.2
Comparative example 1 190.7 90.2
Comparative example 2 193.2 92.1
Comparative example 3 192.9 91.6
As can be seen from the results in Table 1, the chips obtained from the LED epitaxial wafer according to example 1 provided by the present invention have improved brightness and antistatic ability compared with the chips obtained from the comparative example. As can be seen from a comparison of example 2 and example 1, the thickness ratio of the first interposer and the second interposer is preferable, and the photoelectric performance of the chip can be further improved. Embodiment 3 can reduce the Si doping concentration in the N-type GaN layer by optimizing the Sc doping concentration in the first insertion layer, thereby improving the lattice matching degree of the first insertion layer and the N-type GaN layer and improving the light emitting efficiency. Example 4 by optimizing the Lu doping concentration in the second insertion layer, the thickness of the electron blocking layer and the Al composition can be reduced, thereby allowing more holes to be injected into the multiple quantum well layer and improving the light emitting efficiency. In summary, the invention improves the brightness and antistatic ability of the chip by growing the first and second insertion layers before and after the multiple quantum well layer.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the thickness of the first interposer layer is 20-200nm; the thickness of the second insertion layer is 20-200nm.
3. The light-emitting diode epitaxial wafer of claim 2, wherein a thickness ratio of the first interposer layer to the second interposer layer is 1 (1-2).
4. The led epitaxial wafer of claim 1, wherein the Sc in the first interposer has a doping concentration of 1 x 10 3 -1×10 6 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of Lu in the second insertion layer is 1×10 3 -1×10 6 cm -3 。
5. The led epitaxial wafer of claim 1, wherein the Sc doping concentration in the first interposer layer is 5 x 10 4 -5×10 5 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of Si in the N-type GaN layer is 5 multiplied by 10 17 -1×10 18 cm -3 。
6. The light-emitting diode epitaxial wafer of claim 1, wherein the doping concentration of Lu in the second insertion layer is 1 x 10 5 -1×10 6 cm -3 ；
The electron blocking layer is Al a Ga 1-a An N layer, wherein a is 0.2-0.4; the thickness of the electron blocking layer is 30-50nm.
7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer on the substrate;
the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.
8. The method of manufacturing a light emitting diode epitaxial wafer of claim 7, wherein the first insertion layer has a growth temperature of 900-1100 ℃ and a growth pressure of 100-300Torr;
the growth temperature of the second insertion layer is 850-950 ℃, and the growth pressure is 100-300Torr.
9. The method for manufacturing a light emitting diode epitaxial wafer according to claim 7, wherein the growth temperature of the N-type GaN layer is 1100-1150 ℃ and the growth pressure is 100-500Torr;
the growth temperature of the electron blocking layer is 900-1100 ℃, and the growth pressure is 100-500Torr.
10. A light emitting diode, characterized in that the light emitting diode comprises a light emitting diode epitaxial wafer according to any one of claims 1-6.
CN202310577589.0A 2023-05-22 2023-05-22 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Pending CN116525734A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682916A (en) * 2023-08-03 2023-09-01 江西兆驰半导体有限公司 Multi-quantum well layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN117293241A (en) * 2023-11-27 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682916A (en) * 2023-08-03 2023-09-01 江西兆驰半导体有限公司 Multi-quantum well layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN116682916B (en) * 2023-08-03 2023-11-21 江西兆驰半导体有限公司 Multi-quantum well layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN117293241A (en) * 2023-11-27 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117293241B (en) * 2023-11-27 2024-01-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

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