CN108550668B - Light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents

Light emitting diode epitaxial wafer and manufacturing method thereof Download PDF

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CN108550668B
CN108550668B CN201810167278.6A CN201810167278A CN108550668B CN 108550668 B CN108550668 B CN 108550668B CN 201810167278 A CN201810167278 A CN 201810167278A CN 108550668 B CN108550668 B CN 108550668B
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semiconductor layer
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CN108550668A (en
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陶章峰
乔楠
余雪平
程金连
胡加辉
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

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Abstract

The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, and belongs to the technical field of semiconductors. The light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electronic barrier layer, a high-temperature P-type semiconductor layer and a contact layer which are sequentially stacked on the substrate, wherein the low-temperature P-type semiconductor layer comprises a plurality of first sublayers and a plurality of second sublayers, the plurality of first sublayers and the plurality of second sublayers are alternately stacked, each first sublayer is a P-type doped aluminum gallium nitride layer, and each second sublayer is a P-type doped gallium nitride layer. According to the invention, the potential energy of the aluminum gallium nitride layer is higher, so that the overflow of electrons is prevented, meanwhile, two-dimensional electron gas is formed between the aluminum gallium nitride layer and the gallium nitride layer, the expansion of holes can be promoted, the injection efficiency of the holes is improved, and the luminous efficiency of the LED is finally improved.

Description

Light emitting diode epitaxial wafer and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. An LED formed by a third-generation wide bandgap semiconductor material represented by gallium nitride (GaN) is a novel efficient, green and environment-friendly solid-state illumination light source, has the advantages of small volume, light weight, long service life, high reliability, low use power consumption and the like, and is widely applied to the fields of illumination, outdoor display, mobile phone backlight sources, power devices and the like.
The conventional GaN-based LED epitaxial wafer comprises a substrate, and a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, a multi-quantum well layer, a low-temperature P-type gallium nitride layer, an electronic barrier layer, a high-temperature P-type gallium nitride layer and a contact layer which are sequentially stacked on the substrate. When current is injected into the GaN-based LED epitaxial wafer, electrons provided by the N-type gallium nitride layer and holes provided by the high-temperature P-type gallium nitride layer migrate to the multi-quantum well layer under the driving of the current, and are radiatively recombined in the multi-quantum well layer, so that light is emitted.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
because the mobility and the migration speed of electrons are superior to those of holes, part of electrons may directly jump over a multi-quantum well layer, and are injected into a high-temperature P-type gallium nitride layer to be non-radiatively compounded with the holes, so that the phenomenon of electron overflow is generated, and the luminous efficiency of the LED is reduced. The electron blocking layer has a high potential barrier and can block electrons from jumping to the high-temperature P-type gallium nitride layer, and if the electron overflow phenomenon is completely eradicated by improving the potential barrier of the electron blocking layer, the electron blocking layer can also possibly block holes provided by the high-temperature P-type gallium nitride layer from jumping to the multiple quantum well layer, so that the injection efficiency of the holes is influenced, and further, the luminous efficiency of the LED is reduced.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide an led epitaxial wafer. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides an led epitaxial wafer, where the led epitaxial wafer includes a substrate, and a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electron blocking layer, a high-temperature P-type semiconductor layer, and a contact layer sequentially stacked on the substrate, where the low-temperature P-type semiconductor layer includes a plurality of first sublayers and a plurality of second sublayers, the plurality of first sublayers and the plurality of second sublayers are alternately stacked, each first sublayer is a P-type doped aluminum gallium nitride layer, and each second sublayer is a P-type doped gallium nitride layer.
Optionally, the thickness of each of the first sub-layers is less than the thickness of the respective second sub-layer.
Preferably, the thickness of each first sub-layer is 10nm to 15nm, and the thickness of each second sub-layer is 15nm to 30 nm.
Optionally, each of the first sub-layers is AlxGa1-xAnd x is more than or equal to 0.01 and less than or equal to 0.05.
Optionally, the content of the aluminum component in each first sublayer gradually increases and then gradually decreases.
Optionally, the number of the first sub-layers and the number of the second sub-layers are both n, n is greater than 6 and less than or equal to 10, and n is an integer.
Optionally, the thickness of the low-temperature P-type semiconductor layer is smaller than that of the electron blocking layer.
In another aspect, an embodiment of the present invention provides a method for manufacturing an epitaxial wafer of a light emitting diode, where the method includes:
providing a substrate;
growing a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electron barrier layer, a high-temperature P-type semiconductor layer and a contact layer on the substrate in sequence;
the low-temperature P-type semiconductor layer comprises a plurality of first sublayers and a plurality of second sublayers, the first sublayers and the second sublayers are alternately stacked, each first sublayer is a P-type doped aluminum gallium nitride layer, and each second sublayer is a P-type doped gallium nitride layer.
Optionally, the growth conditions of each of the first sublayers are the same as the growth conditions of each of the second sublayers, and the growth conditions include a growth temperature and a growth pressure.
Optionally, the growth temperature of the low-temperature P-type semiconductor layer is lower than the growth temperature of the electron blocking layer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the low-temperature P-type semiconductor layer located between the multiple quantum well layer and the electronic barrier layer is formed by alternately laminating the first sublayers and the second sublayers, the first sublayers are P-type doped aluminum gallium nitride layers, the second sublayers are P-type doped gallium nitride layers, and the potential energy of the aluminum gallium nitride layers is higher, so that the low-temperature P-type semiconductor layer is favorable for preventing electron overflow, electrons are prevented from jumping into the high-temperature P-type semiconductor layer to be non-radiatively compounded with holes, the efficiency of radiation compounding of the electrons and the holes in the multiple quantum well layer is increased, and the luminous efficiency of the LED is further improved. And two-dimensional electron gas is formed between the aluminum gallium nitride layer and the gallium nitride layer, so that the expansion of holes can be promoted, the working voltage is reduced, and the injection efficiency of the holes is improved, thereby greatly improving the distribution density of electrons and holes of the multiple quantum well layer, reducing the spatial separation degree of the electrons and the holes, increasing the overlapping of an electron wave function and a hole wave function, further improving the recombination efficiency of the electrons and the holes in the multiple quantum well layer, and finally improving the luminous efficiency of the LED.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a low-temperature P-type semiconductor layer according to an embodiment of the invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer according to an embodiment of the present invention, and referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 10, and a buffer layer 20, an undoped gallium nitride layer 30, an N-type semiconductor layer 40, a multiple quantum well layer 50, a low temperature P-type semiconductor layer 60, an electron blocking layer 70, a high temperature P-type semiconductor layer 80, and a contact layer 90, which are sequentially stacked on the substrate 10.
Fig. 2 is a schematic structural diagram of a low-temperature P-type semiconductor layer according to an embodiment of the present invention, and referring to fig. 2, in this embodiment, a low-temperature P-type semiconductor layer 60 includes a plurality of first sublayers 61 and a plurality of second sublayers 62, the plurality of first sublayers 61 and the plurality of second sublayers 62 are alternately stacked, each first sublayer 61 is a P-type doped aluminum gallium nitride layer, and each second sublayer 62 is a P-type doped gallium nitride layer.
In fig. 2, the first sub-layer and the last second sub-layer are stacked as an example, and in practical applications, the second sub-layer and the last first sub-layer may be stacked, or the first sub-layer and the last first sub-layer may be stacked, or the second sub-layer and the last second sub-layer may be stacked.
According to the embodiment of the invention, the low-temperature P-type semiconductor layer positioned between the multi-quantum well layer and the electron barrier layer is formed by alternately laminating the plurality of first sublayers and the plurality of second sublayers, the first sublayers are P-type doped aluminum gallium nitride layers, the second sublayers are P-type doped gallium nitride layers, and the potential energy of the aluminum gallium nitride layers is higher, so that the low-temperature P-type semiconductor layer is beneficial to preventing the overflow of electrons, the electrons are prevented from jumping into the high-temperature P-type semiconductor layer to be non-radiatively compounded with holes, the efficiency of the radiation compounding of the electrons and the holes in the multi-quantum well layer is increased, and the luminous efficiency of the LED is further improved. And two-dimensional electron gas is formed between the aluminum gallium nitride layer and the gallium nitride layer, so that the expansion of holes can be promoted, the working voltage is reduced, and the injection efficiency of the holes is improved, thereby greatly improving the distribution density of electrons and holes of the multiple quantum well layer, reducing the spatial separation degree of the electrons and the holes, increasing the overlapping of an electron wave function and a hole wave function, further improving the recombination efficiency of the electrons and the holes in the multiple quantum well layer, and finally improving the luminous efficiency of the LED.
Optionally, the thickness of each first sublayer 61 may be smaller than the thickness of each second sublayer 62, and the first sublayers and the second sublayers may be grown under the same growth conditions, so that the process is simplified, and the implementation is facilitated.
Preferably, the thickness of each first sublayer 61 may be between 10nm and 15nm, such as 12 nm; the thickness of each second sub-layer 62 may be between 15nm and 30nm, such as 18 nm. The thin thickness is adopted, so that blocking of hole transition can be avoided, and the influence on the realization effect of the low-temperature P-type semiconductor layer due to the fact that the thickness is too thin can be avoided.
Specifically, the sum of the thicknesses of the plurality of first sub-layers 61 may be 100nm to 150nm, and the sum of the thicknesses of the plurality of second sub-layers 62 may be 150nm to 300 nm.
Alternatively, each first sublayer 61 may be AlxGa1-xN layer, 0.01 ≦ x ≦ 0.05 (preferably, x ≦ 0.03). The content of the aluminum component in the first sublayer is small, so that the blocking of hole transition can be effectively avoided.
Alternatively, the content of the aluminum component in each first sub-layer 61 may be gradually increased and then gradually decreased to form a better match with the adjacent second sub-layer.
Alternatively, the number of the plurality of first sublayers 61 and the plurality of second sublayers 62 may be n, 6 < n ≦ 10 and n is an integer (preferably, n ≦ 8). If the number of the plurality of first sublayers and the plurality of second sublayers is less than 6, the number of the plurality of first sublayers and the number of the plurality of second sublayers may be too small to affect the implementation effect of the low-temperature P-type semiconductor layer; if the number of the plurality of first sub-layers and the plurality of second sub-layers is greater than 10, the production cost may be too high due to the too large number of the plurality of first sub-layers and the plurality of second sub-layers, and blocking may be caused for the transition of holes.
Alternatively, the thickness of the low temperature P-type semiconductor layer 60 may be smaller than that of the electron blocking layer 70, the low temperature P-type semiconductor layer may serve to provide holes and the relatively multi-quantum well layer may be damaged by the electron blocking layer and the high temperature P-type semiconductor layer which are grown at a higher temperature, and the electron blocking layer may also serve to prevent overflow of electrons.
Preferably, the thickness of the low temperature P-type semiconductor layer 60 may be 200nm to 400nm, such as 300 nm; the electron blocking layer 70 may have a thickness of 300nm to 500nm, such as 400 nm.
Alternatively, the doping concentration of the P-type dopant in the low-temperature P-type semiconductor layer 60 may be greater than the doping concentration of the P-type dopant in the high-temperature P-type semiconductor layer 80.
Further, the doping concentration of the P-type dopant in the electron blocking layer 70 may be greater than that of the high temperature P-type semiconductor layer 80
Alternatively, the doping concentration of the P-type dopant in the low-temperature P-type semiconductor layer 60 may be less than that of the P-type dopant in the contact layer 90.
Further, the doping concentration of the P-type dopant in the electron blocking layer 70 may be less than the doping concentration of the P-type dopant in the contact layer 90.
Specifically, the substrate 10 may be a sapphire substrate. The buffer layer 20 may be an aluminum nitride layer or a gallium nitride layer. The N-type semiconductor layer 40 may be an N-type doped gallium nitride layer. The multiple quantum well layer 50 may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the quantum well may be an indium gallium nitride layer and the quantum barrier may be a gallium nitride layer. The electron blocking layer can be a P-type doped aluminum gallium nitride layer, the high-temperature P-type semiconductor layer can be a P-type doped gallium nitride layer, and the contact layer can be a P-type doped indium gallium nitride layer.
More specifically, the thickness of the buffer layer 20 may be 15nm to 35 nm. The thickness of the undoped gallium nitride layer 30 may be 1 μm to 3 μm. The thickness of the N-type semiconductor layer 40 may be 1 to 2 μm. The thickness of the multiple quantum well layer may be 100nm to 150 nm. The thickness of the high-temperature P-type semiconductor layer 80 may be 100nm to 300 nm. The thickness of the contact layer 90 may be 50nm to 100 nm.
The embodiment of the invention provides a method for manufacturing an epitaxial wafer of a light-emitting diode, which is suitable for manufacturing the epitaxial wafer of the light-emitting diode provided by the first embodiment of the invention. Fig. 3 is a flowchart of a manufacturing method according to an embodiment of the present invention, and referring to fig. 3, the manufacturing method includes:
step 101: a substrate is provided.
Step 102: a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electron barrier layer, a high-temperature P-type semiconductor layer and a contact layer are sequentially grown on a substrate.
In this embodiment, the low-temperature P-type semiconductor layer includes a plurality of first sublayers and a plurality of second sublayers, the plurality of first sublayers and the plurality of second sublayers are alternately stacked, each first sublayer is a P-type doped aluminum gallium nitride layer, and each second sublayer is a P-type doped gallium nitride layer.
According to the embodiment of the invention, the low-temperature P-type semiconductor layer positioned between the multi-quantum well layer and the electron barrier layer is formed by alternately laminating the plurality of first sublayers and the plurality of second sublayers, the first sublayers are P-type doped aluminum gallium nitride layers, the second sublayers are P-type doped gallium nitride layers, and the potential energy of the aluminum gallium nitride layers is higher, so that the low-temperature P-type semiconductor layer is beneficial to preventing the overflow of electrons, the electrons are prevented from jumping into the high-temperature P-type semiconductor layer to be non-radiatively compounded with holes, the efficiency of the radiation compounding of the electrons and the holes in the multi-quantum well layer is increased, and the luminous efficiency of the LED is further improved. And two-dimensional electron gas is formed between the aluminum gallium nitride layer and the gallium nitride layer, so that the expansion of holes can be promoted, the working voltage is reduced, and the injection efficiency of the holes is improved, thereby greatly improving the distribution density of electrons and holes of the multiple quantum well layer, reducing the spatial separation degree of the electrons and the holes, increasing the overlapping of an electron wave function and a hole wave function, further improving the recombination efficiency of the electrons and the holes in the multiple quantum well layer, and finally improving the luminous efficiency of the LED.
Alternatively, the growth conditions of each first sublayer may be the same as those of the respective second sublayers, the growth conditions including growth temperature and growth pressure. The process is simplified and the realization is convenient.
Optionally, the growth temperature of the low-temperature P-type semiconductor layer may be lower than the growth temperature of the electron blocking layer, and the multi-quantum well layer may be prevented from being damaged by the electron blocking layer with a higher growth temperature.
Specifically, this step 102 may include:
firstly, controlling the temperature to be 400-600 ℃, the pressure to be 400-600 torr, and growing a buffer layer with the thickness of 15-35 nm on a substrate.
And secondly, controlling the temperature to be 1100-1150 ℃ and the pressure to be 100-200 torr, and growing an undoped gallium nitride layer with the thickness of 1-3 mu m on the buffer layer.
Thirdly, controlling the temperature to be 1100-1150 ℃ and the pressure to be 200torr, and growing an N-type semiconductor layer with the thickness of 1-2 microns on the undoped gallium nitride layer.
Fourthly, controlling the temperature to be 700-900 ℃ and the pressure to be 200torr, and growing a multi-quantum well layer with the thickness of 100-150 nm on the N-type semiconductor layer.
Fifthly, controlling the temperature to be 700-800 ℃ and the pressure to be 200torr, and growing a low-temperature P-type semiconductor layer with the thickness of 200-400 nm on the multi-quantum well layer.
Sixthly, controlling the temperature to be 950-1000 ℃ and the pressure to be 200torr, and growing an electron blocking layer with the thickness of 300-500 nm on the low-temperature P-type semiconductor layer.
And seventhly, controlling the temperature to be 950-1000 ℃ and the pressure to be 200torr, and growing a high-temperature P-type semiconductor layer with the thickness of 100-300 nm on the electron blocking layer.
And eighthly, controlling the temperature to be 950-1000 ℃ and the pressure to be 200torr, and growing a contact layer with the thickness of 50-100 nm on the high-temperature P-type semiconductor layer.
Optionally, before the first step, the manufacturing method may further include:
controlling the temperature to be 1000-1100 ℃ and the pressure to be 200-500 torr, and preprocessing the substrate for 10min to clean the surface of the substrate.
Specifically, the pretreatment may include annealing the substrate in a hydrogen atmosphere and then performing a nitriding treatment.
Optionally, after the first step, the manufacturing method may further include:
the temperature is controlled to be 1000-1200 ℃, the pressure is 400-600 Torr, and the buffer layer is subjected to in-situ annealing treatment for 5-10 minutes.
Optionally, after the eighth step, the manufacturing method may further include:
the temperature is controlled to be 650-850 ℃, and annealing treatment is carried out for 5-15 minutes in the nitrogen atmosphere.
In particular implementations, the substrate is typically placed on a graphite tray and fed into the reaction chamber for epitaxial material growth, and thus the temperature and pressure controlled during the growth process described above are actually the temperature and pressure within the reaction chamber. Specifically, trimethyl gallium or trimethyl ethyl is used as a gallium source, high-purity nitrogen is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, an N-type dopant is selected from silane, and a P-type dopant is selected from magnesium diclocide.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (6)

1. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electronic barrier layer, a high-temperature P-type semiconductor layer and a contact layer which are sequentially stacked on the substrate, and is characterized in that the low-temperature P-type semiconductor layer comprises a plurality of first sublayers and a plurality of second sublayers, the plurality of first sublayers and the plurality of second sublayers are alternately stacked, and each first sublayer is P-type doped AlxGa1-xThe x is more than or equal to 0.01 and less than or equal to 0.05, and each second sublayer is a P-type doped gallium nitride layer; the thickness of each first sublayer is smaller than that of each second sublayer, the thickness of each first sublayer is 10 nm-15 nm, and the thickness of each second sublayer is 15 nm-30 nm; the growth temperature of the low-temperature P-type semiconductor layer is lower than that of the electron blocking layer.
2. The light-emitting diode epitaxial wafer according to claim 1, wherein the content of the aluminum component in each first sub-layer gradually increases and then gradually decreases.
3. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein the number of the plurality of first sub-layers and the number of the plurality of second sub-layers are both n, 6 < n ≦ 10, and n is an integer.
4. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein the thickness of the low-temperature P-type semiconductor layer is smaller than that of the electron blocking layer.
5. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a buffer layer, an undoped gallium nitride layer, an N-type semiconductor layer, a multi-quantum well layer, a low-temperature P-type semiconductor layer, an electron barrier layer, a high-temperature P-type semiconductor layer and a contact layer on the substrate in sequence;
the low-temperature P-type semiconductor layer comprises a plurality of first sublayers and a plurality of second sublayers, the first sublayers and the second sublayers are alternately stacked, and each first sublayer is P-type doped AlxGa1-xThe x is more than or equal to 0.01 and less than or equal to 0.05, and each second sublayer is a P-type doped gallium nitride layer; the thickness of each first sublayer is smaller than that of each second sublayer, the thickness of each first sublayer is 10 nm-15 nm, and the thickness of each second sublayer is 15 nm-30 nm; the growth temperature of the low-temperature P-type semiconductor layer is lower than that of the electron blocking layer.
6. The method of claim 5, wherein the growth conditions of each of the first sub-layers are the same as the growth conditions of the respective second sub-layers, the growth conditions including growth temperature and growth pressure.
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CN113990990B (en) * 2021-09-01 2023-05-09 华灿光电（浙江）有限公司 Micro light-emitting diode epitaxial wafer and manufacturing method thereof
CN115132892B (en) * 2021-12-30 2024-02-27 淮安澳洋顺昌光电技术有限公司 Light-emitting diode epitaxial structure and light-emitting diode

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