CN108550668A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- CN108550668A CN108550668A CN201810167278.6A CN201810167278A CN108550668A CN 108550668 A CN108550668 A CN 108550668A CN 201810167278 A CN201810167278 A CN 201810167278A CN 108550668 A CN108550668 A CN 108550668A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses a kind of LED epitaxial slices and preparation method thereof, belong to technical field of semiconductors.The LED epitaxial slice includes substrate and stacks gradually buffer layer, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer, low temperature p type semiconductor layer, electronic barrier layer, high temperature p type semiconductor layer, contact layer over the substrate, the low temperature p type semiconductor layer includes multiple first sublayers and multiple second sublayers, the multiple first sublayer and the multiple alternately laminated setting of second sublayer, each first sublayer is the gallium nitride layer of p-type doping, and each second sublayer is the gallium nitride layer of p-type doping.The present invention is higher by the potential energy of gallium nitride layer, prevents electronics overflow, while two-dimensional electron gas is advantageously formed between gallium nitride layer and gallium nitride layer, can promote the extension in hole, improves the injection efficiency in hole, the final luminous efficiency for improving LED.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of LED epitaxial slice and preparation method thereof.
Background technology
Light emitting diode (English：Light Emitting Diode, referred to as：LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.With the LED that the third generation semiconductor material with wide forbidden band that gallium nitride (GaN) is representative is formed, be it is a kind of efficiently, green,
The New Solid lighting source of environmental protection has many advantages, such as small, light-weight, long lifespan, reliability height, using low in energy consumption,
The fields such as illumination, outdoor display, cell phone back light source, power device are widely used.
Existing GaN base LED epitaxial wafer includes substrate and stacks gradually buffer layer, undoped gallium nitride on substrate
Layer, n type gallium nitride layer, multiple quantum well layer, low temperature p-type gallium nitride layer, electronic barrier layer, high temperature p-type gallium nitride layer, contact layer.
When electric current injects in GaN base LED epitaxial wafer, the hole for electronics and high temperature p-type the gallium nitride layer offer that n type gallium nitride layer provides
It under the driving of electric current, migrates, and carry out radiation recombination in multiple quantum well layer, and then shines to multiple quantum well layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems：
Since the mobility and migration velocity of electronics are superior to hole, part electronics may directly be jumped over Multiple-quantum
Well layer is injected in high temperature p-type gallium nitride layer and non-radiative recombination occurs with hole, and there is a phenomenon where electronics overflows, reduce the hair of LED
Light efficiency.Electronic barrier layer has higher potential barrier, can stop electron transition to high temperature p-type gallium nitride layer, if by carrying
The potential barrier of high electronic barrier layer prevents the generation of electronics overflow phenomena completely, then electronic barrier layer may while also can be to high temperature P
The hole transition that type gallium nitride layer provides causes to stop to multiple quantum well layer, influences the injection efficiency in hole, and then reduction LED
Luminous efficiency.
Invention content
In order to solve problems in the prior art, an embodiment of the present invention provides a kind of LED epitaxial slices.The skill
Art scheme is as follows：
On the one hand, an embodiment of the present invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets
Include substrate and stack gradually buffer layer over the substrate, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer,
Low temperature p type semiconductor layer, electronic barrier layer, high temperature p type semiconductor layer, contact layer, the low temperature p type semiconductor layer includes multiple
First sublayer and multiple second sublayers, the multiple first sublayer and the multiple alternately laminated setting of second sublayer, Mei Gesuo
The gallium nitride layer that the first sublayer is p-type doping is stated, each second sublayer is the gallium nitride layer of p-type doping.
Optionally, the thickness of each first sublayer is less than the thickness of each second sublayer.
Preferably, the thickness of each first sublayer is 10nm~15nm, and the thickness of each second sublayer is
15nm~30nm.
Optionally, each first sublayer is AlxGa1-xN layers, 0.01≤x≤0.05.
Optionally, first gradual increase is gradually reduced the content of aluminium component again in each first sublayer.
Optionally, the quantity of the multiple first sublayer and the multiple second sublayer is n, and 6 n≤10 ＜ and n are whole
Number.
Optionally, the thickness of the low temperature p type semiconductor layer is less than the thickness of the electronic barrier layer.
On the other hand, an embodiment of the present invention provides a kind of production method of LED epitaxial slice, the making sides
Method includes：
One substrate is provided；
Grown buffer layer, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer, low temperature successively over the substrate
P type semiconductor layer, electronic barrier layer, high temperature p type semiconductor layer, contact layer；
Wherein, the low temperature p type semiconductor layer includes multiple first sublayers and multiple second sublayers, the multiple first son
Layer and the multiple alternately laminated setting of second sublayer, each first sublayer are the gallium nitride layer of p-type doping, each described
Second sublayer is the gallium nitride layer of p-type doping.
Optionally, the growth conditions of each first sublayer is identical as each growth conditions of second sublayer, institute
It includes growth temperature and growth pressure to state growth conditions.
Optionally, the growth temperature of the low temperature p type semiconductor layer is less than the growth temperature of the electronic barrier layer.
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is：
It is located at multiple quantum well layer and electronic barrier layer by alternately laminated formed of multiple first sublayers and multiple second sublayers
Between low temperature p type semiconductor layer, the first sublayer be p-type doping gallium nitride layer, the second sublayer be p-type doping gallium nitride
Layer, since the potential energy of gallium nitride layer is higher, low temperature p type semiconductor layer is conducive to prevent electronics overflow, avoids electron transition
Non-radiative recombination is carried out with hole in high temperature p type semiconductor layer, increases electrons and holes and is radiated in multiple quantum well layer
Compound efficiency, and then improve the luminous efficiency of LED.And two-dimentional electricity is advantageously formed between gallium nitride layer and gallium nitride layer
Sub- gas can promote the extension in hole, operating voltage be reduced, while improving the injection efficiency in hole, to greatly improve volume
The distribution density of sub- well layer electrons and holes reduces the degree that is spatially separating of electrons and holes, increases electron wave function and hole
The overlapping of wave function further increases combined efficiency of the electrons and holes in multiple quantum well layer, the final luminous effect for improving LED
Rate.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of low temperature p type semiconductor layer provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of the production method of LED epitaxial slice provided in an embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
An embodiment of the present invention provides a kind of LED epitaxial slice, Fig. 1 is provided in an embodiment of the present invention luminous two
The structural schematic diagram of pole pipe epitaxial wafer, referring to Fig. 1, which includes substrate 10 and is sequentially laminated on substrate
Buffer layer 20, undoped gallium nitride layer 30, n type semiconductor layer 40, multiple quantum well layer 50, low temperature p type semiconductor layer 60 on 10,
Electronic barrier layer 70, high temperature p type semiconductor layer 80, contact layer 90.
Fig. 2 is the structural schematic diagram of low temperature p type semiconductor layer provided in an embodiment of the present invention, referring to Fig. 2, in the present embodiment
In, low temperature p type semiconductor layer 60 includes multiple first sublayers 61 and multiple second sublayers 62, multiple first sublayers 61 and multiple the
Two sublayers, 62 alternately laminated setting, each first sublayer 61 are the gallium nitride layer of p-type doping, and each second sublayer 62 is mixed for p-type
Miscellaneous gallium nitride layer.
It should be noted that actually answered for the first sublayer and the second sublayer of last stacking are laminated at first in Fig. 2
Can also be the second sublayer and the first sublayer of last stacking to be laminated at first, or the first sublayer and final layer are laminated at first in
Folded first sublayer, or the second sublayer and the second sublayer of last stacking are laminated at first.
The embodiment of the present invention is located at multiple quantum well layer by alternately laminated formed of multiple first sublayers and multiple second sublayers
Low temperature p type semiconductor layer between electronic barrier layer, the first sublayer are the gallium nitride layer of p-type doping, and the second sublayer is mixed for p-type
Miscellaneous gallium nitride layer, since the potential energy of gallium nitride layer is higher, low temperature p type semiconductor layer is conducive to prevent electronics overflow, keeps away
Exempt to carry out non-radiative recombination with hole in electron transition to high temperature p type semiconductor layer, increases electrons and holes in multiple quantum well layer
It is middle to carry out the efficiency of radiation recombination, and then improve the luminous efficiency of LED.And be conducive between gallium nitride layer and gallium nitride layer
Two-dimensional electron gas is formed, the extension in hole can be promoted, reduces operating voltage, while improving the injection efficiency in hole, to big
The big distribution density for improving multiple quantum well layer electrons and holes, reduces the degree that is spatially separating of electrons and holes, increases electron waves
The overlapping of function and hole wave functions further increases combined efficiency of the electrons and holes in multiple quantum well layer, final to improve
The luminous efficiency of LED.
Optionally, the thickness of each first sublayer 61 can be less than the thickness of each second sublayer 62, may be used identical
One sublayer of growth conditions growth regulation and the second sublayer, simplify technique, facilitate realization.
Preferably, the thickness of each first sublayer 61 can be 10nm~15nm, such as 12nm；The thickness of each second sublayer 62
Degree can be 15nm~30nm, such as 18nm.It using relatively thin thickness, can cause to stop to avoid to the transition in hole, simultaneously also
It can be to avoid thickness is too thin and influences the realization effect of low temperature p type semiconductor layer.
Specifically, the sum of thickness of multiple first sublayers 61 can be 100nm~150nm, the thickness of multiple second sublayers 62
The sum of degree can be 150nm~300nm.
Optionally, each first sublayer 61 can be AlxGa1-xN layers, 0.01≤x≤0.05 (preferably x=0.03).First
The content of aluminium component is smaller in sublayer, it is possible to prevente effectively from causing to stop to the transition in hole.
Optionally, the content of aluminium component first can gradually increase and be gradually reduced again in each first sublayer 61, with it is adjacent
The second sublayer form preferable matching.
Optionally, the quantity of multiple first sublayers 61 and multiple second sublayers 62 can be n, and 6 n≤10 ＜ and n are whole
Number (preferably n=8).If the quantity of multiple first sublayers and multiple second sublayers is less than 6, may due to multiple first sublayers and
The quantity of multiple second sublayers is too small and influences the realization effect of low temperature p type semiconductor layer；If multiple first sublayers and multiple
The quantity of two sublayers is more than 10, then may cause to be produced into since the quantity of multiple first sublayers and multiple second sublayers is too many
Ben Taigao, while being also possible to that the transition in hole is caused to stop.
Optionally, the thickness of low temperature p type semiconductor layer 60 can be less than the thickness of electronic barrier layer 70, and low temperature p-type is partly led
Body layer, which can play, to be provided hole and compares multiple quantum well layer by the higher electronic barrier layer of growth temperature and high temperature P-type semiconductor
The effect of damage layer, while electronic barrier layer can also play the role of preventing electronics overflow.
Preferably, the thickness of low temperature p type semiconductor layer 60 can be with 200nm~400nm, such as 300nm；Electronic barrier layer 70
Thickness can be 300nm~500nm, such as 400nm.
Optionally, the doping concentration of P-type dopant can be more than high temperature p type semiconductor layer in low temperature p type semiconductor layer 60
The doping concentration of P-type dopant in 80.
Further, the doping concentration of P-type dopant can be more than in high temperature p type semiconductor layer 80 in electronic barrier layer 70
The doping concentration of P-type dopant
Optionally, the doping concentration of P-type dopant can be mixed less than p-type in contact layer 90 in low temperature p type semiconductor layer 60
Miscellaneous dose of doping concentration.
Further, the doping concentration of P-type dopant can be less than P-type dopant in contact layer 90 in electronic barrier layer 70
Doping concentration.
Specifically, substrate 10 can be Sapphire Substrate.Buffer layer 20 can be aln layer or gallium nitride layer.N-type
Semiconductor layer 40 can be the gallium nitride layer of n-type doping.Multiple quantum well layer 50 may include that multiple Quantum Well and multiple quantum are built,
Multiple Quantum Well and multiple quantum are built alternately laminated；Quantum Well can be indium gallium nitrogen layer, and quantum base can be gallium nitride layer.Electronics
Barrier layer can be the gallium nitride layer of p-type doping, and high temperature p type semiconductor layer can be the gallium nitride layer of p-type doping, and contact layer can
Think the indium gallium nitrogen layer of p-type doping.
More specifically, the thickness of buffer layer 20 can be 15nm~35nm.The thickness of undoped gallium nitride layer 30 can be 1
μm~3 μm.The thickness of n type semiconductor layer 40 can be 1 μm~2 μm.The thickness of multiple quantum well layer can be 100nm~150nm.
The thickness of high temperature p type semiconductor layer 80 can be 100nm~300nm.The thickness of contact layer 90 can be 50nm~100nm.
An embodiment of the present invention provides a kind of production methods of LED epitaxial slice, are carried suitable for making embodiment one
The LED epitaxial slice of confession.Fig. 3 is the flow chart of production method provided in an embodiment of the present invention, referring to Fig. 3, the making side
Method includes：
Step 101：One substrate is provided.
Step 102：On substrate successively grown buffer layer, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer,
Low temperature p type semiconductor layer, electronic barrier layer, high temperature p type semiconductor layer, contact layer.
In the present embodiment, low temperature p type semiconductor layer includes multiple first sublayers and multiple second sublayers, multiple first sons
Layer and multiple alternately laminated settings of second sublayer, each first sublayer are the gallium nitride layer of p-type doping, and each second sublayer is P
The gallium nitride layer of type doping.
The embodiment of the present invention is located at multiple quantum well layer by alternately laminated formed of multiple first sublayers and multiple second sublayers
Low temperature p type semiconductor layer between electronic barrier layer, the first sublayer are the gallium nitride layer of p-type doping, and the second sublayer is mixed for p-type
Miscellaneous gallium nitride layer, since the potential energy of gallium nitride layer is higher, low temperature p type semiconductor layer is conducive to prevent electronics overflow, keeps away
Exempt to carry out non-radiative recombination with hole in electron transition to high temperature p type semiconductor layer, increases electrons and holes in multiple quantum well layer
It is middle to carry out the efficiency of radiation recombination, and then improve the luminous efficiency of LED.And be conducive between gallium nitride layer and gallium nitride layer
Two-dimensional electron gas is formed, the extension in hole can be promoted, reduces operating voltage, while improving the injection efficiency in hole, to big
The big distribution density for improving multiple quantum well layer electrons and holes, reduces the degree that is spatially separating of electrons and holes, increases electron waves
The overlapping of function and hole wave functions further increases combined efficiency of the electrons and holes in multiple quantum well layer, final to improve
The luminous efficiency of LED.
Optionally, the growth conditions of each first sublayer can be identical as each growth conditions of second sublayer, grows item
Part includes growth temperature and growth pressure.Simplify technique, facilitates realization.
Optionally, the growth temperature of low temperature p type semiconductor layer can be less than the growth temperature of electronic barrier layer, can be to avoid
Multiple quantum well layer is by the higher electronic blocking damage layer of growth temperature.
Specifically, which may include：
The first step, controlled at 400 DEG C~600 DEG C, pressure is 400torr~600torr, on substrate growth thickness
For the buffer layer of 15nm~35nm.
Second step, controlled at 1100 DEG C~1150 DEG C, pressure is 100torr~200torr, is grown on the buffer layer
The undoped gallium nitride layer that thickness is 1 μm~3 μm.
Third walks, and controlled at 1100 DEG C~1150 DEG C, pressure 200torr is grown on undoped gallium nitride layer
The n type semiconductor layer that thickness is 1 μm~2 μm.
4th step, controlled at 700 DEG C~900 DEG C, pressure 200torr, growth thickness is on n type semiconductor layer
The multiple quantum well layer of 100nm~150nm.
5th step, controlled at 700 DEG C~800 DEG C, pressure 200torr, growth thickness is on multiple quantum well layer
The low temperature p type semiconductor layer of 200nm~400nm.
6th step, controlled at 950 DEG C~1000 DEG C, pressure 200torr is grown on low temperature p type semiconductor layer
Thickness is the electronic barrier layer of 300nm~500nm.
7th step, controlled at 950 DEG C~1000 DEG C, pressure 200torr, growth thickness is on electronic barrier layer
The high temperature p type semiconductor layer of 100nm~300nm.
8th step, controlled at 950 DEG C~1000 DEG C, pressure 200torr is grown on high temperature p type semiconductor layer
Thickness is the contact layer of 50nm~100nm.
Optionally, before the first step, which can also include：
Controlled at 1000 DEG C~1100 DEG C, pressure is 200torr~500torr, and the pre- place of 10min is carried out to substrate
Reason, to clean the surface of substrate.
Specifically, pretreatment may include first substrate being annealed in hydrogen atmosphere, then carry out nitrogen treatment.
Optionally, after the first step, which can also include：
Controlled at 1000 DEG C~1200 DEG C, pressure is 400Torr~600Torr, and 5 minutes~10 are carried out to buffer layer
The in-situ annealing processing of minute.
Optionally, after the 8th step, which can also include：
Controlled at 650 DEG C~850 DEG C, 5 minutes~15 minutes annealings are carried out in nitrogen atmosphere.
It is typically to place the substrate on graphite pallet the life be sent into reaction chamber and carry out epitaxial material in specific implementation
It is long, therefore the temperature and pressure controlled in above-mentioned growth course actually refers to the temperature and pressure in reaction chamber.Specifically, it adopts
Use trimethyl gallium or trimethyl second as gallium source, high pure nitrogen is as nitrogen source, and trimethyl indium is as indium source, and trimethyl aluminium is as aluminium
Source, N type dopant select silane, P-type dopant to select two luxuriant magnesium.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate and is sequentially laminated on the substrate
On buffer layer, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer, low temperature p type semiconductor layer, electronic barrier layer,
High temperature p type semiconductor layer, contact layer, which is characterized in that the low temperature p type semiconductor layer includes multiple first sublayers and multiple
Two sublayers, the multiple first sublayer and the multiple alternately laminated setting of second sublayer, each first sublayer are mixed for p-type
Miscellaneous gallium nitride layer, each second sublayer are the gallium nitride layer of p-type doping.
2. LED epitaxial slice according to claim 1, which is characterized in that the thickness of each first sublayer is small
In the thickness of each second sublayer.
3. LED epitaxial slice according to claim 2, which is characterized in that each the thickness of first sublayer is
The thickness of 10nm~15nm, each second sublayer are 15nm~30nm.
4. according to claims 1 to 3 any one of them LED epitaxial slice, which is characterized in that each first son
Layer is AlxGa1-xN layers, 0.01≤x≤0.05.
5. according to claims 1 to 3 any one of them LED epitaxial slice, which is characterized in that each first son
The content of aluminium component first gradually increases and is gradually reduced again in layer.
6. according to claims 1 to 3 any one of them LED epitaxial slice, which is characterized in that the multiple first son
The quantity of layer and the multiple second sublayer is n, and 6 n≤10 ＜ and n are integer.
7. according to claims 1 to 3 any one of them LED epitaxial slice, which is characterized in that the low temperature p-type is partly led
The thickness of body layer is less than the thickness of the electronic barrier layer.
8. a kind of production method of LED epitaxial slice, which is characterized in that the production method includes：
One substrate is provided；
Grown buffer layer, undoped gallium nitride layer, n type semiconductor layer, multiple quantum well layer, low temperature p-type successively over the substrate
Semiconductor layer, electronic barrier layer, high temperature p type semiconductor layer, contact layer；
Wherein, the low temperature p type semiconductor layer includes multiple first sublayers and multiple second sublayers, the multiple first sublayer and
The multiple alternately laminated setting of second sublayer, the gallium nitride layer that each first sublayer is adulterated for p-type, each described second
Sublayer is the gallium nitride layer of p-type doping.
9. production method according to claim 8, which is characterized in that the growth conditions of each first sublayer with it is each
The growth conditions of second sublayer is identical, and the growth conditions includes growth temperature and growth pressure.
10. production method according to claim 8 or claim 9, which is characterized in that the growth temperature of the low temperature p type semiconductor layer
Growth temperature of the degree less than the electronic barrier layer.
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| CN108695415A (en) * | 2018-03-28 | 2018-10-23 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its growing method |
| CN108695415B (en) * | 2018-03-28 | 2020-03-27 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and growth method thereof |
| CN113990990A (en) * | 2021-09-01 | 2022-01-28 | 华灿光电（浙江）有限公司 | Micro light-emitting diode epitaxial wafer and manufacturing method thereof |
| CN113990990B (en) * | 2021-09-01 | 2023-05-09 | 华灿光电（浙江）有限公司 | Micro light-emitting diode epitaxial wafer and manufacturing method thereof |
| WO2023124552A1 (en) * | 2021-12-30 | 2023-07-06 | 淮安澳洋顺昌光电技术有限公司 | Light-emitting diode epitaxial structure and light-emitting diode |
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