CN108091740A - A kind of LED epitaxial slice and its manufacturing method - Google Patents

A kind of LED epitaxial slice and its manufacturing method Download PDF

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CN108091740A
CN108091740A CN201711089437.7A CN201711089437A CN108091740A CN 108091740 A CN108091740 A CN 108091740A CN 201711089437 A CN201711089437 A CN 201711089437A CN 108091740 A CN108091740 A CN 108091740A
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thickness
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electronic barrier
layers
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CN108091740B (en
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苏晨
王慧
肖扬
吕蒙普
胡加辉
李鹏
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HC Semitek Zhejiang Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

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Abstract

The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.LED epitaxial slice includes substrate and stacks gradually buffer layer, GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer, p-type contact layer over the substrate, insert layer is AlN layers, AlN layers of thickness is 1~30nm, low temperature P-type layer is AlInGaN layers, and the thickness of electronic barrier layer is 8~40nm.It is engaged by AlN layers and AlInGaN layers, P layers of energy band of optimization, it forms more conduction band barriers and stops electron transfer, so as to which the thickness of electronic barrier layer is thinned, prevent electronic barrier layer is thicker from can generate a high Valence-band Offsets obstruction hole to multiple quantum well layer migration, and then improve electronics and the recombination probability in hole, the luminous efficiency of LED is improved, and by the optimization of P layers of potential barrier, the thickness of insert layer and P-type layer can be controlled, so as to improve light extraction efficiency, device luminous intensity is improved.

Description

A kind of LED epitaxial slice and its manufacturing method
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of LED epitaxial slice and its manufacturing method.
Background technology
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.As A kind of efficient, environmental protection, green New Solid lighting source, are widely applied rapidly, such as traffic lights, automobile Inside and outside lamp, landscape light in city, cell phone back light source etc., it is the target that LED is constantly pursued to improve chip light emitting efficiency.
Existing LED includes the GaN base epitaxial layer of substrate and setting on substrate, and GaN base epitaxial layer includes being sequentially laminated on Buffer layer, GaN layer, N-type layer, multiple quantum well layer, electronic barrier layer and P-type layer on substrate.
In the implementation of the present invention, inventor has found that the prior art has at least the following problems:
Since the mobility of electronics in GaN material is significantly larger than the mobility in hole, it is be easy to cause under high current density Electronics overflow, so as to weaken the recombination luminescence probability of carrier, existing LED is by setting certain thickness electronic barrier layer to hinder The migration of electronics is kept off, but in order to stop electron transfer to P-type layer, electronic barrier layer is commonly designed thicker (to generally reach 50nm), thicker electronic barrier layer can cause the polarization of storeroom and the effect of stress, while can generate a high valence band band Rank hinders hole to be migrated to multiple quantum well layer, is reduced so as to cause Carrier recombination luminous efficiency.
The content of the invention
In order to solve the problems, such as that the recombination luminescence efficiency of carrier in the prior art is low, an embodiment of the present invention provides one kind LED epitaxial slice and its manufacturing method.The technical solution is as follows:
On the one hand, the present invention provides a kind of LED epitaxial slice, the LED epitaxial slice include substrate, And stack gradually buffer layer, GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electronics over the substrate Barrier layer, high temperature P-type layer and p-type contact layer,
The insert layer is AlN layers, and thickness AlN layers described is 1~30nm, and the low temperature P-type layer is AlInGaN layers, The thickness of the electronic barrier layer is 8~40nm.
Further, the overall thickness of the insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer For 40~150nm.
Further, the electronic barrier layer be AlGaN layer or AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, One kind in AlGaN/InAlN superlattice structures.
Further, thickness AlN layers described is 2nm, and the thickness of the electronic barrier layer is 25nm.
On the other hand, the present invention provides a kind of manufacturing method of LED epitaxial slice, the manufacturing method includes:
One substrate is provided;
Grown buffer layer, GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electricity successively over the substrate Sub- barrier layer, high temperature P-type layer and p-type contact layer, the insert layer are AlN layers, and thickness AlN layers described is 1~30nm, described Low temperature P-type layer is AlInGaN layers, and the thickness of the electronic barrier layer is 8~40nm.
Further, growth temperature AlN layers described is 800~900 DEG C.
Further, growth pressure AlN layers described is 150~250torr.
Further, the overall thickness of the insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer For 40~150nm.
Further, the electronic barrier layer be AlGaN layer or AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, One kind in AlGaN/InAlN superlattice structures.
Further, thickness AlN layers described is 2nm, and the thickness of the electronic barrier layer is 25nm.
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is:
Pass through between multiple quantum well layer and P-type layer set one AlN layers, on the one hand, AlN layers can be formed it is one higher Potential barrier energy level, stop the migration of electronics;On the other hand, AlN layers of thickness is 1~30nm, due to AlN layers of thinner thickness, Stress field caused by adaptation stress between lattice is smaller, so as to improve being efficiently injected into for hole.Low temperature P-type layer is AlInGaN layers, AlInGaN layers with GaN Lattice Matchings, it is possible to reduce due to lattice mismatch generate stress field, while with it is existing The low temperature P-type layer of InGaN materials in LED is compared, and AlInGaN layers of energy level is higher, can further stop moving for electronics It moves.It is engaged by AlN layers and AlInGaN layers, the effect of the electronic barrier layer of a part can be shared, so as to which electricity is thinned The thickness on sub- barrier layer so that the thickness of electronic barrier layer is in the range of 8~40nm, compared to the electronic barrier layer in existing LED Thickness substantially reduces, and the high Valence-band Offsets for avoiding the blocked up generation of electronic barrier layer hinder hole to be migrated to multiple quantum well layer, into And electronics and the recombination probability in hole are improved, improve the luminous efficiency of LED.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings Attached drawing.
Fig. 1 is a kind of structure diagram of LED epitaxial slice provided in an embodiment of the present invention;
Fig. 2 is a kind of method flow diagram of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
Embodiment one
An embodiment of the present invention provides a kind of light emitting diode, Fig. 1 is a kind of light-emitting diodes provided in an embodiment of the present invention The structure diagram of pipe epitaxial wafer, as shown in Figure 1, the light emitting diode includes substrate 1 and stacks gradually on substrate 1 Buffer layer 2, GaN layer 3, N-type layer 4, multiple quantum well layer 5, insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature P-type layer 9, P Type contact layer 10.
Wherein, insert layer 6 is AlN layers, and AlN layers of thickness is 1~30nm, and low temperature P-type layer 7 is AlInGaN layers, electronics resistance The thickness of barrier 8 is 8~40nm.
Preferably, AlN layers of thickness is 2nm, and the thickness of electronic barrier layer 8 is 25nm.The illumination effect of LED is most at this time It is good.
The embodiment of the present invention between multiple quantum well layer and P-type layer by setting one AlN layers, on the one hand, AlN layers can A higher potential barrier energy level is formed, stops the migration of electronics;On the other hand, AlN layers of thickness is 1~30nm, due to AlN layers Thinner thickness, stress field caused by the adaptation stress between lattice is smaller, so as to improve being efficiently injected into for hole.Low temperature P-type layer is AlInGaN layer, AlInGaN layer and GaN Lattice Matchings, it is possible to reduce due to the stress field of lattice mismatch generation, simultaneously Compared with the low temperature P-type layer of the InGaN materials in existing LED, AlInGaN layers of energy level is higher, can further stop electricity The migration of son.It is engaged by AlN layers and AlInGaN layers, the effect of the electronic barrier layer of a part can be shared, so as to The thickness of electronic barrier layer is thinned so that the thickness of electronic barrier layer is in the range of 8~40nm, compared to the electronics in existing LED Barrier layer thickness substantially reduces, and the high Valence-band Offsets for avoiding the blocked up generation of electronic barrier layer hinder hole to be moved to multiple quantum well layer It moves, and then improves electronics and the recombination probability in hole, improve the luminous efficiency of LED.
Optionally, the overall thickness of insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature P-type layer 9 and p-type contact layer 10 For 40~150nm.Since the thickness of electronic barrier layer is thinned, then the thickness of entire P-type layer is thinned, and can improve light emitting diode Positive light extraction.
For the Light-Emitting Diode of positive assembling structure, when insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature p-type When the overall thickness of layer 9 and p-type contact layer 10 is 90nm, the light-out effect of light emitting diode is best.
For the light emitting diode of inverted structure, when insert layer 6, low temperature P-type layer 7, electronic barrier layer 8, high temperature p-type When the overall thickness of layer 9 and p-type contact layer 10 is 70nm, the light-out effect of light emitting diode is best.
Optionally, electronic barrier layer 8 is AlGaN layer or AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, AlGaN/ One kind in InAlN superlattice structures.
Preferably, electronic barrier layer 8 surpasses crystalline substance for AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, AlGaN/InAlN During lattice structure, limitation electronics overflow is more advantageous to.
In the present embodiment, substrate 1 can be Sapphire Substrate, and buffer layer 2 can be AlN layers, and N-type layer 4 can be GaN Layer.
Embodiment two
An embodiment of the present invention provides a kind of manufacturing methods of LED epitaxial slice, are provided suitable for embodiment one LED epitaxial slice, Fig. 2 are a kind of methods of the manufacturing method of LED epitaxial slice provided in an embodiment of the present invention Flow chart, as shown in Fig. 2, the manufacturing method includes:
Step 201 pre-processes substrate.
Optionally, substrate is sapphire, and thickness is 630~650um.
In the present embodiment, using Veeco K465i or C4 MOCVD (Metal Organic Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) equipment realize LED growing method.Using high-purity H2(hydrogen) Or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carrier gas, high-purity N H3As N sources, trimethyl gallium (TMGa) And triethyl-gallium (TEGa), as gallium source, trimethyl indium (TMIn) is used as indium source, silane (SiH4) is used as N type dopant, front three Base aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as P-type dopant.Chamber pressure is 100~600torr.
Specifically, which includes:
In a hydrogen atmosphere, 5~6min of high-temperature process substrate.Wherein, reaction chamber temperature is 1000~1100 DEG C, reative cell Pressure is controlled in 200~500torr.
Step 202, on substrate grown buffer layer.
Specifically, buffer growth is on sapphire face.
Specifically, Sapphire Substrate is sputtered in PVD (Physical Vapor Deposition, physical vapor deposition) The ALN buffer layers of one layer of 5~40nm thickness of sputtering in stove.
Step 203 grows GAN layers on the buffer layer.
After buffer growth, the substrate that sputtering there are ALN buffer layers is put into MOCVD device, room temperature will be reacted Degree is increased to 1040 °, and growth thickness is the GaN layer that 1 μm of high temperature undopes.
Step 204 grows N-type layer on GAN layers.
In the present embodiment, N-type layer is to mix the GaN layer of Si, thickness 2um.When growing N-type layer, reaction chamber temperature is 1000~1100 DEG C, chamber pressure is controlled in 200~300torr.
Step 205 grows multiple quantum well layer in N-type layer.
It in the present embodiment, can first growth stress releasing layer before growing multiple quantum well layer.
Specifically, stress release layer includes the InGaN well layer and GaN barrier layer of 3 cycle alternating growths, wherein InGaN traps The thickness of layer is 2nm, and growth temperature is 850~900 DEG C, growth pressure 250torr.The thickness of GaN barrier layer is 30~50nm, Growth temperature is 850~900 DEG C, growth pressure 250torr.
Stress release layer further includes the InGaN well layer of 6 cycle alternating growths and the thickness of GaN barrier layer, wherein InGaN well layer It spends for 2nm, growth temperature is 800~850 DEG C, growth pressure 250torr.The thickness of GaN barrier layer is 10~20nm, and growth is warm It spends for 800~850 DEG C, growth pressure 250torr.
Specifically, multiple quantum well layer is grown after stress release layer has been grown, multiple quantum well layer includes 8~10 cycles The InGaN quantum well layers of alternating growth and GaN quantum barrier layers, the wherein thickness of InGaN quantum well layers be 2.5nm, growth temperature For 780~820 DEG C, growth pressure 250torr.The thickness of GaN quantum barrier layers is 12nm, and growth temperature is 780~820 DEG C, Growth pressure is 250torr.
Since multiple quantum well layer includes InGaN quantum well layers and GaN quantum barrier layers, high component is grown in GaN material InGaN quantum well layers, higher lattice mismatch can be faced, so as to influence the crystal quality of multiple quantum well layer, by growing Growth stress releasing layer before multiple quantum well layer can make lattice relaxation to the relatively more suitable high component InGaN quantum well layers of growth State.
Step 206 grows insert layer on multiple quantum well layer.
In the present embodiment, insert layer is AlN layers, and AlN layers of thickness is 2nm.Growth temperature is 800~900 DEG C, growth Pressure is 150~250torr.
Step 207, the growing low temperature P-type layer in insert layer.
Optionally, low temperature P-type layer 71 is AlInGaN layers, thickness 30nm.Growth temperature is 700~800 DEG C, growth pressure Power is 150~250torr.
Wherein, doped with Mg in AlInGaN layers, the doping concentration of Mg is 3*1020/cm3
Step 208 grows electronic barrier layer in low temperature P-type layer.
In the present embodiment, electronic barrier layer is AlGaN layer, thickness 25nm.Growth temperature is 900~1000 DEG C, raw Long pressure is 100~600torr
Step 209 grows high temperature P-type layer on electronic barrier layer.
In the present embodiment, electronic barrier layer is AlGaN layer, thickness 20nm.Growth temperature is 980 DEG C, growth pressure For 100~600torr
Step 210, the growing P-type contact layer in high temperature P-type layer.
In the present embodiment, p-type contact layer be heavy doping Mg GaN layer, thickness 1.5nm.Growth temperature for 700~ 800 DEG C, growth pressure is 300~600torr.
It should be noted that p-type contact layer is mainly the Mg for activating and being adulterated in P-type layer, Mg is made to be generated after activating more Hole avoids due to not activating Ohmic contact difference being caused to cause chip brightness low and the high situation of voltage.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention Within, any modifications, equivalent replacements and improvements are made should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate and is sequentially laminated on the lining Buffer layer, GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and P on bottom Type contact layer, which is characterized in that
The insert layer is AlN layers, and thickness AlN layers described is 1~30nm, and the low temperature P-type layer is AlInGaN layers, described The thickness of electronic barrier layer is 8~40nm.
2. LED epitaxial slice according to claim 1, which is characterized in that the insert layer, low temperature P-type layer, electricity The overall thickness on sub- barrier layer, high temperature P-type layer and p-type contact layer is 40~150nm.
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that the electronic barrier layer is AlGaN One kind in layer or AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, AlGaN/InAlN superlattice structure.
4. LED epitaxial slice according to claim 1 or 2, which is characterized in that thickness AlN layers described is 2nm, The thickness of the electronic barrier layer is 25nm.
5. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes:
One substrate is provided;
Grown buffer layer, GaN layer, N-type layer, multiple quantum well layer, insert layer, low temperature P-type layer, electronics resistance successively over the substrate Barrier, high temperature P-type layer and p-type contact layer, the insert layer be AlN layer, thickness AlN layers described be 1~30nm, the low temperature P-type layer is AlInGaN layers, and the thickness of the electronic barrier layer is 8~40nm.
6. manufacturing method according to claim 5, which is characterized in that growth temperature AlN layers described is 800~900 DEG C.
7. manufacturing method according to claim 5, which is characterized in that growth pressure AlN layers described for 150torr~ 250torr。
8. according to claim 5~7 any one of them manufacturing method, which is characterized in that the insert layer, low temperature P-type layer, electricity The overall thickness on sub- barrier layer, high temperature P-type layer and p-type contact layer is 40~150nm.
9. according to claim 5~7 any one of them manufacturing method, which is characterized in that the electronic barrier layer is AlGaN layer Or one kind in AlGaN/GaN, AlGaN/InGaN, AlInGaN/GaN, AlGaN/InAlN superlattice structure.
10. according to claim 5~7 any one of them manufacturing method, which is characterized in that thickness AlN layers described is 2nm, The thickness of the electronic barrier layer is 25nm.
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CN109216510A (en) * 2017-06-29 2019-01-15 苏州新纳晶光电有限公司 A kind of epitaxial wafer growth method delaying LED stress
CN109301041A (en) * 2018-09-19 2019-02-01 华灿光电(苏州)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109360876A (en) * 2018-08-31 2019-02-19 华灿光电(浙江)有限公司 A kind of epitaxial wafer of light emitting diode and preparation method thereof
CN109860351A (en) * 2018-11-14 2019-06-07 华灿光电(浙江)有限公司 A kind of GaN base light emitting epitaxial wafer and preparation method thereof
CN110707188A (en) * 2019-11-15 2020-01-17 芜湖德豪润达光电科技有限公司 Light emitting diode and light emitting diode manufacturing method
CN112670378A (en) * 2020-12-31 2021-04-16 深圳第三代半导体研究院 Light emitting diode and manufacturing method thereof
CN114335270A (en) * 2021-12-27 2022-04-12 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, manufacturing method thereof and light emitting diode
CN115036402A (en) * 2022-08-12 2022-09-09 江苏第三代半导体研究院有限公司 Induced enhanced Micro-LED homoepitaxy structure and preparation method thereof
CN115084325A (en) * 2022-03-24 2022-09-20 淮安澳洋顺昌光电技术有限公司 GaN-based LED epitaxial structure capable of improving antistatic capacity
CN116154059A (en) * 2023-04-04 2023-05-23 江西兆驰半导体有限公司 Gallium nitride light-emitting diode epitaxial structure, LED and preparation method thereof
CN116230824A (en) * 2023-05-08 2023-06-06 江西兆驰半导体有限公司 High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED chip

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Publication number Priority date Publication date Assignee Title
CN109216510A (en) * 2017-06-29 2019-01-15 苏州新纳晶光电有限公司 A kind of epitaxial wafer growth method delaying LED stress
CN109360876A (en) * 2018-08-31 2019-02-19 华灿光电(浙江)有限公司 A kind of epitaxial wafer of light emitting diode and preparation method thereof
CN109301041A (en) * 2018-09-19 2019-02-01 华灿光电(苏州)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109860351A (en) * 2018-11-14 2019-06-07 华灿光电(浙江)有限公司 A kind of GaN base light emitting epitaxial wafer and preparation method thereof
CN110707188A (en) * 2019-11-15 2020-01-17 芜湖德豪润达光电科技有限公司 Light emitting diode and light emitting diode manufacturing method
CN112670378A (en) * 2020-12-31 2021-04-16 深圳第三代半导体研究院 Light emitting diode and manufacturing method thereof
CN114335270A (en) * 2021-12-27 2022-04-12 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, manufacturing method thereof and light emitting diode
CN115084325A (en) * 2022-03-24 2022-09-20 淮安澳洋顺昌光电技术有限公司 GaN-based LED epitaxial structure capable of improving antistatic capacity
CN115036402A (en) * 2022-08-12 2022-09-09 江苏第三代半导体研究院有限公司 Induced enhanced Micro-LED homoepitaxy structure and preparation method thereof
CN116154059A (en) * 2023-04-04 2023-05-23 江西兆驰半导体有限公司 Gallium nitride light-emitting diode epitaxial structure, LED and preparation method thereof
CN116230824A (en) * 2023-05-08 2023-06-06 江西兆驰半导体有限公司 High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED chip
CN116230824B (en) * 2023-05-08 2023-07-18 江西兆驰半导体有限公司 High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED chip

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