CN109545926A - A kind of LED epitaxial slice and its manufacturing method - Google Patents

A kind of LED epitaxial slice and its manufacturing method Download PDF

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Publication number
CN109545926A
CN109545926A CN201811451253.5A CN201811451253A CN109545926A CN 109545926 A CN109545926 A CN 109545926A CN 201811451253 A CN201811451253 A CN 201811451253A CN 109545926 A CN109545926 A CN 109545926A
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layer
insert
type
gan
led epitaxial
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洪威威
王倩
董彬忠
周飚
胡加辉
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Abstract

The invention discloses a kind of LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.LED epitaxial slice includes substrate and stacks gradually buffer layer on substrate, 3D nucleating layer, buffering retrieving layer, N-type layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type contact layer；LED epitaxial slice further includes the insert layer being arranged between buffering retrieving layer and N-type layer, and insert layer is AlN layers.On the one hand, one layer AlN layers are inserted into after GaN buffers retrieving layer, the compression accumulated in GaN buffering retrieving layer can be discharged, improve the crystal quality of GaN epitaxial layer.On the other hand, dislocation can be made to occur to merge, turn to or terminate dislocation for AlN layers, stops bottom defect to extend back, the crystal quality of multiple quantum well layer is promoted, to promote the interior quantum luminous efficiency of LED.

Description

A kind of LED epitaxial slice and its manufacturing method
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its manufacturing method.
Background technique
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.As A kind of efficient, environmentally friendly, green New Solid lighting source, is widely applied rapidly, such as traffic lights, automobile Inside and outside lamp, landscape light in city, cell phone back light source etc..
Epitaxial wafer is the main composition part in LED, and existing GaN base LED epitaxial wafer includes substrate and is sequentially laminated on Buffer layer, 3D nucleating layer, buffering retrieving layer, N-type layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature on substrate P-type layer and p-type contact layer.Wherein, 3D nucleating layer is usually grown at low ambient temperatures, to realize its three dimensional growth.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Since GaN base LED epitaxial wafer mostly uses Sapphire Substrate, there are larger between Sapphire Substrate and GaN epitaxial layer Lattice adaptation and thermal mismatching so that generating compression between Sapphire Substrate and GaN epitaxial layer, and with GaN epitaxial layer Thickness increases, which also will continue to accumulate, and causes the crystal quality of the GaN epitaxial layer grown poor.3D nucleating layer simultaneously Growth temperature it is lower, therefore 3D nucleation layer surface can generate a large amount of line defect and screw dislocation, cause buffering restore There are a large amount of defects in layer, assemble electricity to fault location, influence the luminous efficiency of LED.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slice and its manufacturing methods, can reduce GaN epitaxial layer In compression, stop bottom defect upwardly extend, improve the luminous efficiency of LED.The technical solution is as follows:
On the one hand, a kind of LED epitaxial slice is provided, the LED epitaxial slice includes substrate, Yi Jiyi The secondary buffer layer being layered on the substrate, 3D nucleating layer, buffering retrieving layer, N-type layer, multiple quantum well layer, low temperature P-type layer, electricity Sub- barrier layer, high temperature P-type layer and p-type contact layer,
The LED epitaxial slice further includes insert layer, and insert layer setting is in the buffering retrieving layer and described Between N-type layer, the insert layer is AlN layers, and the buffering retrieving layer is GaN layer.
Further, the insert layer with a thickness of 10~30nm.
Further, the insert layer with a thickness of 20nm.
On the other hand, the present invention provides a kind of manufacturing method of LED epitaxial slice, the manufacturing method includes:
One substrate is provided；
Over the substrate successively grown buffer layer, 3D nucleating layer, buffering retrieving layer；
Insert layer is grown in the buffering retrieving layer, the insert layer is AlN layers；
N-type layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer are successively grown in the insert layer With p-type contact layer.
Further, the insert layer with a thickness of 10~30nm.
Further, the insert layer with a thickness of 20nm.
Further, the growth temperature of the insert layer is 1000~1100 DEG C.
Further, the growth temperature of the insert layer is 1080 DEG C.
Further, the growth pressure of the insert layer is 50~200torr.
Further, the growth pressure of the insert layer is 100torr.
Technical solution provided in an embodiment of the present invention has the benefit that
By being inserted into one layer AlN layers after buffering retrieving layer, on the one hand, since the lattice constant of AlN is less than GaN material, Therefore, one layer AlN layers are inserted into after GaN buffers retrieving layer, the compression accumulated in GaN buffering retrieving layer can be discharged, improved The crystal quality of GaN epitaxial layer.On the other hand, dislocation can be made to occur to merge, turn to or terminate dislocation for AlN layers, stopped Bottom defect extends back, so as to promote the crystal quality of multiple quantum well layer.The crystal quality of multiple quantum well layer is more preferable, then Be conducive to the formation of the richness In centre of luminescence in multiple quantum well layer, more electronics are captured in multiple quantum well layer and hole radiative Recombination luminescence improves the interior quantum luminous efficiency of LED.And AlN insert layer can also stop electronics to 3D nucleating layer and buffering Retrieving layer diffusion, reduces electronics overflow, further improves the luminous efficiency of LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of manufacturing method flow chart of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention, as shown in Figure 1, should LED epitaxial slice includes substrate 1 and the buffer layer being sequentially laminated on substrate 12,3D nucleating layer 3, buffering retrieving layer 4, N-type layer 6, multiple quantum well layer 7, low temperature P-type layer 8, electronic barrier layer 9, high temperature P-type layer 10 and p-type contact layer 11.
LED epitaxial slice further includes insert layer 5, and the setting of insert layer 5 is inserted between buffering retrieving layer 4 and N-type layer 6 Entering layer 5 is AlN layers, and buffering retrieving layer 4 is GaN layer.
The embodiment of the present invention after buffering retrieving layer by being inserted into one layer AlN layers, on the one hand, due to the lattice constant of AlN Less than GaN material, therefore, one layer AlN layers are inserted into after GaN buffers retrieving layer, accumulation in GaN buffering retrieving layer can be discharged Compression improves the crystal quality of GaN epitaxial layer.On the other hand, dislocation can be made to occur to merge, turn to or make position for AlN layers Mistake terminates, and stops bottom defect to extend back, so as to promote the crystal quality of multiple quantum well layer.The crystal of multiple quantum well layer Better quality, then be conducive to the formation of the richness In centre of luminescence in multiple quantum well layer, and more electronics are captured on multiple quantum well layer In with hole radiative recombination luminescence, improve the interior quantum luminous efficiency of LED.And AlN insert layer can also stop electronics to 3D Nucleating layer and buffering retrieving layer diffusion, reduce electronics overflow, further improve the luminous efficiency of LED.
Further, insert layer 5 with a thickness of 10~30nm.If the thickness of insert layer 5 is less than 10nm, raising is not had The effect of the luminous efficiency of LED.If the thickness of insert layer 5 is greater than 30nm, it will cause the wastes of material.
Preferably, insert layer 5 with a thickness of 20nm.It can play the role of improving the luminous efficiency of LED at this time, and will not Cause the waste of material.
Optionally, substrate 1 can be Sapphire Substrate.
Optionally, buffer layer 2 can be AlN buffer layer, with a thickness of 15~50nm.
Optionally, 3D nucleating layer 3 with a thickness of 0.5~2um.
Optionally, buffer retrieving layer 4 with a thickness of 0.5~1um.
Optionally, N-type layer 6 can be to mix the GaN layer of Si, with a thickness of 1~5um.
Optionally, multiple quantum well layer 7 is the superlattice structure in n period, and each superlattice structure includes InGaN quantum Well layer and the GaN quantum barrier layer being grown on InGaN quantum well layer, 5≤n≤11.Wherein, the thickness of InGaN quantum well layer can Think that 2~3nm, the thickness of GaN quantum barrier layer can be 10~20nm.
Optionally, low temperature P-type layer 8 is the GaN layer of heavy doping Mg, and the doping concentration of Mg is greater than or equal to 1 × 1020cm-3。
Optionally, electronic barrier layer 9 can mix the AlGaN layer of Mg, and the doping concentration of Mg is less than
1×1018cm-3, with a thickness of 20~30nm.
Optionally, high temperature P-type layer 10 can be the GaN layer of doping Mg, the doping concentration 1 × 10 of Mg17~1 × 1018cm-3, With a thickness of 10~30nm.
Optionally, p-type contact layer 11 can be the GaN layer of heavily doped Mg, with a thickness of 20~30nm.
Fig. 2 is a kind of manufacturing method flow chart of LED epitaxial slice provided in an embodiment of the present invention, such as Fig. 2 institute Show, which includes:
Step 201 provides a substrate.
In the present embodiment, substrate can use the Al of (0001) crystal orientation2O3Sapphire Substrate.
Step 202, on substrate grown buffer layer.
In the present embodiment, buffer layer is AlN buffer layer.
It specifically, can be using PVD (Physical Vapor Deposition, physical vapor deposition) equipment in substrate The AlN buffer layer that upper deposition thickness is about 15~50nm.Controlling the pressure in PVD equipment reaction chamber is 1~10mtorr, temperature It is 400~700 DEG C, sputtering power is 3000~5000W.
Further, step 202 can also include:
The substrate for being deposited with AlN buffer layer is made annealing treatment, annealing temperature is 1000~1200 DEG C, pressure 200 ~500torr, annealing time are 5~10min.
It specifically, can be in MOCVD (Metal-organicChemicalVaporDeposition, Organometallic conjunction Object chemical gaseous phase deposition) it is made annealing treatment in equipment.The present invention uses high-purity H2Or high-purity N2Or high-purity H2And high-purity N2It is mixed Gas is closed as carrier gas, high-purity N H3As the source N, trimethyl gallium (TMGa) and triethyl-gallium (TEGa) are used as gallium source, trimethyl indium (TMIn) it is used as indium source, silane (SiH4) is used as N type dopant, and trimethyl aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) make For P-type dopant.
Step 203 grows 3D nucleating layer on the buffer layer.
In the present embodiment, 3D nucleating layer is GaN layer.
Specifically, reaction chamber temperature is controlled at 1010~1060 DEG C, pressure is controlled in 300~500torr, growth thickness For the 3D nucleating layer of 0.5~2um.
Step 204, the growth buffering retrieving layer on 3D nucleating layer.
In the present embodiment, buffering retrieving layer is GaN layer.
Specifically, control reaction chamber temperature is 1000~1100 DEG C, and pressure is 100~300torr, growth thickness 0.5 The buffering retrieving layer of~1um.
Step 205 grows insert layer in buffering retrieving layer.
In the present embodiment, insert layer is AlN layers.
Further, insert layer with a thickness of 10~30nm.If the thickness of insert layer is less than 10nm, raising is not had The effect of the luminous efficiency of LED.If the thickness of insert layer is greater than 30nm, it will cause the wastes of material.
Preferably, insert layer with a thickness of 20nm.It can play the role of improving the luminous efficiency of LED at this time, and will not Cause the waste of material.
Further, the growth temperature of insert layer is 1000~1100 DEG C.It is extensive with buffering by the temperature setting of insert layer Cladding temperature is identical, then without adjusting reaction chamber temperature after having grown buffering retrieving layer, can continued growth insert layer temperature, Improve the speed of growth.
Preferably, the growth temperature of insert layer is 1080 DEG C.At this point, the crystal quality of the insert layer grown is best, it can Effectively to stop bottom defect to upwardly extend.
Further, the growth pressure of insert layer is 50~200torr.If the growth pressure of insert layer is less than 50torr, Pressure then in MOCVD system is more difficult to control.If the growth pressure of insert layer is greater than 200torr, AlN layers in MOCVD system When middle growth, Al atom and N atom pre-reaction are strong, and AlN layers are difficult to deposit on epitaxial wafer, so that the AlN layers of shape with impurity Formula exists, to seriously affect the epitaxial layer crystal quality being grown on AlN layer.
Preferably, the growth pressure of insert layer is 100torr.It can guarantee the pressure controlling party in MOCVD system at this time Just, and it will not influence the epitaxial layer crystal quality being grown on AlN layer.
Step 206 grows N-type layer in insert layer.
In the present embodiment, N-type layer is to mix the GaN layer of Si, and the concentration that Si is adulterated in N-type layer is 1 × 1018~1 × 1019cm-3。
Specifically, reaction chamber temperature is controlled at 1000~1200 DEG C, pressure is controlled in 100~500torr, growth thickness For the N-type layer of 1~5um.
Step 207 grows multiple quantum well layer in N-type layer.
In the present embodiment, multiple quantum well layer is the superlattice structure in n period, and each superlattice structure includes InGaN quantum well layer and the GaN quantum barrier layer being grown on InGaN quantum well layer, 5≤n≤11.
Specifically, step 207 may include:
By reaction chamber temperature control at 720~820 DEG C, in 100~300torr, growth thickness is 2~3nm for pressure control InGaN quantum well layer.
By reaction chamber temperature control at 850~950 DEG C, pressure control in 100~300torr, growth thickness is 10~ The GaN quantum barrier layer of 20nm.
Step 208, the growing low temperature P-type layer on multiple quantum well layer.
In the present embodiment, low temperature P-type layer is the GaN layer of heavy doping Mg, the doping concentration of Mg is greater than or equal to 1 × 1020cm-3。
Specifically, reaction chamber temperature is controlled at 700~800 DEG C, pressure is controlled in 100~600torr, and growth thickness is The low temperature P-type layer of 10~30nm.
Step 209 grows electronic barrier layer in low temperature P-type layer.
In the present embodiment, electronic barrier layer is the AlGaN layer for mixing Mg, and the doping concentration of Mg is less than 1 × 1018cm-3。
Specifically, reaction chamber temperature is controlled at 900~1000 DEG C, pressure is controlled in 100~300torr, growth thickness For the electronic barrier layer of 20~30nm.
Step 210 grows high temperature P-type layer on electronic barrier layer.
In the present embodiment, high temperature P-type layer is to adulterate the GaN layer of Mg, the doping concentration 1 × 10 of Mg17~1 × 1018cm-3。
Specifically, reaction chamber temperature is controlled at 900~980 DEG C, pressure is controlled in 300~600torr, and growth thickness is The high temperature P-type layer of 10~30nm.
Step 211, the growing P-type contact layer in high temperature P-type layer.
In the present embodiment, p-type contact layer can be the GaN layer of heavily doped Mg.
Specifically, reaction chamber temperature is controlled at 850~950 DEG C, pressure is controlled in 100~600torr, and growth thickness is The p-type contact layer of 20~30nm.
After above-mentioned steps completion, the temperature of reaction chamber is down to 650~850 DEG C, is carried out at annealing in nitrogen atmosphere 5~15min is managed, room temperature is then gradually decreased to, terminates the epitaxial growth of light emitting diode.
The embodiment of the present invention after buffering retrieving layer by being inserted into one layer AlN layers, on the one hand, due to the lattice constant of AlN Less than GaN material, therefore, one layer AlN layers are inserted into after GaN buffers retrieving layer, accumulation in GaN buffering retrieving layer can be discharged Compression improves the crystal quality of GaN epitaxial layer.On the other hand, dislocation can be made to occur to merge, turn to or make position for AlN layers Mistake terminates, and stops bottom defect to extend back, so as to promote the crystal quality of multiple quantum well layer.The crystal of multiple quantum well layer Better quality, then be conducive to the formation of the richness In centre of luminescence in multiple quantum well layer, and more electronics are captured on multiple quantum well layer In with hole radiative recombination luminescence, improve the interior quantum luminous efficiency of LED.And AlN insert layer can also stop electronics to 3D Nucleating layer and buffering retrieving layer diffusion, reduce electronics overflow, further improve the luminous efficiency of LED.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate and is sequentially laminated on the lining Buffer layer, 3D nucleating layer, buffering retrieving layer, N-type layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P on bottom Type layer and p-type contact layer, which is characterized in that
The LED epitaxial slice further includes insert layer, and the insert layer is arranged in the buffering retrieving layer and the N-type Between layer, the insert layer is AlN layers, and the buffering retrieving layer is GaN layer.
2. LED epitaxial slice according to claim 1, which is characterized in that the insert layer with a thickness of 10~ 30nm。
3. LED epitaxial slice according to claim 1, which is characterized in that the insert layer with a thickness of 20nm.
4. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes:
One substrate is provided；
Over the substrate successively grown buffer layer, 3D nucleating layer, buffering retrieving layer；
Insert layer is grown in the buffering retrieving layer, the insert layer is AlN layers；
N-type layer, multiple quantum well layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and P are successively grown in the insert layer Type contact layer.
5. manufacturing method according to claim 4, which is characterized in that the insert layer with a thickness of 10~30nm.
6. manufacturing method according to claim 4, which is characterized in that the insert layer with a thickness of 20nm.
7. manufacturing method according to claim 4, which is characterized in that the growth temperature of the insert layer is 1000~1100 ℃。
8. manufacturing method according to claim 4, which is characterized in that the growth temperature of the insert layer is 1080 DEG C.
9. manufacturing method according to claim 4, which is characterized in that the growth pressure of the insert layer be 50~ 200torr。
10. manufacturing method according to claim 4, which is characterized in that the growth pressure of the insert layer is 100torr.
CN201811451253.5A 2018-11-30 2018-11-30 A kind of LED epitaxial slice and its manufacturing method Pending CN109545926A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112736171A (en) * 2020-12-31 2021-04-30 晶能光电（江西）有限公司 Silicon substrate GaN-based LED and preparation method thereof
CN113707776A (en) * 2021-08-31 2021-11-26 材料科学姑苏实验室 Epitaxial wafer of AlN-based ultraviolet light-emitting diode and manufacturing method thereof
CN114300592A (en) * 2021-12-28 2022-04-08 福建兆元光电有限公司 Mini LED epitaxial structure and manufacturing method thereof
CN115832135A (en) * 2023-02-14 2023-03-21 江西兆驰半导体有限公司 Silicon-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101060076A (en) * 2007-05-14 2007-10-24 武汉大学 A manufacture method for GaN insulation or semi-insulation epitaxy layer
CN103296151A (en) * 2012-03-01 2013-09-11 上海蓝光科技有限公司 Method for reducing warping stress of LED epitaxy
CN104091868A (en) * 2014-06-12 2014-10-08 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and manufacture method thereof
CN104465918A (en) * 2014-10-31 2015-03-25 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN105161578A (en) * 2015-08-17 2015-12-16 中国科学院半导体研究所 Growth method of GaN thin film on Si substrate and composite GaN thin film
CN106098871A (en) * 2016-07-25 2016-11-09 华灿光电（浙江）有限公司 A kind of preparation method of LED epitaxial slice
CN106601882A (en) * 2016-11-21 2017-04-26 华灿光电（浙江）有限公司 Light-emitting diode epitaxial wafer and manufacturing method thereof
CN107170860A (en) * 2017-05-27 2017-09-15 华灿光电（浙江）有限公司 A kind of epitaxial wafer of light emitting diode and preparation method thereof
CN107248543A (en) * 2017-05-24 2017-10-13 太原理工大学 A kind of LED epitaxial structure and preparation method thereof
CN108258094A (en) * 2018-01-06 2018-07-06 李丹丹 Light emitting semiconductor device and preparation method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101060076A (en) * 2007-05-14 2007-10-24 武汉大学 A manufacture method for GaN insulation or semi-insulation epitaxy layer
CN103296151A (en) * 2012-03-01 2013-09-11 上海蓝光科技有限公司 Method for reducing warping stress of LED epitaxy
CN104091868A (en) * 2014-06-12 2014-10-08 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and manufacture method thereof
CN104465918A (en) * 2014-10-31 2015-03-25 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and preparation method thereof
CN105161578A (en) * 2015-08-17 2015-12-16 中国科学院半导体研究所 Growth method of GaN thin film on Si substrate and composite GaN thin film
CN106098871A (en) * 2016-07-25 2016-11-09 华灿光电（浙江）有限公司 A kind of preparation method of LED epitaxial slice
CN106601882A (en) * 2016-11-21 2017-04-26 华灿光电（浙江）有限公司 Light-emitting diode epitaxial wafer and manufacturing method thereof
CN107248543A (en) * 2017-05-24 2017-10-13 太原理工大学 A kind of LED epitaxial structure and preparation method thereof
CN107170860A (en) * 2017-05-27 2017-09-15 华灿光电（浙江）有限公司 A kind of epitaxial wafer of light emitting diode and preparation method thereof
CN108258094A (en) * 2018-01-06 2018-07-06 李丹丹 Light emitting semiconductor device and preparation method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112736171A (en) * 2020-12-31 2021-04-30 晶能光电（江西）有限公司 Silicon substrate GaN-based LED and preparation method thereof
CN113707776A (en) * 2021-08-31 2021-11-26 材料科学姑苏实验室 Epitaxial wafer of AlN-based ultraviolet light-emitting diode and manufacturing method thereof
CN113707776B (en) * 2021-08-31 2024-04-19 材料科学姑苏实验室 Epitaxial wafer of AlN-based ultraviolet light-emitting diode and manufacturing method thereof
CN114300592A (en) * 2021-12-28 2022-04-08 福建兆元光电有限公司 Mini LED epitaxial structure and manufacturing method thereof
CN114300592B (en) * 2021-12-28 2024-01-09 福建兆元光电有限公司 Mini LED epitaxial structure and manufacturing method thereof
CN115832135A (en) * 2023-02-14 2023-03-21 江西兆驰半导体有限公司 Silicon-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN115832135B (en) * 2023-02-14 2023-05-02 江西兆驰半导体有限公司 Silicon-based light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

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