CN109980056A - Gallium nitride based LED epitaxial slice and its manufacturing method - Google Patents

Gallium nitride based LED epitaxial slice and its manufacturing method Download PDF

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CN109980056A
CN109980056A CN201910152555.0A CN201910152555A CN109980056A CN 109980056 A CN109980056 A CN 109980056A CN 201910152555 A CN201910152555 A CN 201910152555A CN 109980056 A CN109980056 A CN 109980056A
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quantum well
well layer
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superlattice structure
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CN109980056B (en
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刘旺平
乔楠
吕蒙普
胡加辉
李鹏
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

The invention discloses a kind of gallium nitride based LED epitaxial slice and its manufacturing methods, belong to technical field of semiconductors.Gallium nitride based LED epitaxial slice includes substrate and successively grows low temperature buffer layer, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer, stress release layer, multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer on substrate, stress release layer includes the first superlattice structure and the second superlattice structure of multiple alternating growths, first superlattice structure is low temperature InGaN/GaN superlattice structure, and the second superlattice structure is high temperature InGaN/GaN superlattice structure.LED epitaxial slice provided by the invention can optimize the openings of sizes in V-type hole, improve the interior quantum luminous efficiency of LED, while improving the crystal quality of epitaxial layer.

Description

Gallium nitride based LED epitaxial slice and its manufacturing method
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of gallium nitride based LED epitaxial slice and its manufacture Method.
Background technique
LED (Light Emitting Diode, light emitting diode) is a kind of semiconductor electronic component that can be luminous.LED As a kind of efficient, environmental protection, green New Solid lighting source, it is widely applied to such as traffic lights, vapour rapidly In the fields such as interior outer lamp, landscape light in city, cell phone back light source.
Epitaxial wafer is the main composition part in LED, and existing GaN base LED epitaxial wafer includes Sapphire Substrate, Yi Jiyi It is the secondary low temperature buffer layer being layered in Sapphire Substrate, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer, more Quantum well layer, electronic barrier layer, P-type layer and p-type contact layer.Since there are biggish between Sapphire Substrate and GaN epitaxial layer Lattice mismatch so that can generate stress in epitaxial layer, and then generates a large amount of threading dislocation, and stress and threading dislocation are along epitaxial wafer Stacking direction extend in multiple quantum well layer can seriously affect LED shine.In order to improve the luminous efficiency of LED, it will usually One ply stress releasing layer is set between N-type layer and multiple quantum well layer, to discharge bottom stress, reduces dislocation and generates.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Since stress release layer in the prior art is usually in cryogenic thermostat conditioned growth, to guarantee the effect of its stress release Fruit.And threading dislocation can cause the formation in V-type hole under cryogenic, and under cryogenic, the horizontal extension ability of GaN becomes The opening of difference, V-type hole can be gradually increased.When V-type hole opening is excessive, the barrier height that V-type cheats inclined surface is reduced, to carrier Limitation capability weakens, and will lead to and carries out non-radiative recombination between electrons and holes, so that the interior quantum luminous efficiency of LED reduces. Simultaneously under cryogenic, the density in the V-type hole of formation can gradually increase, and decline so as to cause the crystal quality of epitaxial layer.
Summary of the invention
The embodiment of the invention provides a kind of gallium nitride based LED epitaxial slice and its manufacturing methods, can optimize V The openings of sizes in type hole, improves the interior quantum luminous efficiency of LED, while improving the crystal quality of epitaxial layer.The technical solution It is as follows:
On the one hand, the present invention provides a kind of gallium nitride based LED epitaxial slice, two poles of gallium nitride base light emitting Pipe epitaxial wafer include substrate and successively grow low temperature buffer layer over the substrate, three-dimensional nucleating layer, two-dimentional retrieving layer, Undoped GaN layer, N-type layer, stress release layer, multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer,
The stress release layer includes the first superlattice structure and the second superlattice structure of multiple alternating growths, and described One superlattice structure is low temperature InGaN/GaN superlattice structure, and second superlattice structure is high temperature InGaN/GaN superlattices Structure.
Further, the stress release layer with a thickness of 100~150nm.
Further, the multiple quantum well layer includes close to the first kind multiple quantum well layer of the N-type layer, close to the P The third class multiple quantum well layer of type layer and between the first kind multiple quantum well layer and the third class multiple quantum well layer The second class multiple quantum well layer；
The first kind multiple quantum well layer by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, second class Multiple quantum well layer by multiple periods InaGa1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods InaGa1-aN/InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
Further, in the first kind quantum well layer, the second class quantum well layer and the third class quantum well layer InaGa1-aN layers of thickness is equal.
Further, the Al in the first kind quantum well layercGa1-cN layers, the GaN layer in the second class quantum well layer With the In in the third class quantum well layerbGa1-bN layers of thickness is equal.
On the other hand, the present invention provides a kind of manufacturing method of gallium nitride based LED epitaxial slice, the manufactures Method includes:
One substrate is provided；
Successively growing low temperature buffer layer, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N over the substrate Type layer；
The growth stress releasing layer in the N-type layer, the stress release layer include that multiple alternating growths the first surpass crystalline substance Lattice structure and the second superlattice structure, first superlattice structure is low temperature InGaN/GaN superlattice structure, described the second to surpass Lattice structure is high temperature InGaN/GaN superlattice structure；
Multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer are successively grown on the stress release layer.
Further, the growth stress releasing layer in the N-type layer, comprising:
780 DEG C~880 DEG C at a temperature of, grow first superlattice structure；
830 DEG C~930 DEG C at a temperature of, grow second superlattice structure.
Further, the multiple quantum well layer includes close to the first kind multiple quantum well layer of the N-type layer, close to the P The third class multiple quantum well layer of type layer and between the first kind multiple quantum well layer and the third class multiple quantum well layer The second class multiple quantum well layer；
The first kind multiple quantum well layer by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, second class Multiple quantum well layer by multiple periods InaGa1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods InaGa1-aN/InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
Further, in the first kind quantum well layer, the second class quantum well layer and the third class quantum well layer InaGa1-aN layers of thickness is equal.
Further, the Al in the first kind quantum well layercGa1-cN layers, the GaN layer in the second class quantum well layer With the In in the third class quantum well layerbGa1-bN layers of thickness is equal.
Technical solution provided in an embodiment of the present invention has the benefit that
By set stress release layer to include multiple alternating growths the first superlattice structure and the second superlattices knot Structure.Wherein, the first superlattice structure is low temperature InGaN/GaN superlattice structure, the first superlattice structure using low-temperature epitaxy and At, it is ensured that stress release layer has preferable stress release effect.But the first superlattice structure meeting in low-temperature epitaxy Cause the formation in V-type hole, therefore, the present invention the second is surpassed by two superlattice structure of growth regulation after the first superlattice structure Lattice structure is high temperature InGaN/GaN superlattice structure, and under the high temperature conditions, the horizontal extension ability of GaN enhances, and can be inhibited V-type hole opening continue to become larger, thus by V-type hole opening control in suitable range, avoid V-type hole be open it is excessive, The case where causing the interior quantum luminous efficiency reduction of LED appearance.Simultaneously under the high temperature conditions, the density in the V-type of formation hole can be by It is decrescence few, so as to improve the crystal quality of epitaxial layer.And the stress release layer in the present invention includes multiple alternating growths Low temperature InGaN/GaN superlattice structure and high temperature InGaN/GaN superlattice structure, (i.e. only with the stress release layer of single layer structure Including a low temperature InGaN/GaN superlattice structure and a high temperature InGaN/GaN superlattice structure) it compares, V-type hole is opened Mouth control effect is more preferable.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is that a kind of V-type provided in an embodiment of the present invention cheats the hatch frame schematic diagram in multiple quantum well layer；
Fig. 2 is a kind of structural schematic diagram of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of multiple quantum well layer provided in an embodiment of the present invention；
Fig. 4 is a kind of manufacturing method flow chart of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
Fig. 1 is that a kind of V-type provided in an embodiment of the present invention cheats the hatch frame schematic diagram in multiple quantum well layer, such as Fig. 1 Shown, the △ L in Fig. 1 is indicated on the inclined surface that the center of threading dislocation is cheated to the diffusion length of V-type pit edge, △ E expression V-type The barrier height of Quantum Well.It is a large amount of due to that, there are biggish lattice mismatch, can be generated between Sapphire Substrate and GaN epitaxial layer Threading dislocation, and threading dislocation can become the leakage channel of carrier, so capture least a portion of carrier formed it is non-radiative multiple Conjunction center causes the luminous efficiency of LED to decline.Threading dislocation can cause the formation in V-type hole under cryogenic.
When the too small openings in V-type hole, △ L is smaller, and the diffusion length of threading dislocation center to V-type pit edge can be relatively It is short, so that carrier, which is easier to be captured, enters threading dislocation center；△ E is larger, and the inclined surface in V-type hole has higher gesture It builds, it is stronger to carrier limitation capability, it can effectively be passivated the non-radiative center of threading dislocation.
When the opening in V-type hole is excessive, △ L is larger, and the diffusion length of threading dislocation center to V-type pit edge can be relatively It is long, carrier can be inhibited to enter non-radiative recombination center；△ E is smaller, and the barrier height of the inclined surface in V-type hole reduces, to load It flows sub- limitation capability to weaken, threading dislocation still can become the leakage channel of carrier, and then capture least a portion of carrier shape At non-radiative recombination center, the luminous efficiency of LED is caused to decline.
Therefore, the excessive or too small luminous efficiency that can all influence LED that is open in V-type hole.The embodiment of the invention provides one Kind gallium nitride based LED epitaxial slice and its manufacturing method can optimize the openings of sizes in V-type hole, improve the interior amount of LED Sub- luminous efficiency, while improving the crystal quality of epitaxial layer.
Fig. 2 is a kind of structural schematic diagram of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention, such as Fig. 2 Low temperature buffer layer 2, three shown, that gallium nitride based LED epitaxial slice includes substrate 1 and is successively grown on substrate 1 Tie up nucleating layer 3, two-dimentional retrieving layer 4, undoped GaN layer 5, N-type layer 6, stress release layer 7, multiple quantum well layer 8, electronic blocking Layer 9, P-type layer 10 and p-type contact layer 11.
First superlattice structure 71 and second superlattice structure 72 of the stress release layer 7 including multiple alternating growths, first Superlattice structure 71 is low temperature InGaN/GaN superlattice structure, and the second superlattice structure 72 is high temperature InGaN/GaN superlattices knot Structure.
The embodiment of the present invention by by stress release layer be set as include multiple alternating growths the first superlattice structure and Second superlattice structure.Wherein, the first superlattice structure is low temperature InGaN/GaN superlattice structure, and the first superlattice structure is adopted It is formed with low-temperature epitaxy, it is ensured that stress release layer has preferable stress release effect.But the first superlattice structure exists The formation in V-type hole can be caused when low-temperature epitaxy, therefore, the present invention passes through two superlattices of growth regulation after the first superlattice structure Structure, the second superlattice structure are high temperature InGaN/GaN superlattice structure, and under the high temperature conditions, the horizontal extension ability of GaN increases By force, the opening that V-type can be inhibited to cheat continues to become larger, to controlling the opening in V-type hole in suitable range, avoids V-type The case where hole opening is excessive, causes the interior quantum luminous efficiency reduction of LED appearance.Simultaneously under the high temperature conditions, the V-type of formation is cheated Density can gradually decrease, so as to improve the crystal quality of epitaxial layer.And the stress release layer in the present invention includes multiple The low temperature InGaN/GaN superlattice structure and high temperature InGaN/GaN superlattice structure of alternating growth, are released with the stress of single layer structure Layer (only including a low temperature InGaN/GaN superlattice structure and a high temperature InGaN/GaN superlattice structure) is put to compare, it is right The opening control effect in V-type hole is more preferable.
It should be noted that can be open in the present embodiment by the counter preferably V-type hole of releasing of height of luminous efficiency Size, wherein it is preferable to control the effect between 200~300nm for the opening diameter in V-type hole.
Optionally, stress release layer 7 includes the first superlattice structure 71 and the second superlattice structure of N number of alternating growth 72,2≤N≤12.If it is more that the number of N excessively will lead to low temperature, the conversion times of high temperature, if the number of N is very few, can not have The opening in effect control V-type hole.
Illustratively, N=8.The opening in V-type hole can be effectively controlled at this time, and the growth of stress release layer will not be made Journey is excessively complicated.
Further, the high temperature in the low temperature ingan layer 71a and the second superlattice structure 72 in the first superlattice structure 71 InGaN layer 72a is InxGa1-xN layers, 0.05 < x < 0.4.When the content of In is in the value range, stress release layer release is answered The effect of power is best.
Optionally, the thickness of the first superlattice structure 71 and the second superlattice structure 72 is equal, in order to periodically control The growth of stress release layer processed, so that the even density variation of the opening in V-type hole and V-type hole.
Illustratively, the high temperature in the low temperature ingan layer 71a and the second superlattice structure 72 in the first superlattice structure 71 The thickness of InGaN layer 72a is 1~2nm.In GaN layer 71b and the second superlattice structure 72 in first superlattice structure 71 The thickness of GaN layer 72b is 10~40nm.
In other implementations, the thickness of the first superlattice structure 71 and the second superlattice structure 72 can not also phase Deng.
Further, stress release layer 7 with a thickness of 100~150nm.If the thickness of stress release layer 7 is blocked up, can make The crystal quality of stress release layer 7 declines, if the thickness mistake of stress release layer 7, does not have the effect of release stress.By stress The thickness of releasing layer 7 is set as 100~150nm, can proof stress releasing layer 7 crystal quality simultaneously, it is preferable to discharge Bottom stress.
Fig. 3 is a kind of structural schematic diagram of multiple quantum well layer provided in an embodiment of the present invention, as shown in figure 3, multiple quantum wells Layer 8 includes the first kind multiple quantum well layer 81 close to N-type layer 6, third class multiple quantum well layer 83, the Yi Jiwei close to P-type layer 10 The second class multiple quantum well layer 82 between first kind multiple quantum well layer 81 and third class multiple quantum well layer 83.
First kind multiple quantum well layer 81 by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, the second class Multiple-quantum Well layer 82 by multiple periods InaGa1-aN/GaN superlattices composition, third class multiple quantum well layer 83 by multiple periods InaGa1- aN/InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
Due to AlGaN, GaN, InbGa1-bThe size relation of the forbidden bandwidth of these three materials of N are as follows: InGaN < GaN < AlGaN.Therefore, the growth rate in the V-type hole formed in stress release layer 7 is in these three materials of InGaN, GaN, AlGaN It is gradually reduced.Therefore, the growth cheated using AlGaN as barrier layer, V-type in the first kind multiple quantum well layer 81 close to N-type layer 6 Rate is slower, can inhibit V-type hole opening is too fast to become larger from the incipient stage, V-type hole is avoided to extend close to the volume of P-type layer 10 Opening becomes excessive when sub- well layer 8, then successively uses GaN in the second class multiple quantum well layer 82 and third class multiple quantum well layer 83 With InGaN as barrier layer, the too small openings that can prevent V-type from cheating.When the too small openings in V-type hole, threading dislocation to V-type cheats side The diffusion length of edge can be shorter, so that carrier, which is easier to be captured, enters threading dislocation center.
Further, in first kind quantum well layer 81, the second class quantum well layer 82 and third class quantum well layer 83 InaGa1-aN layers of thickness is equal, and thereby may be ensured that the consistency of emission wavelength.
Optionally, the In in first kind quantum well layer 81aGa1-aIn in N layers of 81a, the second class quantum well layer 82aGa1-aN In in layer 82a, third class quantum well layer 83aGa1-aN layers of thickness is 3~4nm.
Further, the Al in first kind quantum well layer 81cGa1-cGaN layer in N layers of 81b, the second class quantum well layer 82 In in 82b and third class quantum well layer 83bGa1-bThe thickness of N layers of 83b is equal, in order to grow the opening in control V-type hole Size.
Al in other implementations, in first kind quantum well layer 81cGa1-cIn N layers of 81b, the second class quantum well layer 82 GaN layer 82b and third class quantum well layer 83 in InbGa1-bThe thickness of N layers of 83b can also be unequal.
Optionally, the Al in first kind quantum well layer 81cGa1-cGaN layer 82b in N layers of 81b, the second class quantum well layer 82 With the In in third class quantum well layer 83bGa1-bThe thickness of N layers of 83b is 9~20nm.
Optionally, substrate 1 can be Sapphire Substrate.
Optionally, low temperature buffer layer 2 can be AlN buffer layer or GaN buffer layer.
Optionally, three-dimensional nucleating layer 3 can be GaN layer, with a thickness of 400~600nm.
Optionally, two-dimentional retrieving layer 4 can be GaN layer, with a thickness of 500~800nm.
Optionally, undoped GaN layer 5 with a thickness of 1~2um.
Optionally, N-type layer 6 can be to mix the GaN layer of Si, with a thickness of 1~2um.
Optionally, the thickness of electronic barrier layer 9 can be 20~100nm.
Optionally, P-type layer 10 can be GaN layer, with a thickness of 100~300nm.
Optionally, LED epitaxial slice can also include the p-type contact layer 11 being arranged in P-type layer 10.P-type contact Layer 11 can be the GaN layer of heavily doped Mg, with a thickness of 50~100nm.
Fig. 4 is a kind of manufacturing method flow chart of gallium nitride based LED epitaxial slice provided in an embodiment of the present invention, As shown in figure 4, the manufacturing method includes:
Step 401 provides a substrate.
Wherein, the Al of [0001] crystal orientation can be used in substrate2O3Sapphire Substrate.
Further, step 401 can also include:
Substrate is annealed 1~10min in hydrogen atmosphere, to clean substrate surface, nitrogen treatment then is carried out to substrate, Temperature when nitrogen treatment is controlled at 1000~1200 DEG C.
Wherein, the mode that substrate is made annealing treatment depends on the growth pattern of low temperature buffer layer.
When using PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) method deposit low temperature buffer layer When, carrying out annealing to substrate includes: that substrate is placed into the reaction chamber of PVD equipment, and vacuumizes to reaction chamber, Start to carry out heat temperature raising to substrate while vacuumizing.When the pressure in reaction chamber is evacuated to lower than 1*10-7When torr, it will heat Temperature is stablized at 350~750 DEG C, toasts to substrate, and baking time is 2~12min.
When using MOCVD (Metal-organic Chemical Vapor Deposition, metallo-organic compound Learn gaseous phase deposition) method deposit low temperature buffer layer when, to substrate carry out annealing include: that substrate is placed into MOCVD device Reaction chamber in, then made annealing treatment 10 minutes in hydrogen atmosphere, clean substrate surface, annealing temperature is at 1000 DEG C and 1100 Between DEG C, pressure is between 200torr~500torr.
Step 402, on substrate growing low temperature buffer layer.
Wherein, low temperature buffer layer can be GaN buffer layer, be also possible to AlN buffer layer.
When low temperature buffer layer is GaN buffer layer, mocvd method growing low temperature buffer layer can be used, comprising: firstly, will The reaction cavity temperature of MOCVD device is adjusted to 400 DEG C~600 DEG C, and pressure is adjusted to 200~600torr, grows 15~35nm Thick GaN buffer layer.
When low temperature buffer layer is AlN buffer layer, PVD method growing low temperature buffer layer can be used, comprising: by PVD equipment Reaction cavity temperature adjust to 400~700 DEG C, sputtering power is adjusted to 3000~5000W, pressure adjustment most 1~ 10mtorr grows the AlN buffer layer of 15~35nm thickness.
It should be noted that the undoped GaN layer in epitaxial layer, N-type layer, stress release layer, multiple quantum well layer, electronics Barrier layer, P-type layer and p-type contact layer can be grown using mocvd method.It in specific implementation, is usually to place the substrate in It is sent on graphite pallet in the reaction chamber of MOCVD device and carries out the growth of epitaxial material, therefore controlled in above-mentioned growth course Temperature and pressure actually refers to the temperature and pressure in reaction chamber.Specifically, using trimethyl gallium or trimethyl second as gallium Source, boron triethyl are mixed as indium source, trimethyl aluminium as silicon source, N-type as boron source, high pure nitrogen as nitrogen source, trimethyl indium Miscellaneous dose of selection silane, P-type dopant select two luxuriant magnesium.
Step 403, the growing three-dimensional nucleating layer on low temperature buffer layer.
In the present embodiment, three-dimensional nucleating layer can be GaN layer.
Illustratively, reaction chamber temperature being adjusted to 1000~1050 DEG C, chamber pressure is controlled in 300~600torr, Growth thickness is the three-dimensional nucleating layer of 400~600nm, and growth time is 10~20min.
Step 404 grows two-dimentional buffer layer on three-dimensional nucleating layer.
In the present embodiment, two-dimentional buffer layer can be GaN layer.
Illustratively, reaction chamber temperature being adjusted to 1050~1150 DEG C, chamber pressure is controlled in 100~300torr, Growth thickness is the two-dimentional buffer layer of 500~800nm, and growth time is 20~40min.
Step 405 grows undoped GaN layer on two-dimentional buffer layer.
Illustratively, reaction chamber temperature being adjusted to 1050~1200 DEG C, chamber pressure is controlled in 100~300torr, Growth thickness is the undoped GaN layer of 1~2um.
Step 406 grows N-type layer in undoped GaN layer.
In the present embodiment, N-type layer can be to mix the GaN layer of Si, and Si doping concentration can be 1018cm-3~1020cm-3。
Illustratively, reaction chamber temperature being adjusted to 1050~1200 DEG C, chamber pressure is controlled in 100~300torr, Growth thickness is the N-type layer of 1~2um.
Step 407, the growth stress releasing layer in N-type layer.
In the present embodiment, stress release layer includes the first superlattice structure and the second superlattices knot of multiple alternating growths Structure, the first superlattice structure are low temperature InGaN/GaN superlattice structure, and the second superlattice structure is that high temperature InGaN/GaN is super brilliant Lattice structure.
Optionally, stress release layer includes the first superlattice structure and the second superlattice structure of N number of alternating growth, 2≤N ≤12。
Further, the high temperature ingan layers in the low temperature ingan layer and the second superlattice structure in the first superlattice structure It is InxGa1-xN layers, 0.05 < x < 0.4.
Optionally, the thickness of the first superlattice structure 71 and the second superlattice structure 72 is equal, in order to periodically control The growth of stress release layer processed, so that the even density variation of the opening in V-type hole and V-type hole.
Illustratively, the high temperature ingan layers in the low temperature ingan layer and the second superlattice structure in the first superlattice structure Thickness be 1~2nm.The thickness of GaN layer in first superlattice structure and the GaN layer in the second superlattice structure is 10 ~40nm.
In other implementations, the thickness of the first superlattice structure 71 and the second superlattice structure 72 can not also phase Deng.
Further, stress release layer with a thickness of 100~150nm.
Illustratively, step 407 may include:
780 DEG C~880 DEG C at a temperature of, one superlattice structure of growth regulation.
830 DEG C~930 DEG C at a temperature of, two superlattice structure of growth regulation.
Illustratively, chamber pressure control is in 100~500torr, growth stress releasing layer.
Step 408 grows multiple quantum well layer on stress release layer.
Wherein, multiple quantum well layer includes the first kind multiple quantum well layer close to N-type layer, the third class volume close to P-type layer Sub- well layer and the second class multiple quantum well layer between first kind multiple quantum well layer and third class multiple quantum well layer.
First kind multiple quantum well layer by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, the second class multiple quantum wells Layer by multiple periods InaGa1-aN/GaN superlattices composition, third class multiple quantum well layer by multiple periods InaGa1-aN/ InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
Further, the In in first kind quantum well layer, the second class quantum well layer and third class quantum well layeraGa1-aN layers Thickness be equal, thereby may be ensured that the consistency of emission wavelength.
Illustratively, the In in first kind quantum well layeraGa1-aN layers, the In in the second class quantum well layeraGa1-aN layers, In in three classes quantum well layeraGa1-aN layers of thickness is 3~4nm.
Further, the Al in first kind quantum well layercGa1-cN layers, GaN layer and third class in the second class quantum well layer In in quantum well layerbGa1-bN layers of thickness is equal.
Optionally, the Al in first kind quantum well layercGa1-cN layers, the GaN layer in the second class quantum well layer and third class amount In in sub- well layerbGa1-bN layers of thickness is 9~20nm.
Al in other implementations, in first kind quantum well layercGa1-cN layers, the GaN layer in the second class quantum well layer With the In in third class quantum well layerbGa1-bN layers of thickness can also be unequal.
Optionally, the In in first kind quantum well layeraGa1-aN layers, the In in the second class quantum well layeraGa1-aN layers, third In in class quantum well layeraGa1-aN layers of growth temperature and growth pressure is equal.
Optionally, the AlGaN layer in first kind quantum well layer, the GaN layer in the second class quantum well layer and third class quantum In in well layerbGa1-bN layers of growth temperature and growth pressure is equal.
Illustratively, step 408 may include:
Controlling reaction chamber temperature is 750~830 DEG C, and chamber pressure is 100~500torr, grows first kind Quantum Well In in layeraGa1-aN layers, the In in the second class quantum well layeraGa1-aN layers, the In in third class quantum well layeraGa1-aN layers；
Controlling reaction chamber temperature is 850~900 DEG C, and chamber pressure is 100~500torr, grows first kind Quantum Well Al in layercGa1-cN layers, the GaN layer in the second class quantum well layer and the In in third class quantum well layerbGa1-bN layers.
Step 409 grows electronic barrier layer on multiple quantum well layer.
In the present embodiment, electronic barrier layer can be p-type AlGaN layer
Illustratively, reaction chamber temperature is adjusted to 800~1000 DEG C, chamber pressure control is in 50~500torr, life The long electronic barrier layer with a thickness of 20~100nm.
Step 410, the growing P-type layer on electronic barrier layer.
In the present embodiment, P-type layer is to mix the GaN layer of Mg, and the doping concentration of Mg can be 1 × 1019~1 × 1020cm-3。
Illustratively, reaction chamber temperature is adjusted to 850~950 DEG C, chamber pressure control is in 100~300torr, life The long P-type layer with a thickness of 100~300nm.
Step 411, the growing P-type contact layer in P-type layer.
In the present embodiment, p-type contact layer can be the GaN layer of heavily doped Mg.
Illustratively, reaction chamber temperature being adjusted to 850~1000 DEG C, chamber pressure is controlled in 100~300torr, Growth thickness is the p-type contact layer of 50~100nm.
After above-mentioned steps completion, the temperature of reaction chamber is down to 650~850 DEG C, is carried out at annealing in nitrogen atmosphere 5~15min is managed, room temperature is then gradually decreased to, terminates the epitaxial growth of light emitting diode.
The embodiment of the present invention by by stress release layer be set as include multiple alternating growths the first superlattice structure and Second superlattice structure.Wherein, the first superlattice structure is low temperature InGaN/GaN superlattice structure, and the first superlattice structure is adopted It is formed with low-temperature epitaxy, it is ensured that stress release layer has preferable stress release effect.But the first superlattice structure exists The formation in V-type hole can be caused when low-temperature epitaxy, therefore, the present invention passes through two superlattices of growth regulation after the first superlattice structure Structure, the second superlattice structure are high temperature InGaN/GaN superlattice structure, and under the high temperature conditions, the horizontal extension ability of GaN increases By force, the opening that V-type can be inhibited to cheat continues to become larger, to controlling the opening in V-type hole in suitable range, avoids V-type The case where hole opening is excessive, causes the interior quantum luminous efficiency reduction of LED appearance.Simultaneously under the high temperature conditions, the V-type of formation is cheated Density can gradually decrease, so as to improve the crystal quality of epitaxial layer.And the stress release layer in the present invention includes multiple The low temperature InGaN/GaN superlattice structure and high temperature InGaN/GaN superlattice structure of alternating growth, are released with the stress of single layer structure Layer (only including a low temperature InGaN/GaN superlattice structure and a high temperature InGaN/GaN superlattice structure) is put to compare, it is right The opening control effect in V-type hole is more preferable.
The foregoing is merely a prefered embodiment of the invention, is not intended to limit the invention, all in the spirit and principles in the present invention Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of gallium nitride based LED epitaxial slice, the gallium nitride based LED epitaxial slice include substrate and It successively grows low temperature buffer layer over the substrate, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer, answer Power releasing layer, multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer, which is characterized in that
The stress release layer includes the first superlattice structure and the second superlattice structure of multiple alternating growths, described the first to surpass Lattice structure is low temperature InGaN/GaN superlattice structure, and second superlattice structure is high temperature InGaN/GaN superlattices knot Structure.
2. gallium nitride based LED epitaxial slice according to claim 1, which is characterized in that the stress release layer With a thickness of 100~150nm.
3. gallium nitride based LED epitaxial slice according to claim 1, which is characterized in that the multiple quantum well layer packet It includes the first kind multiple quantum well layer close to the N-type layer, the third class multiple quantum well layer close to the P-type layer and is located at institute State the second class multiple quantum well layer between first kind multiple quantum well layer and the third class multiple quantum well layer；
The first kind multiple quantum well layer by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, the second class volume Sub- well layer by multiple periods InaGa1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods InaGa1-aN/InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
4. gallium nitride based LED epitaxial slice according to claim 3, which is characterized in that the first kind Quantum Well In in layer, the second class quantum well layer and the third class quantum well layeraGa1-aN layers of thickness is equal.
5. gallium nitride based LED epitaxial slice according to claim 3, which is characterized in that the first kind Quantum Well Al in layercGa1-cN layers, the GaN layer in the second class quantum well layer and the In in the third class quantum well layerbGa1-bN layers Thickness be equal.
6. a kind of manufacturing method of gallium nitride based LED epitaxial slice, which is characterized in that the manufacturing method includes:
One substrate is provided；
Successively growing low temperature buffer layer, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer over the substrate；
The growth stress releasing layer in the N-type layer, the stress release layer include the first superlattices knot of multiple alternating growths Structure and the second superlattice structure, first superlattice structure are low temperature InGaN/GaN superlattice structure, second superlattices Structure is high temperature InGaN/GaN superlattice structure；
Multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer are successively grown on the stress release layer.
7. manufacturing method according to claim 6, which is characterized in that the growth stress releasing layer in the N-type layer, packet It includes:
780 DEG C~880 DEG C at a temperature of, grow first superlattice structure；
830 DEG C~930 DEG C at a temperature of, grow second superlattice structure.
8. manufacturing method according to claim 6, which is characterized in that the multiple quantum well layer includes close to the N-type layer First kind multiple quantum well layer, close to the P-type layer third class multiple quantum well layer and be located at the first kind multiple quantum wells The second class multiple quantum well layer between layer and the third class multiple quantum well layer；
The first kind multiple quantum well layer by multiple periods InaGa1-aN/AlcGa1-cN superlattices composition, the second class volume Sub- well layer by multiple periods InaGa1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods InaGa1-aN/InbGa1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.
9. manufacturing method according to claim 8, which is characterized in that the first kind quantum well layer, the second class amount In in sub- well layer and the third class quantum well layeraGa1-aN layers of thickness is equal.
10. manufacturing method according to claim 8, which is characterized in that the Al in the first kind quantum well layercGa1-cN Layer, the GaN layer in the second class quantum well layer and the In in the third class quantum well layerbGa1-bN layers of thickness is equal.
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