CN109360876A - A kind of epitaxial wafer of light emitting diode and preparation method thereof - Google Patents

A kind of epitaxial wafer of light emitting diode and preparation method thereof Download PDF

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Publication number
CN109360876A
CN109360876A CN201811015039.5A CN201811015039A CN109360876A CN 109360876 A CN109360876 A CN 109360876A CN 201811015039 A CN201811015039 A CN 201811015039A CN 109360876 A CN109360876 A CN 109360876A
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layer
gan
ingan
layers
quantum well
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吕蒙普
叶芸
郭炳磊
胡加辉
李鹏
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Abstract

The invention discloses epitaxial wafers of a kind of light emitting diode and preparation method thereof, belong to light emitting diode manufacturing field.The compound insert layer being arranged between electronic barrier layer and InGaN/GaN multiple quantum well layer can be matched with the last one GaN quantum barrier layer in InGaN/GaN multiple quantum well layer doped with Al element, it can play the role of part blocking electronics doped with the last one GaN quantum barrier layer of Al element, by electronic blocking in InGaN/GaN multiple quantum well layer, and the AlN layer of potential barrier with higher can also play the role of stopping electronics with InAlGaN layers in compound insert layer.Simultaneously, due to being doped with magnesium elements in AlN layers and InAlGaN layers, AlN layers can be used as hole source with InAlGaN layers, can by electronic blocking in InGaN/GaN multiple quantum well layer while, it is able to enter more holes in InGaN/GaN multiple quantum well layer compound and then luminous with electronics progress, the combined efficiency of electronics and hole in InGaN/GaN multiple quantum well layer is improved, and then improves the luminous efficiency of light emitting diode.

Description

A kind of epitaxial wafer of light emitting diode and preparation method thereof
Technical field
The present invention relates to light emitting diode manufacturing field, in particular to the epitaxial wafer of a kind of light emitting diode and its preparation side Method.
Background technique
Light emitting diode is a kind of semiconductor diode that electric energy can be converted to luminous energy, have small in size, the service life is long, The advantages that low in energy consumption, is widely used in automobile signal light, traffic lights, display screen and lighting apparatus at present.Epitaxial wafer It is the foundation structure for making light emitting diode, the structure of epitaxial wafer includes substrate and the epitaxial layer grown on substrate.Wherein, The structure of epitaxial layer specifically includes that buffer layer, N-type GaN layer, the InGaN/GaN multiple quantum well layer, electricity successively grown on substrate Sub- barrier layer and p-type GaN layer.
When having electric current to pass through in epitaxial wafer, the hole in electronics and p-type GaN layer in N-type GaN layer all can be to InGaN/ GaN multiple quantum well layer is mobile, and recombination luminescence is carried out in InGaN/GaN multiple quantum well layer.But the physics based on hole itself Characteristic, the number of cavities being capable of forming in p-type GaN layer is less, cause to be able to enter InGaN/GaN multiple quantum well layer and The limited amount for carrying out luminous hole in InGaN/GaN multiple quantum well layer with electronics, a large amount of electronics from N-type GaN layer exist Combined efficiency in InGaN/GaN multiple quantum well layer is lower, and the luminous efficiency of light emitting diode is lower.
Summary of the invention
The embodiment of the invention provides epitaxial wafers of a kind of light emitting diode and preparation method thereof, can be improved light-emitting diodes The luminous efficiency of pipe.The technical solution is as follows:
The embodiment of the invention provides a kind of epitaxial wafer of light emitting diode, the epitaxial wafer includes substrate and stacks gradually Buffer layer, N-type GaN layer, InGaN/GaN multiple quantum well layer, compound insert layer and p-type GaN layer over the substrate is set,
Wherein, the InGaN/GaN multiple quantum well layer adulterates along the last one GaN quantum barrier layer that the direction of growth is laminated There is Al element, the compound insert layer includes the AlN layer and InAlGaN layers, described AlN layers and the InAlGaN stacked gradually Doped with Mg element in layer.
Optionally, the doping concentration of Mg is greater than or equal to 5 × 10 in InAlGaN layers described19cm-3, be less than or equal to 1 × 1020cm-3。
Optionally, the doping concentration of Mg is less than the doping concentration of Mg in described InAlGaN layers in AlN layers described.
Optionally, the content of the Al component in AlN layers described is greater than the content of the Al component in described InAlGaN layers.
Optionally, the thickness of the electronic barrier layer is greater than 0nm and is less than or equal to 20nm.
Optionally, the last one GaN quantum barrier layer with a thickness of 3~8nm.
Optionally, AlN layers of the thickness is greater than 0nm and is less than or equal to 4nm.
The embodiment of the invention provides a kind of preparation method of the epitaxial wafer of light emitting diode, the preparation method includes:
One substrate is provided；
Grown buffer layer over the substrate；
N-type GaN layer is grown on the buffer layer；
InGaN/GaN multiple quantum well layer is grown in the N-type GaN layer；
The growing mixed insert layer on the InGaN/GaN multiple quantum well layer；
Electronic barrier layer is grown in the compound insert layer；
The growth P-type GaN layer on the electronic barrier layer,
Wherein, the InGaN/GaN multiple quantum well layer adulterates along the last one GaN quantum barrier layer that the direction of growth is laminated There is Al element, the compound insert layer includes the AlN layer and InAlGaN layers, described AlN layers and the InAlGaN stacked gradually Doped with Mg element in layer.
Optionally, AlN layers of the growth temperature is 800~900 DEG C, and InAlGaN layers of the growth temperature is 700- 800℃。
Optionally, when growing described AlN layers, to the intracavitary TMAl for being passed through 50~100sccm of reflection, described in growth At InAlGaN layers, to the intracavitary TMAl for being passed through 20~50sccm of reflection.
Technical solution provided in an embodiment of the present invention has the benefit that more in electronic barrier layer and InGaN/GaN The compound insert layer being arranged between quantum well layer can in InGaN/GaN multiple quantum well layer doped with Al element the last one GaN quantum barrier layer matches, and can play the role of part blocking electronics doped with the last one GaN quantum barrier layer of Al element, By electronic blocking in InGaN/GaN multiple quantum well layer, and in compound insert layer the AlN layer of potential barrier with higher with InAlGaN layers can also play the role of stopping electronics.Simultaneously as being doped with magnesium elements, AlN in AlN layers and InAlGaN layers Layer with InAlGaN layers can be used as hole source, can by electronic blocking in InGaN/GaN multiple quantum well layer while, It is able to enter more holes in InGaN/GaN multiple quantum well layer compound and then luminous with electronics progress, improves The combined efficiency of electronics and hole in InGaN/GaN multiple quantum well layer, at the same time compound insert layer and the last one GaN barrier layer Combined effect the restriction effect of electronics overflow is reinforced, that is, the electronic barrier layer of thinner thickness can be used to stop electronics, phase Traditional electronic barrier layer thickness is thinned, the luminous efficiency of light emitting diode also can be improved.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of structural schematic diagram of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of the epitaxial wafer of another light emitting diode provided in an embodiment of the present invention；
Fig. 3 is a kind of preparation method flow chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention；
Fig. 4 is the preparation method process of the epitaxial wafer of another light emitting diode provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
Fig. 1 is a kind of structural schematic diagram of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention.As shown in Figure 1, The epitaxial wafer includes substrate 1 and the buffer layer being cascading on substrate 12, N-type GaN layer 3, InGaN/GaN multiple quantum wells Layer 4, compound insert layer 5, electronic barrier layer 6 and p-type GaN layer 7.
Wherein, InGaN/GaN multiple quantum well layer 4 adulterates along the last one GaN quantum barrier layer 41 that the direction of growth is laminated Have an Al element, compound insert layer 5 includes the AlN layer 51 and InAlGaN layer 52 stacked gradually, AlN layer 51 in InAlGaN layer 52 Doped with Mg element.
The compound insert layer being arranged between electronic barrier layer and InGaN/GaN multiple quantum well layer can be more with InGaN/GaN The last one GaN quantum barrier layer in quantum well layer doped with Al element matches, doped with the last one GaN amount of Al element Sub- barrier layer can play the role of part and stop electronics, by electronic blocking in InGaN/GaN multiple quantum well layer, and compound insert layer In the AlN layer of potential barrier with higher can also play the role of stopping electronics with InAlGaN layers.Simultaneously as AlN layers with Magnesium elements are doped in InAlGaN layers, AlN layers can be used as hole source with InAlGaN layers, and electronic blocking can exist While in InGaN/GaN multiple quantum well layer, make more holes be able to enter in InGaN/GaN multiple quantum well layer with electronics into Row is compound and then luminous, improves the combined efficiency of electronics and hole in InGaN/GaN multiple quantum well layer, and then improve hair The luminous efficiency of optical diode.
Due to the last one GaN quantum barrier layer and combination socket of InGaN/GaN multiple quantum well layer in the embodiment of the present invention Entering layer can play the role of stopping electronics, therefore the electronic barrier layer in the epitaxial wafer of relatively traditional light emitting diode, this Inventive embodiments, can be corresponding in the case where not influencing electronics and the combined efficiency in hole in InGaN/GaN multiple quantum well layer The thickness of ground lightening holes electronic barrier layer, the thinned of the thickness of electronic barrier layer may make from InGaN/GaN multiple quantum well layer The light of sending need during being transmitted to outside light emitting diode by medium reduce so that light emitting diode Luminous efficiency is available to be further increased.
Fig. 2 is the structural schematic diagram of the epitaxial wafer of another light emitting diode provided in an embodiment of the present invention.Such as Fig. 2 institute Show, which may include substrate 1 and the buffer layer being cascading on substrate 12, N-type GaN layer 3, N-type current expansion Layer 8, superlattice structure 9, InGaN/GaN multiple quantum well layer 4, compound insert layer 5, electronic barrier layer 6, p-type GaN layer 7 and ohm Contact layer 10.
As shown in Fig. 2, buffer layer 2 may include low temperature GaN buffer 21 and layer of undoped gan 22.
Wherein, the thickness of low temperature GaN buffer 21 can be 15~30nm, the thickness of layer of undoped gan 22 can for 0.8 to 3.0μm.This set can reduce substrate 1 and the lattice mismatch between N-type GaN layer 4, guarantee the quality of forming film of epitaxial layer.
Illustratively, the thickness of N-type GaN layer 3 can be 2~3 μm.
Wherein, the doped chemical in N-type GaN layer 3 can be Si, doping concentration of the Si in N-type GaN layer 3 can for 5 × 1018cm-3。
Optionally, N-type current extending 8 can be used GaN material production, due in N-type current extending Si adulterate it is dense Spend it is lower, the setting of N-type current extending can play the role of extend electric current, further increase the luminous effect of light emitting diode Rate.
Wherein, the thickness of N-type current extending 8 can be 100~300nm.Doped chemical in N-type current extending 8 can For Si, doping concentration of the Si in N-type current extending 8 can be 2 × 1017cm-3。
Optionally, superlattice structure 9 includes alternately stacked InGaN layer 91, AlxGa1-xN layer 92 and AlyGa1-yN layer 93, Wherein, 0 y≤1 < x <.Due to the Al in the superlattice structurexGa1-xN layers and AlyGa1-yN layers of potential barrier is higher, and electronics is by N When type GaN layer enters InGaN/GaN multiple quantum well layer, Al will receivexGa1-xN layers and AlyGa1-yN layers of blocking, so that electric Son can be extending transversely when entering InGaN/GaN multiple quantum well layer, and the area that electronics enters InGaN/GaN multiple quantum well layer increases Greatly, AlxGa1-xN layers of potential barrier compares AlyGa1-yN layers of potential barrier is low, so that electronics is by AlxGa1-xN layers and AlyGa1-yN layers points Flow resistance gear, electronics will not congestion in AlxGa1-xAt N layers or AlyGa1-yAt N layers, electronics can more uniformly enter InGaN/ GaN multiple quantum well layer.This superlattice structure can be realized to carry out good and equably extends to the electric current in light emitting diode, And then improve the luminous efficiency of light emitting diode.
In the present embodiment, InGaN/GaN multiple quantum well layer 4 may include the shallow well layer 42 stacked gradually and luminous well layer 43。
Wherein, shallow well layer 42 may include alternately stacked InGaN well layer 421 and GaN barrier layer 422, InGaN well layer 421 Thickness can be 1~3nm, and the thickness of GaN barrier layer 422 can be 6~12nm.
Optionally, the number of plies of the number of plies of InGaN well layer 421 and GaN barrier layer 422 can be 5~10.The setting of shallow well layer is being sent out The effect of certain stress release can be played before ligh trap layer, guarantee the crystal quality of luminous well layer and then guarantee light emitting diode Luminous efficiency.
The well layer 43 that shines include alternately stacked InGaN quantum well layer 431 and GaN quantum barrier layer 432 and last A InGaN quantum well layer 431 and the last one GaN quantum barrier layer 41.
Wherein, the thickness of InGaN quantum well layer 431 can be 2~4nm, the thickness of GaN quantum barrier layer 432 can for 10~ 15nm。
It should be noted that the content of indium component is 10%~30% in InGaN well layer 421.InGaN quantum well layer 431 The content of middle indium component can be 50%~70%, and the content just because of In component in shallow well layer 42 is than In group in luminous well layer 43 Point content it is few so that electronics in luminous well layer 43 with the main recombination luminescence in hole without in shallow well layer 42 with hole answer It closes and shines, shallow well layer 42 primarily serves the effect of stress release.
Optionally, the number of plies of InGaN quantum well layer 431 and the number of plies of GaN quantum barrier layer 432 can be 9~15.
Illustratively, the thickness of the last one GaN quantum barrier layer 41 can be 3~8nm.The last one GaN quantum barrier layer Thickness setting in range above, can in not influencing InGaN/GaN multiple quantum well layer electronics and the combined efficiency in hole premise Under, part is carried out to the thickness of InGaN/GaN multiple quantum well layer entirety and is thinned, InGaN/GaN multiple quantum well layer is advantageously reduced The light of sending needed during being transmitted to outside light emitting diode by medium so that light emitting diode shine Efficiency is available to be further increased.
Illustratively, the content of the Al component in AlN layer 51 is greater than the content of the Al component in InAlGaN layer 52.It is this The Al constituent content being arranged in InAlGaN layers avoidable is excessively high, and then influences InAlGaN layers of quality.
Optionally, the doping concentration of Mg is greater than or equal to 5 × 10 in InAlGaN layer 52 in compound insert layer 519cm-3, small In or equal to 1 × 1020cm-3.The doping concentration setting of Mg in the above range can be in the matter for guaranteeing epitaxial wafer in InAlGaN layers Make the number of cavities entered in InGaN/GaN multiple quantum well layer more while amount, the luminous efficiency of light emitting diode is preferable.
Further, the doping concentration of Mg is smaller than the doping concentration of Mg in InAlGaN layer 52 in AlN layer 51.In AlN layers Crystal matter of the Mg adulterated during the doping concentration of Mg is AlN layers certifiable lower than the doping concentration of Mg in InAlGaN layer to epitaxial layer Amount has excessive influence, guarantees the total quality of epitaxial wafer.
Optionally, the thickness of AlN layer 51 can be greater than 0nm and be less than or equal to 4nm in compound insert layer 5.In this thickness Under the conditions of setting, it is ensured that the quality of the epitaxial wafer of light emitting diode is conducive to hole injection InGaN/GaN multiple quantum well layer In.
Further, the thickness of InAlGaN layer 52 can be within the scope of 20~40nm in compound insert layer 5, and this set can The quality for guaranteeing the epitaxial wafer of light emitting diode is also beneficial in hole injection InGaN/GaN multiple quantum well layer.
Optionally, the thickness of electronic barrier layer 6 is greater than 0nm and is less than or equal to 20nm.The thickness of electronic barrier layer is arranged Within this range, good blocking electronics can be played the role of in guarantee electronic barrier layer, and it is good to guarantee that light emitting diode has Good luminous efficiency.
In the present embodiment, electronic barrier layer 6 can be p-type AlGaN layer.
Doped chemical in electronic barrier layer 6 can be Mg, and in electronic barrier layer 6 Mg doping concentration can for 5 × 1017cm-3。
The thickness of p-type GaN layer 7 can be 60~100nm, and doped chemical can be Mg, and the doping of the Mg in p-type GaN layer 7 is dense Degree is not less than 5 × 1019cm-3。
The setting of ohmic contact layer 10 can prepare for the subsequent production of the chip of light emitting diode, can be in Ohmic contact P electrode is made on layer 10.Ohmic contact layer can reduce the operating voltage of P electrode, and the operating voltage of P electrode can be prevented excessive, And generate the waste that excessive heat causes energy.
Ohmic contact layer 10 can be made of GaN material or InGaN material, can also be mixed in ohmic contact layer 10 Perhaps to form p-type ohmic contact layer or N-type ohmic contact layer, the present invention compares with no restrictions Si Mg.
Fig. 3 is a kind of preparation method flow chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention, such as Fig. 3 institute Show, which includes:
S101: a substrate is provided.
S102: grown buffer layer on substrate.
S103: N-type GaN layer is grown on the buffer layer.
S104: InGaN/GaN multiple quantum well layer is grown in N-type GaN layer.
S105: the growing mixed insert layer on InGaN/GaN multiple quantum well layer.
S106: electronic barrier layer is grown in compound insert layer.
S107: the growth P-type GaN layer on electronic barrier layer.
The compound insert layer being arranged between electronic barrier layer and InGaN/GaN multiple quantum well layer can be more with InGaN/GaN The last one GaN quantum barrier layer in quantum well layer doped with Al element matches, doped with the last one GaN amount of Al element Sub- barrier layer can play the role of part and stop electronics, by electronic blocking in InGaN/GaN multiple quantum well layer, and compound insert layer In the AlN layer of potential barrier with higher can also play the role of stopping electronics with InAlGaN layers.Simultaneously as AlN layers with Magnesium elements are doped in InAlGaN layers, AlN layers can be used as hole source with InAlGaN layers, and electronic blocking can exist While in InGaN/GaN multiple quantum well layer, make more holes be able to enter in InGaN/GaN multiple quantum well layer with electronics into Row is compound and then luminous, improves the combined efficiency of electronics and hole in InGaN/GaN multiple quantum well layer, and then improve hair The luminous efficiency of optical diode.
Fig. 4 is a kind of preparation method flow chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention, such as Fig. 4 institute Show, which includes:
S201: a substrate is provided.
Wherein, the material of substrate can be gallium nitride single crystal, sapphire, monocrystalline silicon, single-crystal silicon carbide etc..
On substrate before grown buffer layer, substrate can be made annealing treatment in hydrogen atmosphere.With the table to substrate Face carries out cleaning treatment, guarantees the quality of the epitaxial layer grown on substrate.
Annealing temperature can be 1040~1180 DEG C.
Further, can also nitrogen treatment be carried out to substrate after making annealing treatment to substrate, i.e., in the table of substrate Face growing AIN layer reduces the lattice mismatch between substrate and N-type epitaxy layer.
S202: grown buffer layer on substrate.
Wherein, buffer layer may include low temperature GaN buffer and undoped GaN buffer layer.
Optionally, the growth pressure of low temperature GaN buffer can be controlled in 100~200torr, the life of low temperature GaN buffer Long temperature can be 500~600 DEG C.
Optionally, the growth thickness of low temperature GaN buffer can be 15~30nm.
Illustratively, the growth temperature of layer of undoped gan can be 1100~1200 DEG C, growth pressure can for 100~ 200Torr.The quality of the layer of undoped gan grown with this condition is preferable.
Illustratively, the thickness of layer of undoped gan can be 0.8~3 μm.
S203: N-type GaN layer is grown on the buffer layer.
Illustratively, the thickness of N-type GaN layer can be 30~80nm.
Optionally, the doped chemical of N-type GaN layer is Si element, and the doping concentration of Si element can be 2 × 1017cm-3。
Wherein, the growth temperature of N-type GaN layer can be 1000~1200 DEG C, and growth pressure can be 100~200Torr.
S204: N-type current extending is grown in N-type GaN layer.
GaN material production can be used in N-type current extending.
Illustratively, the thickness of N-type current extending can be 100~300nm.
Optionally, the doped chemical of N-type current extending is Si element, and the doping concentration of Si element can be 5 × 1018cm-3。
Wherein, the growth temperature of N-type current extending can be 1000~1200 DEG C, growth pressure can for 100~ 200Torr。
S205: superlattice structure is grown on N-type current extending.
Wherein, superlattice structure includes alternately stacked InGaN layer, AlxGa1-xN layers and AlyGa1-yN layers, wherein 0 < x Y≤1 <.
Optionally, the growth temperature of superlattice structure is 800~900 DEG C.The superlattices knot obtained under the conditions of this temperature The quality of structure is preferable, can reduce the crystal defect in epitaxial wafer.
Optionally, the growth pressure of superlattice structure is 200~300 DEG C.The superlattices knot obtained under this growth conditions The quality of structure is preferable, can reduce the crystal defect in epitaxial wafer.
Illustratively, in growth AlxGa1-xN layers and AlyGa1-yAt N layers, the flow to the intracavitary TMAl being passed through of reflection can be 10~100sccm.The superlattice structure grown with this condition can be while effectively playing current expansion effect, no It will affect the quantity that can enter the electronics of InGaN/GaN multiple quantum well layer and hole progress recombination luminescence, guarantee light emitting diode Luminous efficiency.
S206: InGaN/GaN multiple quantum well layer is grown on superlattice structure.
InGaN/GaN multiple quantum well layer may include the shallow well layer stacked gradually and luminous well layer.
Wherein, shallow well layer may include alternately stacked InGaN well layer and GaN barrier layer, the thickness of InGaN well layer can for 1~ The thickness of 3nm, GaN barrier layer can be 6~12nm.
The growth temperature of InGaN well layer can be 850~900 DEG C, and the growth temperature of GaN barrier layer can be 850~900 DEG C. The growth pressure of InGaN well layer can be 100~300Torr, and the growth pressure of GaN barrier layer can be 100~300Torr.
Luminous well layer includes alternately stacked InGaN quantum well layer and GaN quantum barrier layer and the last one InGaN amount Sub- well layer and the last one GaN quantum barrier layer.
Wherein, the thickness of InGaN quantum well layer can be 2~4nm, and the thickness of GaN quantum barrier layer can be 10~15nm.
The thickness of the last one GaN quantum barrier layer can be 3~8nm.
The growth temperature of InGaN quantum well layer can be 800~850 DEG C, and GaN quantum barrier layer and the last one GaN quantum are built The growth temperature of layer can be 850~900 DEG C.The growth pressure of InGaN quantum well layer can be 100~300Torr, GaN quantum The growth pressure of barrier layer and the last one GaN quantum barrier layer can be 100~300Torr.
Wherein, InGaN/GaN multiple quantum well layer is along the last one GaN quantum barrier layer that the direction of growth is laminated doped with Al Element.
S207: the growing mixed insert layer on InGaN/GaN multiple quantum well layer.
Wherein, compound insert layer includes the AlN layer that stacks gradually and InAlGaN layers, AlN layers with InAlGaN layers in mix It is miscellaneous to have Mg element.
Optionally, in compound insert layer, AlN layers of growth temperature is 800~900 DEG C, and InAlGaN layers of growth temperature is 700-800℃.With when being grown under this condition for InAlGaN layers, light emitting diode shines AlN layer in compound insert layer Efficiency is preferable.
Illustratively, AlN layers of growth pressure can be 100~200torr, InAlGaN layer of growth pressure for 100~ 200torr.AlN layer in compound insert layer with when being grown under this condition for InAlGaN layers, the luminous effect of light emitting diode Rate is preferable.
Optionally, in growing AIN layer, to the intracavitary TMAl for being passed through 50~100sccm is reflected, in InAlGaN layers of growth When, to the intracavitary TMAl for being passed through 20~50sccm of reflection.
S208: electronic barrier layer is grown in compound insert layer.
In the present embodiment, electronic barrier layer can be p-type AlGaN layer.
Doped chemical in electronic barrier layer can be Mg, and the doping concentration of Mg is 5 × 10 in electronic barrier layer17cm-3。
S209: the growth P-type GaN layer on electronic barrier layer.
The thickness of p-type GaN layer can be 60~100nm, and doped chemical can be Mg, the doping concentration of the Mg in p-type GaN layer Not less than 5 × 1019cm-3。
The growth temperature of p-type GaN layer can be 900~1000 DEG C, and the growth pressure of p-type GaN layer can be 100~300Torr.
S210: the growing P-type contact layer in p-type GaN layer.
The setting of ohmic contact layer can prepare for the subsequent production of the chip of light emitting diode, can be in ohmic contact layer Upper production P electrode.Ohmic contact layer can reduce the operating voltage of P electrode, and the operating voltage of P electrode can be prevented excessive, and produce Raw excessive heat causes the waste of energy.
Optionally, after ohmic contact layer is grown, it can will reflect that intracavitary temperature is adjusted to 600~900 DEG C, in purity nitrogen Atmosphere enclose it is lower epitaxial wafer is made annealing treatment 10~20 minutes, and be cooled to room temperature, terminate the growth of epitaxial wafer.This processing can swash Mg atom in epitaxial layer living, improves the number of cavities in epitaxial layer.
Above-mentioned growth course can be using MOCVD (Metal-Organic Chemical Vapor Deposition, gold Belonging to organic compound chemical vapor deposition) method carries out in the reaction chamber of MOCVD device.
Using another epitaxial slice structure provided in an embodiment of the present invention, in a kind of situation provided in an embodiment of the present invention In, the growth temperature of N-type GaN layer is 1100 DEG C, the doping concentration of Si is 5 × 1018cm-3, the growth of N-type GaN current extending Temperature is 1100 DEG C, the doping concentration of Si is 2 × 1017cm-3。
Shallow well layer includes the InGaN well layer of 6 2nm and the GaN barrier layer of 6 70nm, and the well layer that shines composition is by 15 3nm's In0.18Ga0.82The GaN quantum barrier layer of N quantum well layer and 15 10.5nm are combined into, and P-type electron barrier layer is p-type Al0.16Ga0.84N layers, p-type Al0.16Ga0.84The doping concentration of Mg is 5 × 10 in N layers17cm-3, the growth temperature of p-type GaN layer is 900~1000 DEG C, p-type GaN layer with a thickness of 60~100nm, the doping concentration of Mg is not less than 5 × 10 in p-type GaN layer19cm-3。
AlN layers of growth temperature is 800~900 DEG C, and 150torr, AlN layer of pressure reflects when growing intracavitary not to be passed through TEGa, the AlN layers of flow for reflecting the intracavitary TMAl being passed through in growth are 60sccm.And AlN layers with a thickness of 4nm；InAlGaN Layer reflects that the flow of the intracavitary TMAl being passed through is 30sccm in growth, and InAlGaN layers of growth temperature is 700-800 DEG C, raw Long pressure is that the doping concentration of Mg in 200 DEG C, InAlGaN layers is 5 × 1019cm-3, InAlGaN layers with a thickness of 30nm；
Electronic barrier layer is p-type Al0.16Ga0.84N layers, the doping concentration of Mg is 5 × 10 in electronic barrier layer17cm-3, electronics In growth, the flow to the intracavitary TMAl being passed through of reflection is 120sccm on barrier layer.Electronic barrier layer with a thickness of 20nm.
The epitaxial wafer obtained with this condition is cleaned, is deposited, the semiconducter process such as photoetching, and then obtains list Light-emitting diode chip for backlight unit of the chips having a size of 10 × 25mil, the result obtained after testing the light-emitting diode chip for backlight unit Are as follows: test electric current be 120mA, operating voltage 3.09V, brightness 199mw.
Conventional LED chip (removes compound insert layer and the last one GaN quantum barrier layer, other structures and growth The epitaxial wafer grown under conditions of condition is all the same) test result are as follows: test electric current be 120mA, operating voltage 3.10V, Brightness is 197mw.
Compared with the epitaxial wafer of conventional LED chip, the luminous efficiency of light-emitting diode chip for backlight unit is mentioned in the present embodiment High by 1%, operating voltage reduces 0.01V.Luminous efficiency is improved.
Using another epitaxial slice structure provided in an embodiment of the present invention, in another situation provided in an embodiment of the present invention In, other growth conditions are identical, and the AlN layers of flow for reflecting the intracavitary TMAl being passed through in growth are 80sccm, AlN layers of thickness For 2nm, the InAlGaN layers of flow for reflecting the intracavitary TMAl being passed through in growth are 30sccm, and the doping of Mg is dense in InAlGaN layers Degree is 5 × 1019cm-3, InAlGaN layers with a thickness of 20nm, electronic barrier layer is in growth, to reflecting the intracavitary TMAl being passed through Flow be 150sccm.Electronic barrier layer with a thickness of 15nm.
Equally, after the growth for terminating epitaxial wafer, which is cleaned, is deposited, the semiconductor machinings such as photoetching Light-emitting diode chip for backlight unit of the single chip having a size of 10 × 25mil is made in technique, carries out embodiment to the light-emitting diode chip for backlight unit The test of the same terms in two, obtained result are as follows: test electric current be 120mA, operating voltage 3.09V, brightness 200mw, Compared with the epitaxial wafer of conventional LED chip, the luminous efficiency of light-emitting diode chip for backlight unit is improved in the present embodiment 1.5%.
Therefore, the epitaxial slice structure in the present invention compared with the prior art in the epitaxial layer structure of light emitting diode can actually Improve the luminous efficiency of light emitting diode.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of epitaxial wafer of light emitting diode, which is characterized in that the epitaxial wafer includes substrate and is cascading in institute State buffer layer, N-type GaN layer, InGaN/GaN multiple quantum well layer, compound insert layer, electronic barrier layer and the p-type GaN on substrate Layer,
Wherein, the InGaN/GaN multiple quantum well layer is along the last one GaN quantum barrier layer that the direction of growth is laminated doped with Al Element, the compound insert layer include the AlN layer that stacks gradually with InAlGaN layer, described AlN layers and it is InAlGaN layers described in Doped with Mg element.
2. epitaxial wafer according to claim 1, which is characterized in that in InAlGaN layers described the doping concentration of Mg be greater than or Equal to 5 × 1019cm-3, it is less than or equal to 1 × 1020cm-3。
3. epitaxial wafer according to claim 2, which is characterized in that the doping concentration of Mg is less than described in AlN layers described The doping concentration of Mg in InAlGaN layers.
4. epitaxial wafer according to claim 1, which is characterized in that the content of the Al component in AlN layers described is greater than described The content of Al component in InAlGaN layers.
5. epitaxial wafer according to any one of claims 1 to 4, which is characterized in that the thickness of the electronic barrier layer is greater than 0nm and be less than or equal to 20nm.
6. preparation method according to any one of claims 1 to 4, which is characterized in that the last one described GaN quantum barrier layer With a thickness of 3~8nm.
7. preparation method according to any one of claims 1 to 4, which is characterized in that AlN layers of the thickness is greater than 0nm And it is less than or equal to 4nm.
8. a kind of preparation method of the epitaxial wafer of light emitting diode, which is characterized in that the preparation method includes:
One substrate is provided；
Grown buffer layer over the substrate；
N-type GaN layer is grown on the buffer layer；
InGaN/GaN multiple quantum well layer is grown in the N-type GaN layer；
The growing mixed insert layer on the InGaN/GaN multiple quantum well layer；
Electronic barrier layer is grown in the compound insert layer；
The growth P-type GaN layer on the electronic barrier layer,
Wherein, the InGaN/GaN multiple quantum well layer is along the last one GaN quantum barrier layer that the direction of growth is laminated doped with Al Element, the compound insert layer include the AlN layer that stacks gradually with InAlGaN layer, described AlN layers and it is InAlGaN layers described in Doped with Mg element.
9. preparation method according to claim 8, which is characterized in that AlN layers of the growth temperature is 800~900 DEG C, InAlGaN layers of the growth temperature is 700-800 DEG C.
10. preparation method according to claim 8, which is characterized in that intracavitary logical to reflecting when growing described AlN layers The TMAl for entering 50~100sccm, when growing described InAlGaN layers, to the intracavitary TMAl for being passed through 20~50sccm of reflection.
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Application publication date: 20190219