CN109950375A - LED epitaxial slice and its growing method - Google Patents

LED epitaxial slice and its growing method Download PDF

Info

Publication number
CN109950375A
CN109950375A CN201910097795.5A CN201910097795A CN109950375A CN 109950375 A CN109950375 A CN 109950375A CN 201910097795 A CN201910097795 A CN 201910097795A CN 109950375 A CN109950375 A CN 109950375A
Authority
CN
China
Prior art keywords
sublayer
silicon
doping concentration
laminated construction
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910097795.5A
Other languages
Chinese (zh)
Other versions
CN109950375B (en
Inventor
姚振
从颖
胡加辉
李鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HC Semitek Zhejiang Co Ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN201910097795.5A priority Critical patent/CN109950375B/en
Publication of CN109950375A publication Critical patent/CN109950375A/en
Application granted granted Critical
Publication of CN109950375B publication Critical patent/CN109950375B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention discloses a kind of LED epitaxial slice and its growing methods, belong to technical field of semiconductors.Epitaxial wafer includes substrate, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer, and n type semiconductor layer includes the multiple laminated construction stacked gradually, and laminated construction includes the first sublayer, the second sublayer and third sublayer stacked gradually;The material of the material of first sublayer, the material of the second sublayer and third sublayer is all made of the gallium nitride of doped silicon, and the doping concentration of silicon in the first sublayer of multiple laminated construction, the doping concentration of silicon in the second sublayer of multiple laminated construction, the doping concentration of silicon is successively reduced along the stacking direction of multiple laminated construction in the third sublayer of multiple laminated construction;In the same laminated construction, the doping concentration of silicon is greater than the doping concentration of silicon in third sublayer in the first sublayer, and the doping concentration of silicon is greater than the doping concentration of silicon in the second sublayer in third sublayer.The luminous efficiency of LED can be improved in the present invention.

Description

LED epitaxial slice and its growing method
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its growing method.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous Subcomponent.As a kind of New Solid lighting source efficiently, environmentally friendly, green, LED is widely used in rapidly traffic The fields such as signal lamp, automobile interior exterior lamp, landscape light in city, cell phone back light source.The core component of LED is chip, improves chip Luminous efficiency be the target constantly pursued in LED application process.
Chip includes epitaxial wafer and the electrode that extension on piece is arranged in.Existing LED epitaxial wafer includes substrate, buffer layer, N Type semiconductor layer, active layer and p type semiconductor layer, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer stack gradually On substrate.Substrate is for providing the surface of epitaxial growth, and buffer layer for providing the nuclearing centre of epitaxial growth, partly lead by N-type Body layer is for providing the electronics of recombination luminescence, and p type semiconductor layer is for providing the hole of recombination luminescence, and active layer is for carrying out electricity The recombination luminescence of son and hole.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The material of n type semiconductor layer uses the gallium nitride of heavily-doped Si.Silicon substituted by gallium forms covalent bond i.e. with nitrogen and may result from By mobile electronics, thus in the quantity of electronics and n type semiconductor layer silicon doping concentration it is proportional.Silicon in n type semiconductor layer Doping concentration it is very high, greater number of electronics can be provided.But since the rate travel of electronics is very fast, when N-type half Conductor layer inject active layer electron amount it is excessive when, part electrons cross active layer reach p type semiconductor layer in hole Non-radiative recombination is carried out, the hole in p type semiconductor layer is consumed, the number of cavities of p type semiconductor layer injection active layer is caused to subtract It is few, reduce the luminous efficiency of LED.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slice and its growing methods, are able to solve the prior art LED luminous efficiency need the problem of being improved.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets Include substrate, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer, it is the buffer layer, the n type semiconductor layer, described Active layer and the p type semiconductor layer stack gradually over the substrate;The n type semiconductor layer include stack gradually it is multiple Laminated construction, the laminated construction include the first sublayer, the second sublayer and third sublayer stacked gradually;First sublayer The material of material, the material of second sublayer and the third sublayer is all made of the gallium nitride of doped silicon, the multiple lamination It is the doping concentration of silicon in first sublayer of structure, the doping concentration of silicon in the second sublayer of the multiple laminated construction, described more The doping concentration of silicon is successively reduced along the stacking direction of the multiple laminated construction in the third sublayer of a laminated construction;It is same In a laminated construction, the doping concentration of silicon is greater than the doping concentration of silicon in the third sublayer, institute in first sublayer The doping concentration for stating silicon in third sublayer is greater than the doping concentration of silicon in second sublayer.
Optionally, in the same laminated construction, the doping concentration of silicon is the third sublayer in first sublayer 1.5 times of the doping concentration of middle silicon~2.5 times, the doping concentration of silicon is that silicon is mixed in second sublayer in the third sublayer 5 times of miscellaneous concentration~10 times.
Optionally, the reduction ratio of the doping concentration of silicon in the first sublayer of the multiple laminated construction, the multiple folded The reduction ratio of doping concentration of silicon in second sublayer of layer structure, in the third sublayer of the multiple laminated construction silicon doping The reduction of concentration is in equal proportions.
Further, in two neighboring first sublayer, the doping concentration of silicon is in first sublayer that is first laminated 1.5 times~5 times of the doping concentration of silicon in first sublayer being laminated afterwards.
Optionally, the thickness of the first sublayer of the multiple laminated construction, the second sublayer of the multiple laminated construction The thickness of the third sublayer of thickness, the multiple laminated construction is successively reduced along the stacking direction of the multiple laminated construction.
Further, the reduction ratio of the thickness of the first sublayer of the multiple laminated construction, the multiple laminated construction The reduction of thickness of the reduction ratio of thickness of the second sublayer, the third sublayer of the multiple laminated construction be in equal proportions.
Further, in two neighboring first sublayer, first sublayer that is first laminated with a thickness of rear stacking 1.5 times~6 times of thickness of first sublayer.
Optionally, in the same laminated construction, the thickness of second sublayer is less than the thickness of first sublayer, The thickness of the third sublayer is equal to the thickness of first sublayer.
Further, in the same laminated construction, the thickness with a thickness of second sublayer of first sublayer 1.5 times~8 times.
On the other hand, the embodiment of the invention provides a kind of growing method of LED epitaxial slice, the growth sides Method includes:
One substrate is provided;
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate;
Wherein, the n type semiconductor layer includes the multiple laminated construction stacked gradually, and the laminated construction includes successively layer Folded the first sublayer, the second sublayer and third sublayer;The material of first sublayer, the material of second sublayer and described The material of three sublayers is all made of the gallium nitride of doped silicon, the doping concentration of silicon, institute in the first sublayer of the multiple laminated construction State that the doping concentration of silicon in the second sublayer of multiple laminated construction, the doping of silicon is dense in the third sublayer of the multiple laminated construction Degree is successively reduced along the stacking direction of the multiple laminated construction;In the same laminated construction, in first sublayer The doping concentration of silicon is greater than the doping concentration of silicon in the third sublayer, and the doping concentration of silicon is greater than described in the third sublayer The doping concentration of silicon in second sublayer.
Technical solution provided in an embodiment of the present invention has the benefit that
By the way that n type semiconductor layer is divided into multiple laminated construction, each laminated construction includes three doping concentration differences Gallium nitride layer, change n type semiconductor layer in continue highly doped silicon situation, it is complete to lattice on the one hand can to reduce highly doped silicon The destruction of whole property;On the other hand in the case where providing enough electronics for active layer, the electron amount of injection active layer is reduced simultaneously The migration rate for reducing electronics avoids part electron transition from carrying out non-radiative recombination with hole into p type semiconductor layer, improves The luminous efficiency of LED.
And in intermediate gallium nitride layer silicon doping concentration it is minimum so that the doping concentration of silicon is in recessed in laminated construction On the one hand shape can effectively change the situation of the gallium nitride layer growth for a long time of highly doped silicon, be equivalent to the nitrogen of highly doped silicon The growth time for changing gallium layer scatter, and is conducive to promote perfection of lattice, reduces stress and defect extension that highly doped silicon generates The recombination luminescence of electrons and holes is influenced to active layer;On the other hand it can promote current expansion.Simultaneously for low-doped The gallium nitride layer of the highly doped silicon of the gallium nitride layer two sides of silicon, far from active layer gallium nitride layer in silicon doping concentration be greater than lean on The doping concentration of silicon in the gallium nitride layer of nearly active layer, so that quantity of the electronics in laminated construction far from active layer region is greater than Quantity close to active layer region, quantitative difference are conducive to electronics and move towards the direction close to active layer.
In addition, the doping concentration of silicon is successively reduced along the stacking direction of multiple laminated construction in multiple laminated construction, a side Face is greater than the doping concentration of the silicon in the laminated construction of active layer far from the doping concentration of silicon in the laminated construction of active layer, makes It obtains electronics and is greater than the quantity close to active layer region in the quantity far from active layer region, quantitative difference is conducive to electronics court It is moved close to the direction of active layer;On the other hand the doping concentration of silicon is lower in the laminated construction of active layer, with active layer Lattice comparison match, electric current it is extending transversely also preferably, moreover it is possible to further avoid part electron transition into p type semiconductor layer Non-radiative recombination is carried out with hole, improves the luminous efficiency of LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention;
Fig. 2 is the structural schematic diagram of n type semiconductor layer provided in an embodiment of the present invention;
Fig. 3 is a kind of flow chart of the growing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slices.Fig. 1 is a kind of hair provided in an embodiment of the present invention The structural schematic diagram of optical diode epitaxial wafer.Referring to Fig. 1, which includes substrate 1, buffer layer 2, N-type half Conductor layer 3, active layer 4 and p type semiconductor layer 5, buffer layer 2, n type semiconductor layer 3, active layer 4 and p type semiconductor layer 5 are successively It is layered on substrate 1.
Fig. 2 is the structural schematic diagram of n type semiconductor layer provided in an embodiment of the present invention.Referring to fig. 2, n type semiconductor layer 3 wraps Include the multiple laminated construction 30 stacked gradually, laminated construction 30 includes the first sublayer 31 stacked gradually, the second sublayer 32 and the Three sublayers 33.The material of the material of first sublayer 31, the material of the second sublayer 32 and third sublayer 33 is all made of the nitrogen of doped silicon Change gallium, the doping concentration of silicon in the first sublayer 31 of multiple laminated construction 30, silicon in the second sublayer 32 of multiple laminated construction 30 Doping concentration, in the third sublayer 33 of multiple laminated construction 30 silicon doping concentration along the stacking side of multiple laminated construction 30 It is reduced to layer-by-layer;The doping concentration of silicon is along the stacking side of multiple laminated construction 30 in first sublayer 31 of i.e. multiple laminated construction 30 It is reduced to layer-by-layer, stacking direction of the doping concentration of silicon along multiple laminated construction 30 in the second sublayer 32 of multiple laminated construction 30 Successively reduce, in the third sublayer 33 of multiple laminated construction 30 doping concentration of silicon along multiple laminated construction 30 stacking direction by Layer reduces.In the same laminated construction, the doping concentration of silicon is greater than the doping concentration of silicon in third sublayer 33 in the first sublayer 31, The doping concentration of silicon is greater than the doping concentration of silicon in the second sublayer 32 in third sublayer 33.
For the embodiment of the present invention by the way that n type semiconductor layer is divided into multiple laminated construction, each laminated construction includes three silicon The different gallium nitride layer of doping concentration changes the situation for continuing highly doped silicon in n type semiconductor layer, on the one hand can reduce highly doped Destruction of the miscellaneous silicon to perfection of lattice;On the other hand in the case where providing enough electronics for active layer, injection active layer is reduced Electron amount and reduce the migration rate of electronics, avoid part electron transition from carrying out non-spoke with hole into p type semiconductor layer It penetrates compound, improves the luminous efficiency of LED.
And in intermediate gallium nitride layer silicon doping concentration it is minimum so that the doping concentration of silicon is in recessed in laminated construction On the one hand shape can effectively change the situation of the gallium nitride layer growth for a long time of highly doped silicon, be equivalent to the nitrogen of highly doped silicon The growth time for changing gallium layer scatter, and is conducive to promote perfection of lattice, reduces stress and defect extension that highly doped silicon generates The recombination luminescence of electrons and holes is influenced to active layer;On the other hand it can promote current expansion.Simultaneously for low-doped The gallium nitride layer of the highly doped silicon of the gallium nitride layer two sides of silicon, far from active layer gallium nitride layer in silicon doping concentration be greater than lean on The doping concentration of silicon in the gallium nitride layer of nearly active layer, so that quantity of the electronics in laminated construction far from active layer region is greater than Quantity close to active layer region, quantitative difference are conducive to electronics and move towards the direction close to active layer.
In addition, the doping concentration of silicon is successively reduced along the stacking direction of multiple laminated construction in multiple laminated construction, a side Face is greater than the doping concentration of the silicon in the laminated construction of active layer far from the doping concentration of silicon in the laminated construction of active layer, makes It obtains electronics and is greater than the quantity close to active layer region in the quantity far from active layer region, quantitative difference is conducive to electronics court It is moved close to the direction of active layer;On the other hand the doping concentration of silicon is lower in the laminated construction of active layer, with active layer Lattice comparison match, electric current it is extending transversely also preferably, moreover it is possible to further avoid part electron transition into p type semiconductor layer Non-radiative recombination is carried out with hole, improves the luminous efficiency of LED.
Optionally, in the same laminated construction 30, the doping concentration of silicon can be in third sublayer 33 in the first sublayer 31 1.5 times of the doping concentration of silicon~2.5 times, such as 2 times;The doping concentration of silicon can be silicon in the second sublayer 32 in third sublayer 33 5 times~10 times of doping concentration, such as 6 times~10 times.Doping of the doping concentration of silicon than silicon in third sublayer in first sublayer Concentration is slightly higher, while the doping concentration of silicon is much higher than the doping concentration of silicon in the second sublayer in third sublayer, so that laminated construction The doping concentration of middle silicon is concave, can effectively facilitate the extending transversely of electric current;Simultaneously two sides sublayer in silicon doping concentration Slightly difference can use quantitative difference and promote electronics towards close to active so that the electron amount of two sides is also slightly different The direction movement of layer.
Optionally, the reduction ratio of the doping concentration of silicon, multiple lamination knots in the first sublayer 31 of multiple laminated construction 30 In second sublayer 32 of structure 30 in the reduction ratio of doping concentration, the third sublayer 33 of multiple laminated construction 30 of silicon silicon doping The reduction ratio of concentration can be equal.The doping concentration of silicon in each sublayer, the same lamination knot are reduced using identical ratio The comparison in difference of doping concentration is constant between each sublayer in structure, is conducive to the stabilization of crystal structure.
Further, in two neighboring first sublayer 31, the doping concentration of silicon can be in the first sublayer 31 for being first laminated 1.5 times~5 times of the doping concentration of silicon in the first sublayer 31 being laminated afterwards, such as 1.5 times~4 times.If the first son being first laminated 1.5 times of the doping concentration of silicon in the first sublayer that the doping concentration of silicon is laminated after being less than in layer, then may be due to the first sublayer The doping concentration variation of middle silicon is smaller and part electron transition can not effectively be avoided to carry out non-spoke with hole into p type semiconductor layer Penetrate compound, the final luminous efficiency for influencing LED;If the doping concentration of silicon is laminated after being greater than in the first sublayer being first laminated 5 times of the doping concentration of silicon in one sublayer may then be changed greatly due to the doping concentration of silicon in the first sublayer and lead to crystal It is second-rate, eventually affect the luminous efficiency of LED.
Correspondingly, in two neighboring second sublayer 32, after the doping concentration of silicon can be in the second sublayer 32 for being first laminated 1.5 times~5 times of the doping concentration of silicon in second sublayer 32 of stacking, such as 1.5 times~4 times;In two neighboring third sublayer 33, 1.5 times of the doping concentration of silicon in the third sublayer 33 that the doping concentration of silicon is laminated after being in the third sublayer 33 being first laminated ~5 times, such as 1.5 times~4 times.
Illustratively, the doping concentration of silicon can be 5*10 in the first sublayer 3118/cm3~5*1019/cm3, such as 5*1018/ cm3~3*1019/cm3;The doping concentration of silicon can be 5*10 in second sublayer 3217/cm3~2.5*1018/cm3, such as 6*1017/ cm3~2.5*1018/cm3;The doping concentration of silicon can be 2.5*10 in third sublayer 3318/cm3~2.5*1019/cm3, such as 2.5*1018/cm3~1*1019/cm3, realize that effect is good.
Optionally, the thickness of the first sublayer 31 of multiple laminated construction 30, the second sublayer 32 of multiple laminated construction 30 The thickness of the third sublayer 33 of thickness, multiple laminated construction 30 can the stacking direction along multiple laminated construction 30 successively drop It is low;The thickness of first sublayer 31 of i.e. multiple laminated construction 30 is successively reduced along the stacking direction of multiple laminated construction 30, multiple The thickness of second sublayer 32 of laminated construction 30 is successively reduced along the stacking direction of multiple laminated construction 30, multiple laminated construction 30 The thickness of third sublayer 33 successively reduced along the stacking direction of multiple laminated construction 30.The thickness of each sublayer and each sublayer The doping concentration of middle silicon is synchronous to be reduced, and the two cooperates, and the doping concentration of silicon is higher in the laminated construction far from active layer, together The biggish thickness of Shi Caiyong can provide sufficient amount of electronics for active layer;Silicon mixes in the laminated construction of active layer Miscellaneous concentration is lower, while using lesser thickness, is conducive to electron injection active layer.
Further, the reduction ratio of the thickness of the first sublayer 31 of multiple laminated construction 30, multiple laminated construction 30 Reduction ratio, the reduction ratio of the thickness of the third sublayer 33 of multiple laminated construction 30 of the thickness of second sublayer 32 can phases Deng.The thickness of each sublayer is reduced using identical ratio, in the same laminated construction between each sublayer thickness diversity ratio It is more constant, be conducive to the stabilization of crystal structure.
Further, in two neighboring first sublayer 31, the first sublayer 31 for being first laminated with a thickness of the of rear stacking 1.5 times of the thickness of one sublayer 31~6 times, such as 1.5 times~4 times.If the thickness for the first sublayer being first laminated is laminated after being less than 1.5 times of thickness of the first sublayer, then may can not be matched in the first sublayer since the thickness change of the first sublayer is smaller The variation of doping concentration causes the electron amount injected in active layer too little or too much;If the first sublayer being first laminated 6 times of the thickness for the first sublayer that thickness is laminated after being greater than then may lead to crystalline substance since the thickness change of the first sublayer is too big Weight is poor, eventually affects the luminous efficiency of LED.
Correspondingly, in two neighboring second sublayer 32, the second son with a thickness of rear stacking for the second sublayer 32 being first laminated 1.5 times~6 times of the thickness of layer 32, such as 1.5 times~4 times;In two neighboring third sublayer 33, the third sublayer 33 that is first laminated With a thickness of 1.5 times~6 times of the thickness of the third sublayer 33 of rear stacking, such as 1.5 times~4 times.
Optionally, in the same laminated construction 30, the thickness of the second sublayer 32 can less than the thickness of the first sublayer 31, The thickness of three sublayers 33 can be equal to the thickness of the first sublayer 31, avoid the second sublayer too thick and cause n type semiconductor layer whole Doping concentration it is lower, and then influence current expansion.
Further, in the same laminated construction 30, the thickness of the first sublayer 31 can be the thickness of the second sublayer 32 1.5 times~8 times, such as 3 times~8 times.If the thickness of the first sublayer, may be due to less than 1.5 times of thickness of the second sublayer Second sublayer is too thick and causes the doping concentration of n type semiconductor layer entirety lower, and then influences current expansion;If first The thickness of sublayer is greater than 8 times of the thickness of the second sublayer, then may can not effectively play protection crystalline substance since the second sublayer is too thin The effect of lattice integrality.
Illustratively, the thickness of the first sublayer 31 can be 100nm~500nm, such as 100nm~400nm;Second sublayer 32 Thickness can be 40nm~100nm, such as 40nm~80nm;The thickness of third sublayer 33 can be 100nm~500nm, such as 100nm~400nm realizes that effect is good.
Optionally, the quantity of laminated construction 30 can be 5~20, such as 6~15.If the quantity of laminated construction Less than 5, then may due to laminated construction negligible amounts and can not effectively adjust injection active layer electron amount;If folded The quantity of layer structure is more than 20, then may be more due to the quantity of laminated construction and cause that growth technique is complicated, growth cost It is higher, or even influence electron injection active layer.
Optionally, the material of substrate 1 can use sapphire (main material is aluminum oxide), if crystal orientation is [0001] Sapphire.The material of buffer layer 2 can use undoped gallium nitride or aluminium nitride.Active layer 4 may include multiple amounts Sub- trap and multiple quantum are built, and multiple Quantum Well and multiple quantum build alternately laminated setting;The material of Quantum Well can be using nitridation Indium gallium (InGaN), such as InxGa1-xN, 0 < x < 1, the material that quantum is built can use gallium nitride.The material of p type semiconductor layer 5 It can be using the gallium nitride of p-type doping (such as magnesium).
Further, the thickness of buffer layer 2 can be 15nm~30nm, preferably 25nm.The thickness of Quantum Well can be 2nm~3nm, preferably 2.5nm;The thickness that quantum is built can be 8nm~11nm, preferably 9.5nm;The quantity and amount of Quantum Well The quantity that son is built is identical, and the quantity that quantum is built can be 11~13, preferably 12;The thickness of active layer 4 can be 130nm~160nm, preferably 145nm.The thickness of p type semiconductor layer 5 can be 50nm~80nm, preferably 65nm;P-type half The doping concentration of P-type dopant can be 10 in conductor layer 518/cm3~1020/cm3, preferably 1019/cm3
Optionally, as shown in Figure 1, the LED epitaxial slice can also include undoped gallium nitride layer 6, undoped with nitrogen Change gallium layer 6 to be arranged between buffer layer 2 and n type semiconductor layer 3, be generated with alleviating lattice mismatch between substrate material and gallium nitride Stress and defect, provide crystal quality preferable growing surface for epitaxial wafer main structure.
In specific implementation, buffer layer 2 is the gallium nitride of the layer of low-temperature epitaxy first in patterned substrate, because This is also referred to as low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again, will form multiple mutually independent three Island structure is tieed up, referred to as three-dimensional nucleating layer;Then it is carried out between each three-dimensional island structure on all three-dimensional island structures The cross growth of gallium nitride forms two-dimension plane structure, referred to as two-dimentional retrieving layer;The finally high growth temperature one on two-dimensional growth layer The thicker gallium nitride of layer, referred to as intrinsic gallium nitride layer.By three-dimensional nucleating layer, two-dimentional retrieving layer and intrinsic gallium nitride in the present embodiment Layer is referred to as undoped gallium nitride layer 6.
Further, the thickness of undoped gallium nitride layer 6 can be 2 μm~3.5 μm, preferably 2.75 μm.
Optionally, which can also include stress release layer 7, and the setting of stress release layer 7 is in N-type half Between conductor layer 3 and active layer 4, discharged with the stress generated to lattice mismatch between sapphire and gallium nitride, raising has The crystal quality of active layer is conducive to electrons and holes and shines in active layer progress radiation recombination, improves the internal quantum efficiency of LED, And then improve the luminous efficiency of LED.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include electronic barrier layer 81, electronic barrier layer 81 are arranged between active layer 4 and p type semiconductor layer 5, carry out non-spoke with hole into p type semiconductor layer to avoid electron transition It penetrates compound, reduces the luminous efficiency of LED.
Specifically, the material of electronic barrier layer 81 can be using the aluminium gallium nitride alloy (AlGaN) of p-type doping, such as AlyGa1-yN, 0.15 < y < 0.25.
Further, the thickness of electronic barrier layer 81 can be 30nm~50nm, preferably 40nm.
Preferably, as shown in Figure 1, the LED epitaxial slice can also include low temperature P-type layer 82, low temperature P-type layer 82 It is arranged between active layer 4 and electronic barrier layer 81, is caused in active layer to avoid the higher growth temperature of electronic barrier layer Phosphide atom is precipitated, and influences the luminous efficiency of light emitting diode.
Specifically, the material of low temperature P-type layer 82 can be the gallium nitride of p-type doping.
Further, the thickness of low temperature P-type layer 82 can be 10nm~50nm, preferably 30nm;P in low temperature P-type layer 82 The doping concentration of type dopant can be 1018/cm3~1020/cm3, preferably 1019/cm3
Optionally, as shown in Figure 1, the LED epitaxial slice can also include contact layer 9, contact layer 9 is arranged in p-type On semiconductor layer 5, to form Ohmic contact between the electrode or transparent conductive film that are formed in chip fabrication technique.
Specifically, the material of contact layer 9 can be using the InGaN or gallium nitride of p-type doping.
Further, the thickness of contact layer 9 can be 5nm~300nm, preferably 100nm;P-type dopant in contact layer 9 Doping concentration can be 1021/cm3~1022/cm3, preferably 5*1021/cm3
The embodiment of the invention provides a kind of growing method of LED epitaxial slice, it is suitable for growing shown in FIG. 1 LED epitaxial slice.Fig. 3 is a kind of process of the growing method of LED epitaxial slice provided in an embodiment of the present invention Figure.Referring to Fig. 3, which includes:
Step 201: a substrate is provided.
Optionally, which may include:
Controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure be 200torr~500torr (preferably 350torr), 5 minutes~6 minutes (preferably 5.5 minutes) annealings are carried out to substrate in hydrogen atmosphere.
The surface for cleaning substrate through the above steps avoids being conducive to the life for improving epitaxial wafer in impurity incorporation epitaxial wafer Long quality.
Step 202: successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer on substrate.
In the present embodiment, n type semiconductor layer includes the multiple laminated construction stacked gradually, and laminated construction includes successively layer Folded the first sublayer, the second sublayer and third sublayer.The material of the material of first sublayer, the material of the second sublayer and third sublayer It is all made of the gallium nitride of doped silicon, the second of the doping concentration of silicon in the first sublayer of multiple laminated construction, multiple laminated construction The doping concentration of silicon in sublayer, in the third sublayer of multiple laminated construction silicon doping concentration along the stacking of multiple laminated construction Direction successively reduces.In the same laminated construction, the doping concentration of silicon is dense greater than the doping of silicon in third sublayer in the first sublayer It spends, the doping concentration of silicon is greater than the doping concentration of silicon in the second sublayer in third sublayer.
Optionally, in the same laminated construction, the growth conditions of the first sublayer, the growth conditions of the second sublayer, third The growth conditions of layer can be identical.Further, the growth conditions of each laminated construction can also be identical, is realized with facilitating.Its In, growth conditions may include growth temperature and growth pressure.
Optionally, which may include:
The first step, controlled at 530 DEG C~560 DEG C (preferably 545 DEG C), pressure is that 200torr~500torr is (excellent It is selected as 350torr), grown buffer layer on substrate;
Second step, controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure is 200torr~300torr (preferably 250torr), grows n type semiconductor layer on the buffer layer;
Third step grows active layer on n type semiconductor layer;Wherein, the growth temperature of Quantum Well is 760 DEG C~780 DEG C (preferably 770 DEG C), pressure 200torr;The growth temperature that quantum is built is 860 DEG C~890 DEG C (preferably 875 DEG C), pressure For 200torr;
4th step, controlled at 940 DEG C~980 DEG C (preferably 960 DEG C), pressure is that 200torr~600torr is (excellent It is selected as 400torr), the growing P-type semiconductor layer on active layer.
Optionally, before second step, which can also include:
Undoped gallium nitride layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on undoped gallium nitride layer.
Specifically, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure be 200torr~600torr (preferably 400torr), undoped gallium nitride layer is grown on the buffer layer.
Optionally, before third step, which can also include:
The growth stress releasing layer on n type semiconductor layer.
Correspondingly, active layer is grown on stress release layer.
Optionally, before the 4th step, which can also include:
Electronic barrier layer is grown on active layer.
Correspondingly, p type semiconductor layer is grown on electronic barrier layer.
Specifically, electronic barrier layer is grown on active layer, may include:
Controlled at 930 DEG C~970 DEG C (preferably 950 DEG C), pressure 100torr grows electronics on active layer Barrier layer.
Preferably, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer.
Correspondingly, electronic barrier layer is grown in low temperature P-type layer.
Specifically, the growing low temperature P-type layer on active layer may include:
Controlled at 600 DEG C~850 DEG C (preferably 750 DEG C), pressure be 100torr~600torr (preferably 300torr), the growing low temperature P-type layer on active layer.
Optionally, after the 4th step, which can also include:
Contact layer is grown on p type semiconductor layer.
Specifically, contact layer is grown on p type semiconductor layer, may include:
Controlled at 850 DEG C~1050 DEG C (preferably 950 DEG C), pressure be 100torr~300torr (preferably 200torr), contact layer is grown on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 650 DEG C~850 DEG C (preferably It is 750 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again The temperature of epitaxial wafer is reduced to room temperature.
Control temperature, pressure each mean temperature, pressure in the reaction chamber of control growth epitaxial wafer, and specially metal is organic Compound chemical gaseous phase deposition (English: Metal-organic Chemical Vapor Deposition, referred to as: MOCVD) set Standby reaction chamber, such as Veeco K465i MOCVD or Veeco C4 MOCVD.With hydrogen or nitrogen or hydrogen when realization The mixed gas of gas and nitrogen is as carrier gas, trimethyl gallium or triethyl-gallium as gallium source, and high-purity ammonia is as nitrogen source, trimethyl Indium is as indium source, and trimethyl aluminium is as silicon source, and silane is as silicon source, and two luxuriant magnesium are as magnesium source.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, buffer layer, n type semiconductor layer, has Active layer and p type semiconductor layer, the buffer layer, the n type semiconductor layer, the active layer and the p type semiconductor layer are successively Stacking is over the substrate;It is characterized in that, the n type semiconductor layer includes the multiple laminated construction stacked gradually, it is described folded Layer structure includes the first sublayer, the second sublayer and third sublayer stacked gradually;The material of first sublayer, second son The material of layer and the material of the third sublayer are all made of the gallium nitride of doped silicon, in the first sublayer of the multiple laminated construction The doping concentration, the third of the multiple laminated construction of silicon in the doping concentration of silicon, the second sublayer of the multiple laminated construction The doping concentration of silicon is successively reduced along the stacking direction of the multiple laminated construction in sublayer;The same laminated construction In, the doping concentration of silicon is greater than the doping concentration of silicon in the third sublayer, silicon in the third sublayer in first sublayer Doping concentration be greater than second sublayer in silicon doping concentration.
2. LED epitaxial slice according to claim 1, which is characterized in that in the same laminated construction, institute The doping concentration for stating silicon in the first sublayer is 1.5 times~2.5 times of the doping concentration of silicon in the third sublayer, third The doping concentration of silicon is 5 times~10 times of the doping concentration of silicon in second sublayer in layer.
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that the of the multiple laminated construction The reduction ratio of the doping concentration of silicon in one sublayer, in the second sublayer of the multiple laminated construction the doping concentration of silicon reduction The reduction of the doping concentration of silicon is in equal proportions in ratio, the third sublayer of the multiple laminated construction.
4. LED epitaxial slice according to claim 3, which is characterized in that in two neighboring first sublayer, 1.5 times of the doping concentration of silicon in first sublayer that the doping concentration of silicon is laminated after being in first sublayer being first laminated ~5 times.
5. LED epitaxial slice according to claim 1 or 2, which is characterized in that the of the multiple laminated construction The thickness of the third sublayer of the thickness of one sublayer, the thickness of the second sublayer of the multiple laminated construction, the multiple laminated construction Degree is successively reduced along the stacking direction of the multiple laminated construction.
6. LED epitaxial slice according to claim 5, which is characterized in that the first son of the multiple laminated construction Reduction ratio, the reduction ratio of the thickness of the second sublayer of the multiple laminated construction, the multiple lamination knot of the thickness of layer The reduction of the thickness of the third sublayer of structure is in equal proportions.
7. LED epitaxial slice according to claim 6, which is characterized in that in two neighboring first sublayer, 1.5 times~6 times of the thickness of first sublayer with a thickness of rear stacking for first sublayer being first laminated.
8. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the same laminated construction, The thickness of second sublayer is less than the thickness of first sublayer, and the thickness of the third sublayer is equal to first sublayer Thickness.
9. LED epitaxial slice according to claim 8, which is characterized in that in the same laminated construction, institute 1.5 times~8 times for stating the thickness with a thickness of second sublayer of the first sublayer.
10. a kind of growing method of LED epitaxial slice, which is characterized in that the growing method includes:
One substrate is provided;
Successively grown buffer layer, n type semiconductor layer, active layer and p type semiconductor layer over the substrate;
Wherein, the n type semiconductor layer includes the multiple laminated construction stacked gradually, and the laminated construction includes stacking gradually First sublayer, the second sublayer and third sublayer;The material of first sublayer, the material of second sublayer and third The material of layer is all made of the gallium nitride of doped silicon, the doping concentration of silicon in the first sublayer of the multiple laminated construction, described more The doping concentration of silicon in second sublayer of a laminated construction, the doping concentration of silicon is equal in the third sublayer of the multiple laminated construction Stacking direction along the multiple laminated construction successively reduces;In the same laminated construction, silicon in first sublayer Doping concentration is greater than the doping concentration of silicon in the third sublayer, and the doping concentration of silicon is greater than described second in the third sublayer The doping concentration of silicon in sublayer.
CN201910097795.5A 2019-01-31 2019-01-31 Light emitting diode epitaxial wafer and growth method thereof Active CN109950375B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910097795.5A CN109950375B (en) 2019-01-31 2019-01-31 Light emitting diode epitaxial wafer and growth method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910097795.5A CN109950375B (en) 2019-01-31 2019-01-31 Light emitting diode epitaxial wafer and growth method thereof

Publications (2)

Publication Number Publication Date
CN109950375A true CN109950375A (en) 2019-06-28
CN109950375B CN109950375B (en) 2021-04-02

Family

ID=67006728

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910097795.5A Active CN109950375B (en) 2019-01-31 2019-01-31 Light emitting diode epitaxial wafer and growth method thereof

Country Status (1)

Country Link
CN (1) CN109950375B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990990A (en) * 2021-09-01 2022-01-28 华灿光电(浙江)有限公司 Micro light-emitting diode epitaxial wafer and manufacturing method thereof
CN114695608A (en) * 2022-05-31 2022-07-01 江西兆驰半导体有限公司 LED epitaxial wafer, chip and preparation method thereof

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157648A (en) * 2010-02-12 2011-08-17 株式会社东芝 Semiconductor light emitting device
US20110263128A1 (en) * 2010-04-22 2011-10-27 Luminus Devices, Inc. Selective wet etching and textured surface planarization processes
CN102851734A (en) * 2012-09-06 2013-01-02 程凯 Semiconductor epitaxy structure and growth method thereof
CN103531680A (en) * 2013-10-23 2014-01-22 苏州矩阵光电有限公司 LED epitaxy structure and preparation method thereof
CN103682001A (en) * 2012-09-26 2014-03-26 丰田合成株式会社 Group iii nitride semiconductor light-emitting device
CN104091871A (en) * 2014-06-17 2014-10-08 华灿光电(苏州)有限公司 Light-emitting diode epitaxial slice and manufacturing method thereof
CN104112798A (en) * 2014-07-31 2014-10-22 圆融光电科技有限公司 Light-emitting diode manufacturing method and light-emitting diode
CN105206723A (en) * 2015-11-03 2015-12-30 湘能华磊光电股份有限公司 Epitaxial growth method for improving LED brightness
US20160276529A1 (en) * 2015-03-20 2016-09-22 Enraytek Optoelectronics Co., Ltd. Gan-based led epitaxial structure and preparation method thereof
CN106057988A (en) * 2016-06-22 2016-10-26 华灿光电(苏州)有限公司 Preparation method for epitaxial wafer of GaN-based light emitting diode
CN106252480A (en) * 2016-08-05 2016-12-21 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and growing method thereof
CN106328777A (en) * 2016-09-08 2017-01-11 湘能华磊光电股份有限公司 Light emitting diode stress release layer epitaxial growth method
CN107394018A (en) * 2017-08-10 2017-11-24 湘能华磊光电股份有限公司 A kind of LED epitaxial growth methods
CN107919416A (en) * 2016-08-25 2018-04-17 映瑞光电科技(上海)有限公司 A kind of GaN base light emitting epitaxial structure and preparation method thereof
CN108565319A (en) * 2013-01-25 2018-09-21 新世纪光电股份有限公司 Nitride semiconductor structure and semiconductor light-emitting elements
CN108598235A (en) * 2018-05-09 2018-09-28 芜湖德豪润达光电科技有限公司 Gan base led structure and preparation method thereof
US20180331259A1 (en) * 2001-10-26 2018-11-15 Lg Innotek Co., Ltd. Diode having vertical structure
CN108878603A (en) * 2018-07-03 2018-11-23 贵州杰芯光电科技有限公司 A kind of epitaxial preparation method of gallium nitride based LED
CN108878606A (en) * 2018-06-22 2018-11-23 西安电子科技大学 Based on superlattice structure and the δ efficient LED adulterated and preparation method
CN108987544A (en) * 2018-05-31 2018-12-11 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN108987543A (en) * 2017-06-01 2018-12-11 英属开曼群岛商镎创科技股份有限公司 Light-emitting component

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180331259A1 (en) * 2001-10-26 2018-11-15 Lg Innotek Co., Ltd. Diode having vertical structure
CN102157648A (en) * 2010-02-12 2011-08-17 株式会社东芝 Semiconductor light emitting device
US20110263128A1 (en) * 2010-04-22 2011-10-27 Luminus Devices, Inc. Selective wet etching and textured surface planarization processes
CN102851734A (en) * 2012-09-06 2013-01-02 程凯 Semiconductor epitaxy structure and growth method thereof
CN103682001A (en) * 2012-09-26 2014-03-26 丰田合成株式会社 Group iii nitride semiconductor light-emitting device
CN108565319A (en) * 2013-01-25 2018-09-21 新世纪光电股份有限公司 Nitride semiconductor structure and semiconductor light-emitting elements
CN103531680A (en) * 2013-10-23 2014-01-22 苏州矩阵光电有限公司 LED epitaxy structure and preparation method thereof
CN104091871A (en) * 2014-06-17 2014-10-08 华灿光电(苏州)有限公司 Light-emitting diode epitaxial slice and manufacturing method thereof
CN104112798A (en) * 2014-07-31 2014-10-22 圆融光电科技有限公司 Light-emitting diode manufacturing method and light-emitting diode
US20160276529A1 (en) * 2015-03-20 2016-09-22 Enraytek Optoelectronics Co., Ltd. Gan-based led epitaxial structure and preparation method thereof
CN105206723A (en) * 2015-11-03 2015-12-30 湘能华磊光电股份有限公司 Epitaxial growth method for improving LED brightness
CN106057988A (en) * 2016-06-22 2016-10-26 华灿光电(苏州)有限公司 Preparation method for epitaxial wafer of GaN-based light emitting diode
CN106252480A (en) * 2016-08-05 2016-12-21 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and growing method thereof
CN107919416A (en) * 2016-08-25 2018-04-17 映瑞光电科技(上海)有限公司 A kind of GaN base light emitting epitaxial structure and preparation method thereof
CN106328777A (en) * 2016-09-08 2017-01-11 湘能华磊光电股份有限公司 Light emitting diode stress release layer epitaxial growth method
CN108987543A (en) * 2017-06-01 2018-12-11 英属开曼群岛商镎创科技股份有限公司 Light-emitting component
CN107394018A (en) * 2017-08-10 2017-11-24 湘能华磊光电股份有限公司 A kind of LED epitaxial growth methods
CN108598235A (en) * 2018-05-09 2018-09-28 芜湖德豪润达光电科技有限公司 Gan base led structure and preparation method thereof
CN108987544A (en) * 2018-05-31 2018-12-11 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN108878606A (en) * 2018-06-22 2018-11-23 西安电子科技大学 Based on superlattice structure and the δ efficient LED adulterated and preparation method
CN108878603A (en) * 2018-07-03 2018-11-23 贵州杰芯光电科技有限公司 A kind of epitaxial preparation method of gallium nitride based LED

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
周之琰: ""硅衬底生长的InGaN/GaN多层量子阱中δ型硅掺杂n-GaN层对载流子复合过程的调节作用"", 《发光学报》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990990A (en) * 2021-09-01 2022-01-28 华灿光电(浙江)有限公司 Micro light-emitting diode epitaxial wafer and manufacturing method thereof
CN113990990B (en) * 2021-09-01 2023-05-09 华灿光电(浙江)有限公司 Micro light-emitting diode epitaxial wafer and manufacturing method thereof
CN114695608A (en) * 2022-05-31 2022-07-01 江西兆驰半导体有限公司 LED epitaxial wafer, chip and preparation method thereof

Also Published As

Publication number Publication date
CN109950375B (en) 2021-04-02

Similar Documents

Publication Publication Date Title
CN108550675B (en) A kind of LED epitaxial slice and preparation method thereof
CN109786529A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN110311022A (en) GaN base light emitting epitaxial wafer and its manufacturing method
CN107293619B (en) A kind of LED epitaxial slice and its manufacturing method
CN110112269A (en) LED epitaxial slice and preparation method thereof
CN109860358A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109192831A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109860359A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109346576A (en) A kind of LED epitaxial slice and preparation method thereof
CN109065679A (en) A kind of LED epitaxial slice and its manufacturing method
CN109346583A (en) A kind of LED epitaxial slice and preparation method thereof
CN109256445A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109065682B (en) A kind of LED epitaxial slice and its manufacturing method
CN109103312B (en) Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof
CN109950375A (en) LED epitaxial slice and its growing method
CN110364598A (en) LED epitaxial slice and preparation method thereof
CN109671817A (en) A kind of LED epitaxial slice and preparation method thereof
CN109346568A (en) A kind of LED epitaxial slice and preparation method thereof
CN109473516A (en) A kind of gallium nitride based LED epitaxial slice and its growing method
CN109920884B (en) Light emitting diode epitaxial wafer and growth method thereof
CN109830582A (en) LED epitaxial slice and its growing method
CN109087977B (en) Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof
CN109473521A (en) A kind of LED epitaxial slice and preparation method thereof
CN109686823A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109768136A (en) A kind of LED epitaxial slice and its growing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant