CN108807620B - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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CN108807620B
CN108807620B CN201810616928.0A CN201810616928A CN108807620B CN 108807620 B CN108807620 B CN 108807620B CN 201810616928 A CN201810616928 A CN 201810616928A CN 108807620 B CN108807620 B CN 108807620B
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CN108807620A (en
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刘旺平
乔楠
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, belonging to the field of light-emitting diode manufacturing. The active layer is arranged to include a first barrier layer and a plurality of InGaN well layers, a plurality of the first barrier layers including GaN/InxGa1‑xN/AlzGa1‑zN/InyGa1‑yThe first sub-barrier layers of the N/GaN superlattice structure and the InGaN well layer are alternately stacked. Due to GaN/InxGa1‑xN/AlzGa1‑ zN/InyGa1‑yThe N/GaN superlattice structure has a high energy band, and can prevent electrons from entering the P-type GaN layer, so that an electron blocking layer is not required to be arranged to prevent the electrons from flowing out of the active layer, the arrangement can limit the electrons from leaving the active layer and simultaneously improve the number of holes entering the active layer, further improve the number of holes which are in the active layer and emit light in a composite mode with the electrons, and also can reduce the polarization condition among the electron blocking layer, the active layer and the P-type layer due to the arrangement of the electron blocking layer in the epitaxial layer, further avoid the reduction of light-emitting band gaps in the epitaxial layer, increase the recombination efficiency of the electrons and the holes, and further increase the light-emitting efficiency of the light-emitting diode.

Description

Light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The invention relates to the field of light emitting diode manufacturing, in particular to a light emitting diode epitaxial wafer and a preparation method thereof.
Background
The light emitting diode is a semiconductor diode capable of converting electric energy into light energy, has the advantages of small volume, long service life, low power consumption and the like, and is widely applied to automobile signal lamps, traffic signal lamps, display screens and lighting equipment at present. The epitaxial wafer is a basic structure for manufacturing the light emitting diode, and the structure of the epitaxial wafer comprises a substrate and an epitaxial layer grown on the substrate. Wherein, the structure of epitaxial layer mainly includes: the GaN-based light-emitting diode comprises a low-temperature GaN buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an AlGaN electron blocking layer and a P-type GaN layer which are sequentially grown on a substrate.
The AlGaN electron blocking layer generally plays a role in preventing electrons in the active layer from migrating to the P-type GaN layer, so that it is ensured that as many electrons as possible are combined in the active layer, and the light emitting efficiency of the light emitting diode is further ensured. Meanwhile, the AlGaN electron blocking layer can also block holes from entering the active layer, the number of the holes entering the active layer is smaller than that of electrons entering the active layer originally, and the AlGaN electron blocking layer can limit the number of the holes entering the active layer, so that the number of the holes which are in line with electrons to emit light in the active layer is smaller, and the overall light emitting efficiency of the light emitting diode is lower.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode epitaxial wafer and a preparation method thereof, which can improve the light-emitting efficiency of a light-emitting diode. The technical scheme is as follows:
the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and a low-temperature GaN buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer and a P-type GaN layer which are sequentially stacked on the substrate,
the active layer comprises a first barrier layer and a plurality of well layers, the first barrier layer comprises a plurality of first sub-barrier layers, the first sub-barrier layers and the well layers are alternately stacked, the well layers are InGaN well layers, and the first sub-barrier layers comprise GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35。
Optionally, the ratio of x to z is 0.15:1 to 0.4: 1.
Alternatively, x > y.
Optionally, the ratio of x to y is 3:1 to 5: 1.
Optionally, the active layer further includes a second barrier layer, the second barrier layer includes two GaN barrier layers, the two GaN barrier layers are respectively disposed on two sides of the first barrier layer, and a layer is disposed between the two GaN barrier layers and the first barrier layer to form the well layer.
Optionally, the thickness of the GaN barrier layer is the same as that of the first sub-barrier layer.
Optionally, the thickness of the first sub-barrier layer is 8-20 nm.
Optionally, the number of the first sub-base layers is 3-13.
The embodiment of the invention provides a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing a low-temperature GaN buffer layer on the substrate;
growing an undoped GaN layer on the low-temperature GaN buffer layer;
growing an N-type GaN layer on the undoped GaN layer;
growing an active layer on the N-type GaN layer;
growing a P-type GaN layer on the active layer,
the active layer comprises a first barrier layer and a plurality of well layers, the first barrier layer comprises a plurality of first sub-barrier layers, the first sub-barrier layers and the well layers are alternately stacked, the well layers are InGaN well layers, and the first sub-barrier layers comprise GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35。
Optionally, the growth temperature of the well layer is 720-830 ℃, and the growth temperature of the first sub-barrier layer is 850-959 ℃.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: due to GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yThe N/GaN superlattice structure has higher energy band and can play a role in blocking electrons from entering the P-type GaN layer, so that an electron blocking layer is not required to be arranged to block the electrons from flowing out of the active layer in the invention, the arrangement can improve the number of holes entering the active layer while limiting the electrons from leaving the active layer, further improve the number of holes which are compositely luminous with the electrons in the active layer, improve the luminous efficiency of the light-emitting diode, simultaneously reduce the polarization condition among the electron blocking layer, the active layer and the P-type layer caused by the arrangement of the electron blocking layer in the epitaxial layer, further avoid the reduction of the luminous band gap in the epitaxial layer, increase the recombination efficiency of the electrons and the holes, and further increase the luminous two-layer GaN layerThe luminous efficiency of the diode.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another epitaxial wafer provided in an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 4 to fig. 5 are flowcharts of epitaxial wafer structures during the preparation process of an epitaxial wafer according to an embodiment of the present invention;
fig. 6 is another method for manufacturing an epitaxial wafer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an epitaxial wafer in a preparation process of another epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a structural diagram of an led epitaxial wafer according to an embodiment of the present invention. As shown in fig. 1, the epitaxial wafer includes a substrate 1, and a low-temperature GaN buffer layer 2, an undoped GaN layer 3, an N-type GaN layer 4, an active layer 5, and a P-type GaN layer 6 stacked in this order on the substrate 1.
The active layer 5 includes a first barrier layer 51 and a plurality of well layers 521, the first barrier layer 51 includes a plurality of first sub-barrier layers 511, the first sub-barrier layers 511 and the well layers 521 are alternately stacked, the well layers 521 are InGaN well layers, and the first sub-barrier layers 511 include GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yAn N/GaN superlattice structure is adopted,wherein, 0<x<0.08，0<y<0.07，0.05<z<0.35。
Due to GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yThe N/GaN superlattice structure has a higher energy band and can play a role in blocking electrons from entering the P-type GaN layer, so that an electron blocking layer is not required to be arranged to block the electrons from flowing out of the active layer, the arrangement can limit the electrons from leaving the active layer and simultaneously improve the number of holes entering the active layer, further improve the number of holes which are compositely luminous with the electrons in the active layer, improve the luminous efficiency of the light-emitting diode and simultaneously reduce the polarization condition among the electron blocking layer, the active layer and the P-type layer caused by the arrangement of the electron blocking layer in the epitaxial layer, further avoid the reduction of a luminous band gap in the epitaxial layer, improve the recombination efficiency of the electrons and the holes and further improve the luminous efficiency of the light-emitting diode.
At the same time, GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yTwo-dimensional electron gas and two-dimensional hole gas, GaN/In, can be formed In the N/GaN superlattice structurexGa1-xN/AlzGa1-zN/InyGa1-yThe formation of the two-dimensional electron gas and the two-dimensional hole gas in the N/GaN superlattice structure can limit electrons in the active layer, so that more electrons can be radiatively combined with holes in the active layer, and the luminous efficiency of the light-emitting diode is further improved.
Alternatively, the thickness of the undoped GaN layer 3 may be 0.1 to 2.0 μm.
Wherein, the doping element in the N-type GaN layer 4 is Si. The thickness of the N-type GaN layer 4 may be 1-5 μm.
Illustratively, the ratio of x to z is 0.15:1 to 0.4: 1. Setting the ratio of x to z to the above range can make the distribution of electrons and holes recombined in the active layer more uniform, thereby improving the light emitting efficiency of the light emitting diode.
Alternatively, x>y. x is greater than y such that GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yTwo in N/GaN superlattice structureThe two-dimensional electron gas and the two-dimensional hole gas are easier to form, so that electrons and holes are easier to be radiatively combined in the active layer, and the luminous efficiency of the light-emitting diode is improved.
Further, the ratio of x to y can be 3:1 to 5: 1. The arrangement can enable more electrons and holes to be radiatively recombined in the active layer, and the luminous efficiency of the light-emitting diode is improved.
Specifically, the ratio of x to y may be 4:1, and when the ratio of x to y is set to 4:1, the luminous efficiency of the led is greatly improved.
As shown in FIG. 1, in the present embodiment, a P-type GaN layer 6 is further disposed on the active layer 5, and the thickness of the P-type GaN layer 6 may be 100-200 nm.
Fig. 2 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 2, the active layer 5 further includes a second barrier layer 53, the second barrier layer 53 includes two GaN barrier layers 531, the two GaN barrier layers 531 are respectively disposed on two sides of the first barrier layer 51, and a well layer 521 is disposed between the two GaN barrier layers 531 and the first barrier layer 51.
Two GaN barrier layers 531 are disposed on both sides of the first barrier layer 51, respectively, to reduce GaN/InxGa1-xN/AlzGa1- zN/InyGa1-yThe lattice mismatch between the N/GaN superlattice structure and the P-type GaN layer further improves the overall quality of the epitaxial layer and ensures the luminous efficiency of the light-emitting diode.
Optionally, the active layer 5 further includes a well layer 521 disposed between the GaN barrier layer 531 near the N-type GaN layer 4 and the N-type GaN layer 4. This arrangement facilitates smooth entry of electrons in the N-type GaN layer into the active layer.
Illustratively, the thickness of GaN barrier layer 531 may be the same as the thickness of first sub-barrier layer 511. The thickness of the GaN barrier layer is set to be the same, so that the whole growth and manufacturing of the active layer are facilitated.
The thickness of the first sub-barrier layer 511 may be 8-20 nm. The thickness of the first sub-barrier layer is set in the range, so that the quality of the first sub-barrier layer can be guaranteed, the overall quality of the epitaxial layer is improved, and the light emitting efficiency of the light emitting diode is guaranteed. The thickness of the well layer 521 may be 3 nm.
Optionally, the number of first sub-barrier layers 511 may be 3 to 13. The number of the first sub-barrier layers is set to be within the range, so that more electrons can be subjected to radiation recombination with holes in the active layer, the light emitting efficiency of the light emitting diode is guaranteed, and the manufacturing cost of the active layer is not increased.
As shown in fig. 2, in the present embodiment, a P-type GaN layer 6 and a P-type contact layer 7 are further provided on the active layer 5, respectively. Wherein, the thickness of the P-type contact layer 7 can be 5-300 nm.
Fig. 3 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 3, the method includes:
step S11: a substrate is provided.
Among them, a sapphire substrate may be used as the substrate.
Optionally, the preparation method may further include annealing the substrate. So as to obtain a cleaner substrate with better surface quality, and is beneficial to ensuring the quality of an epitaxial layer grown on the substrate.
Wherein annealing the substrate may include: and annealing the substrate in a hydrogen atmosphere, wherein the annealing time is 8min, the annealing temperature is 1000-1200 ℃, and the annealing pressure is 400-600 Torr.
Further, after the substrate is annealed, the substrate may be nitrided, that is, a layer of AlN is grown on the substrate to reduce lattice mismatch between the substrate and the N-type GaN layer.
Step S12: and growing a low-temperature GaN buffer layer on the substrate.
Wherein, the growth temperature of the low-temperature GaN buffer layer can be 400-600 ℃, and the growth pressure of the low-temperature GaN buffer layer can be 400-600 Torr. The low-temperature GaN buffer layer obtained at the temperature has good quality, and can effectively reduce the problem of lattice mismatch between the N-type GaN layer and the substrate.
Optionally, the growth thickness of the low-temperature GaN buffer layer can be 15-35 nm.
Further, after the growth on the low-temperature GaN buffer layer is completed, the low-temperature GaN buffer layer may be subjected to an in-situ annealing process. And the low-temperature GaN buffer layer is annealed, so that dislocation in the low-temperature GaN buffer layer can be reduced, the quality of the low-temperature GaN buffer layer is ensured, and the growth of a subsequent epitaxial layer is facilitated.
Wherein annealing the low temperature GaN buffer layer comprises:
and carrying out in-situ annealing treatment on the low-temperature GaN buffer layer under the conditions that the annealing temperature is 1000-1200 ℃ and the annealing pressure is 400-600 Torr, wherein the annealing time is 5-10 min.
Step S13: and growing an undoped GaN layer on the low-temperature GaN buffer layer.
In step S13, the growth temperature of the undoped GaN layer may be 1000 to 1100 ℃, and the growth pressure may be 100 to 500 Torr. The quality of the undoped GaN layer grown under the condition is better.
Illustratively, the thickness of the undoped GaN layer may be 1-5 μm.
Step S14: and growing an N-type GaN layer on the undoped GaN layer.
In the embodiment of the invention, the N-type GaN layer can be an N-type GaN layer.
Wherein the growth temperature of the N-type GaN layer can be 1000-1200 deg.C, and the growth pressure can be 100-500 Torr.
The thickness of the N-type GaN layer can be 1-5 μm.
Optionally, the doping element of the N-type GaN layer is a Si element, and the doping concentration of the Si element is 1018～1019cm-3。
Fig. 4 is a schematic structural view of the epitaxial layer after step S14, in which a low-temperature GaN buffer layer 2, an undoped GaN layer 3, and an N-type GaN layer 4 are sequentially stacked on a substrate 1.
Step S15: and growing an active layer on the N-type GaN layer.
The active layer may include a first barrier layer and a plurality of well layers, the first barrier layer includes a plurality of first sub-barrier layers, the first sub-barrier layers and the well layers are alternately stacked, the well layers are InGaN well layers, and the first sub-barrier layers include GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35。
The growth temperature of the well layer is 720-830 ℃, and the growth temperature of the first sub-barrier layer is 850-959 ℃. The growth temperatures of the well layer and the first sub-barrier layer are respectively set in the ranges, so that the quality of the grown active layer is better, and the light emitting efficiency of the light emitting diode is ensured.
After the step S15 is performed, the epitaxial layer structure may be as shown in fig. 5, where the low-temperature GaN buffer layer 2, the undoped GaN layer 3, the N-type GaN layer 4, and the active layer 5 are sequentially grown on the substrate 1, the active layer 5 includes a first barrier layer 51 and a plurality of well layers 521, the first barrier layer 51 includes a plurality of first sub-barrier layers 511, and the first sub-barrier layers 511 and the well layers 521 are alternately stacked.
Step S16: and growing a P-type GaN layer on the active layer.
In the present embodiment, the growth temperature of the P-type GaN layer can be 850-1080 ℃ and the growth pressure can be 100-300 Torr.
The growth thickness of the P-type GaN layer can be 100-800 nm.
The epitaxial wafer structure after the above steps is shown in fig. 1, and a P-type GaN layer 6 is disposed on the active layer 5.
Due to GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yThe N/GaN superlattice structure has a higher energy band and can play a role in blocking electrons from entering the P-type GaN layer, so that an electron blocking layer is not required to be arranged to block the electrons from flowing out of the active layer, the arrangement can limit the electrons from leaving the active layer and simultaneously improve the number of holes entering the active layer, further improve the number of holes which are compositely luminous with the electrons in the active layer, improve the luminous efficiency of the light-emitting diode and simultaneously reduce the polarization condition among the electron blocking layer, the active layer and the P-type layer caused by the arrangement of the electron blocking layer in the epitaxial layer, further avoid the reduction of a luminous band gap in the epitaxial layer, improve the recombination efficiency of the electrons and the holes and further improve the luminous efficiency of the light-emitting diode.
Optionally, the preparation method can further comprise:
and after the growth of the epitaxial wafer is finished, annealing the epitaxial wafer in a nitrogen atmosphere, wherein the annealing temperature is 650-850 ℃, and the annealing time is 5-15 min. After the epitaxial wafer is grown, the epitaxial wafer is annealed, so that Mg atoms in the P-type GaN layer can be activated, the hole concentration in the P-type GaN layer is improved, and the luminous efficiency of the light-emitting diode is improved.
Fig. 6 is another method for preparing an epitaxial wafer according to an embodiment of the present invention, which includes the steps of:
step S21: a substrate is provided.
Step S22: and growing a low-temperature GaN buffer layer on the substrate.
Step S23: and growing an undoped GaN layer on the low-temperature GaN buffer layer.
In step S23, the growth temperature of the undoped GaN layer may be 1000 to 1100 ℃, and the growth pressure may be 100 to 500 Torr. The quality of the undoped GaN layer grown under the condition is better.
Illustratively, the thickness of the undoped GaN layer may be 1-5 μm.
Step S24: and growing an N-type GaN layer on the undoped GaN layer.
Step S25: and growing an active layer on the N-type GaN layer.
The active layer may include a first barrier layer including a plurality of first sub-barrier layers alternately stacked with well layers of InGaN, and a plurality of well layers including GaN/InxGa1-xN/AlzGa1-zN/InyGa1- yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35。
Further, the active layer further comprises a second barrier layer, the second barrier layer comprises two GaN barrier layers, the two GaN barrier layers are arranged on two sides of the first barrier layer respectively, and a well layer is arranged between the two GaN barrier layers and the first barrier layer.
The growth temperature of the GaN barrier layer can be the same as that of the first sub-barrier layer, and the whole active layer can be conveniently grown and manufactured.
The structure of the epitaxial wafer after step S25 is shown in fig. 7, and a low temperature GaN buffer layer 2, an undoped GaN layer 3, an N-type GaN layer 4, and an active layer 5 are sequentially stacked on a substrate 1. The active layer 5 includes a first barrier layer 51 and a plurality of well layers 521, the first barrier layer 51 includes a plurality of first sub-barrier layers 511, and the first sub-barrier layers 511 and the well layers 521 are alternately stacked. The active layer 5 further includes a second barrier layer 53, the second barrier layer 53 includes two GaN barrier layers 531, the GaN barrier layers 531 and the well layer 521 are alternately stacked, and the two GaN barrier layers 531 are respectively disposed on two sides of the first barrier layer 51.
Step S26: and growing a P-type GaN layer on the active layer.
Step S27: and growing a P-type contact layer on the P-type GaN layer.
Wherein the growth temperature of the P-type contact layer can be 650-850 deg.C, and the growth pressure can be 100-300 Torr. The thickness of the film can be set to 5-300 nm. The structure of the epitaxial wafer after the step S27 is performed is shown in fig. 2,. The structure of the GaN-based active material comprises a substrate 1, and a low-temperature GaN buffer layer 2, an undoped GaN layer 3, an N-type GaN layer 4, an active layer 5, a P-type GaN layer 6 and a P-type contact layer 7 which are sequentially stacked on the substrate 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (8)

1. An epitaxial wafer of a light emitting diode, which comprises a substrate, and a low-temperature GaN buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer and a P-type GaN layer which are sequentially stacked on the substrate,
the active layer comprises a first barrier layer and a plurality of well layers, the first barrier layer comprises a plurality of first sub-barrier layers, the first sub-barrier layers and the well layers are alternately stacked, the well layers are InGaN well layers, and the first sub-barrier layers comprise GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35，
x is greater than y, and the ratio of x to y is 3: 1-5: 1.
2. The epitaxial wafer of claim 1, wherein the ratio of x to z is 0.15:1 to 0.4: 1.
3. The epitaxial wafer of claim 1, wherein the active layer further comprises a second barrier layer comprising two GaN barrier layers respectively disposed on both sides of the first barrier layer, and wherein one of the well layers is disposed between the two GaN barrier layers and the first barrier layer.
4. The epitaxial wafer of claim 3, wherein the thickness of the GaN barrier layer is the same as the thickness of the first sub-barrier layer.
5. The epitaxial wafer of claim 1, wherein the thickness of the first sub-barrier layer is 8-20 nm.
6. The epitaxial wafer of claim 1, wherein the number of layers of the first sub-barrier layer is 3 to 13.
7. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a low-temperature GaN buffer layer on the substrate;
growing an undoped GaN layer on the low-temperature GaN buffer layer;
growing an N-type GaN layer on the undoped GaN layer;
growing an active layer on the N-type GaN layer;
growing a P-type GaN layer on the active layer,
the active layer comprises a first barrier layer and a plurality of well layers, the first barrier layer comprises a plurality of first sub-barrier layers, the first sub-barrier layers and the well layers are alternately stacked, the well layers are InGaN well layers, and the first sub-barrier layers comprise GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structure, wherein 0<x<0.08，0<y<0.07，0.05<z<0.35，
x is greater than y, and the ratio of x to y is 3: 1-5: 1.
8. The method according to claim 7, wherein the growth temperature of the well layer is 720-830 ℃ and the growth temperature of the first sub-barrier layer is 850-959 ℃.
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