CN114156380B - Light-emitting diode epitaxial wafer for improving internal quantum efficiency and preparation method thereof - Google Patents

Light-emitting diode epitaxial wafer for improving internal quantum efficiency and preparation method thereof Download PDF

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CN114156380B
CN114156380B CN202111442421.6A CN202111442421A CN114156380B CN 114156380 B CN114156380 B CN 114156380B CN 202111442421 A CN202111442421 A CN 202111442421A CN 114156380 B CN114156380 B CN 114156380B
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CN114156380A (en
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陈张笑雄
卢云霞
葛永晖
贾胜敏
陆香花
李鹏
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

The invention discloses a light-emitting diode epitaxial wafer for improving internal quantum efficiency and a preparation method thereof, belonging to the field of light-emitting diode manufacturing. The low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer is added between the undoped GaN layer and the N-type GaN layer, the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer grows at a lower temperature, N gaps are difficult to form at the lower temperature, the generation of the N gaps is reduced, in atoms carried In the superlattice optimizing layer can react with the N gaps In advance, the possibility that the N gaps extend into the multi-quantum-well layer to form photon annihilation points is reduced, and the internal quantum efficiency of the light-emitting diode epitaxial wafer is improved. The GaN transition layer in the superlattice optimization layer is doped with Si, so that the increase and flow of electrons can be promoted, electrons can enter the InGaN/GaN multiple quantum well layer more uniformly by matching with the potential barrier of the InAlGaN transition layer, and the light emitting uniformity is improved while the internal quantum efficiency is improved.

Description

Light-emitting diode epitaxial wafer for improving internal quantum efficiency and preparation method thereof
Technical Field
The disclosure relates to the field of light-emitting diode manufacturing, in particular to a light-emitting diode epitaxial wafer for improving internal quantum efficiency and a preparation method thereof.
Background
A light emitting diode is a semiconductor electronic device capable of emitting light. As a novel efficient, environment-friendly and green solid-state lighting source, the solid-state lighting source is rapidly and widely applied to traffic lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlights and the like, and the improvement of the luminous efficiency of chips is a continuously pursued goal of light-emitting diodes.
The light-emitting diode epitaxial wafer is a basic structure for preparing a light-emitting diode, and at least comprises a substrate, a buffer layer, an undoped GaN layer, an n-type GaN layer, an InGaN/GaN multi-quantum well layer and a p-type GaN layer on the substrate, wherein electrons provided by the n-type GaN layer and holes provided by the p-type GaN layer enter the InGaN/GaN multi-quantum well layer to perform compound luminescence.
Because more defects exist on the surface of the underlying structure in front of the undoped GaN layer, the growth temperature of the undoped GaN layer is higher, and Ga atoms which are high in viscosity and active at high temperature are more easily aggregated in the initial growth stage of the undoped GaN layer under the influence of the temperature and the defects, so that more N gaps exist in the undoped GaN layer. In the subsequent epitaxial structure growth process, the N gaps gradually extend into the N-type GaN layer and the InGaN/GaN multiple quantum well layer, defects In the N-type GaN layer and the InGaN/GaN multiple quantum well layer are increased, and if In atoms are separated out In a larger amplitude In the growth process of the InGaN/GaN multiple quantum well layer, the In atoms In the InGaN/GaN multiple quantum well layer can be captured by the N gaps In the InGaN/GaN multiple quantum well layer to form photon annihilation points, and electrons and holes In the photon annihilation points are combined into non-radiative compounds, so that the internal quantum efficiency of the light-emitting diode epitaxial wafer is reduced.
Disclosure of Invention
The embodiment of the disclosure provides a light-emitting diode epitaxial wafer for improving internal quantum efficiency and a preparation method thereof, which can improve the crystal quality of the light-emitting diode epitaxial wafer so as to improve the internal quantum efficiency of the light-emitting diode epitaxial wafer. The technical scheme is as follows:
the embodiment of the disclosure provides a light-emitting diode epitaxial wafer for improving internal quantum efficiency, which comprises a substrate, a buffer layer, an undoped GaN layer, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer, an n-type GaN layer, an InGaN/GaN multiple quantum well layer and a p-type GaN layer which are sequentially laminated on the substrate,
the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer comprises an InAlGaN transition layer, an InGaN transition layer and a GaN transition layer, wherein the GaN transition layer is doped with Si.
Optionally, the concentration of Si doped in the GaN transition layer is 1×10 18 cm -3 ～1×10 19 cm -3 。
Optionally, the InAlGaN transition layer comprises 10% -50% of In component and 3% -20% of Al component.
Optionally, the thickness of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is 30-70 nm.
Optionally, the thickness of the InAlGaN transition layer is 1-3 nm, the growth thickness of the InGaN transition layer is 2-3 nm, and the growth thickness of the GaN transition layer is 5-8 nm.
Optionally, the InGaN/GaN multiple quantum well layer comprises a plurality of InGaN well layers and GaN barrier layers which are alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer in the InGaN/GaN multiple quantum well layer are respectively divided into an end-point InGaN well layer and an end-point GaN barrier layer, the end-point InGaN well layer is positioned between the end-point GaN barrier layer and the p-type GaN layer,
and Mg is doped in the end-point InGaN well layer and the end-point GaN barrier layer.
The embodiment of the disclosure provides a preparation method of a light-emitting diode epitaxial wafer for improving internal quantum efficiency, which comprises the following steps:
providing a substrate;
sequentially growing a buffer layer, an undoped GaN layer, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer, an n-type GaN layer, an InGaN/GaN multi-quantum well layer and a p-type GaN layer on the substrate,
the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer comprises an InAlGaN transition layer, an InGaN transition layer and a GaN transition layer, wherein the GaN transition layer is doped with Si.
Optionally, the growth temperature of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is 300-400 ℃ lower than that of the undoped GaN layer.
Optionally, the growth rotating speed of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is 500-800 rpm.
Optionally, the InGaN/GaN multiple quantum well layer comprises a plurality of InGaN well layers and GaN barrier layers which are alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer in the InGaN/GaN multiple quantum well layer are respectively divided into an end-point InGaN well layer and an end-point GaN barrier layer, the end-point InGaN well layer is positioned between the end-point GaN barrier layer and the p-type GaN layer,
and the growth temperature of the end-point InGaN well layer and the end-point GaN barrier layer is lower than that of the InGaN well layer and the GaN barrier layer except the end-point InGaN well layer and the end-point GaN barrier layer in the InGaN/GaN multiple quantum well layer.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is added between the undoped GaN layer and the n-type GaN layer, on one hand, the superlattice structure can release certain stress, and defects caused by the stress in the growth process of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer are reduced, so that the quality of the superlattice optimization layer and the n-type GaN layer is improved; on the other hand, the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer grows at a lower temperature, N gaps are difficult to form at the lower temperature, the N gaps inside the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer are reduced, in atoms carried In the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer can react with the N gaps extending into the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer In advance, the possibility that the N gaps extend into the multiple quantum well layer to form photon annihilation points is reduced, the composite light emitting efficiency In the InGaN/GaN multiple quantum well layer is improved, and the internal quantum efficiency of the light emitting diode epitaxial wafer is improved. And the GaN transition layer in the InAlGaN/InGaN/GaN superlattice optimizing layer is doped with Si, so that the increase and flow of electrons can be promoted, electrons can enter the InGaN/GaN multiple quantum well layer more uniformly by matching with the potential barrier of the InAlGaN transition layer, and the light emitting uniformity is improved while the internal quantum efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another led epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing a light emitting diode epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure;
fig. 4 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode for improving internal quantum efficiency according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure, and referring to fig. 1, it can be seen that the embodiment of the present disclosure provides a light emitting diode epitaxial wafer for improving internal quantum efficiency, which includes a substrate 1, a buffer layer 2, an undoped GaN layer 3, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4, an n-type GaN layer 5, an InGaN/GaN multiple quantum well layer 6 and a p-type GaN layer 7 sequentially stacked on the substrate 1.
The low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 includes an InAlGaN transition layer 41, an InGaN transition layer 4342, and a GaN transition layer 43, and the GaN transition layer 43 is doped with Si.
The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 is added between the undoped GaN layer 3 and the n-type GaN layer 5, on one hand, the superlattice structure can release certain stress, and defects caused by the stress in the growth process of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 are reduced, so that the quality of the superlattice optimization layer 4 and the n-type GaN layer 5 is improved; on the other hand, the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer 4 grows at a lower temperature, N gaps are difficult to form at the lower temperature, the N gaps inside the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer 4 are reduced, on the other hand, in atoms carried In the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer 4 can react with the N gaps extending into the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer 4 In advance, the possibility that the N gaps extend into the multiple quantum well layer 6 to form photon annihilation points is reduced, so that the composite light extraction efficiency In the InGaN/GaN multiple quantum well layer 6 is improved, and the internal quantum efficiency of the light emitting diode epitaxial wafer is improved. And the GaN transition layer 43 in the InAlGaN/InGaN/GaN superlattice optimization layer 4 is doped with Si, so that the increase and flow of electrons can be promoted, electrons can enter the InGaN/GaN multiple quantum well layer 6 more uniformly by matching with the potential barrier of the InAlGaN transition layer 41, and the light emitting uniformity is improved while the internal quantum efficiency is improved.
The internal quantum efficiency of the InGaN/GaN multiple quantum well layer 6 is the internal quantum efficiency of the led epitaxial wafer.
Alternatively, the concentration of Si incorporated in the GaN transition layer 43 is 1×10 18 cm -3 ～1×10 19 cm -3 。
The doping concentration of Si in the GaN transition layer 43 is within the above range, and the uniform supply of electrons can be ensured, and the doping concentration of Si is very low, far lower than that in the n-type GaN layer 5, so that the concentration of electrons in the GaN transition layer 43 is also far lower than that in the n-type GaN layer 5. Under the condition of no power on, part of electrons can enter the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer 4 from the n-type GaN layer 5 with higher concentration, the distance between the electrons and the InGaN/GaN multiple quantum well layer 6 is increased, more migration time of holes can enter the InGaN/GaN multiple quantum well layer 6, and the hole concentration in the InGaN/GaN multiple quantum well layer 6 is improved to improve the internal quantum efficiency of the InGaN/GaN multiple quantum well layer 6.
Optionally, the In component proportion In the InAlGaN transition layer 41 is 10% to 50%, and the Al component proportion is 3% to 20%.
The ratios of the In component and the Al component In the InAlGaN transition layer 41 are respectively In the above ranges, the InAlGaN transition layer 41 has enough In atoms which react with the N voids, and meanwhile, the InAlGaN transition layer 41 also has a certain potential barrier to play a role of laterally expanding electrons, so that the uniformity of electrons finally entering the InGaN/GaN multiple quantum well layer 6 is improved, and the light emitting uniformity of the InGaN/GaN multiple quantum well layer 6 is improved.
Alternatively, the low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 has a thickness of 30-70 nm.
The thickness of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 is in the above range, so that the crystal quality of the InAlGaN/InGaN/GaN superlattice optimization layer 4 can be ensured, the quality of the obtained n-type GaN layer 5 can be effectively improved, and the preparation cost of the light-emitting diode epitaxial wafer can not be excessively improved.
Illustratively, inAlGaN transition layer 41 has a thickness of 1-3 nm, inGaN transition layer has a growth thickness of 2-3 nm, and GaN transition layer 43 has a growth thickness of 5-8 nm.
The thicknesses of the layers in the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 are respectively within the above ranges, so that the InAlGaN transition layer 41 can provide proper blocking capability for electrons, and the InGaN transition layer and the GaN transition layer 43 can respectively have enough space to react with the N voids and provide enough accommodation space for electrons. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 has a good effect of releasing stress, and can effectively improve the internal quantum efficiency of the finally obtained light-emitting diode epitaxial wafer.
Alternatively, the period number of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 may be 2 to 4. The quality and stress releasing effect of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 can be guaranteed.
Illustratively, the ratio of the In component In the InGaN transition layer is 0.11 to 0.23. The N voids extending into the low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 can be effectively reduced to reduce the possibility that photon annihilation points are formed in the InGaN/GaN multiple quantum well layer 6.
Fig. 2 is a schematic structural diagram of another led epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure, and referring to fig. 2, it can be seen that in another implementation manner of the present disclosure, the led epitaxial wafer may include a substrate 1, a buffer layer 2 grown on the substrate 1, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer 4, an n-type GaN layer 5, an InGaN/GaN multiple quantum well layer 6, an AlGaN electron blocking layer 8, a p-type GaN layer 7, and a p-type contact layer 9.
It should be noted that the low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 shown in fig. 2 has the same structure as the low temperature InAlGaN/InGaN/GaN superlattice optimization layer 4 shown in fig. 1, and thus will not be described here.
Alternatively, the substrate 1 may be a sapphire substrate 1. Easy to manufacture and obtain.
Illustratively, the buffer layer 2 may include a GaN buffer layer 2 sequentially stacked on the substrate 1. Lattice mismatch can be effectively relieved.
In other implementations provided by the present disclosure, the buffer layer 2 may also be one of aluminum nitride, aluminum gallium nitride, or aluminum indium gallium nitride. The present disclosure is not limited in this regard.
Alternatively, the doping element of the n-type GaN layer 5 may be Si, and the doping concentration of the Si element may be 1×10 18 ～1×10 19 cm -3 . The overall quality of the n-type GaN layer 5 is good.
The thickness of the n-type GaN layer 5 may be 1-5 μm, for example. The quality of the whole obtained n-type GaN layer 5 is better.
In one implementation provided by the present disclosure, the thickness of the n-type GaN layer 5 may be 3 μm. The present disclosure is not limited in this regard.
Illustratively, the InGaN/GaN multiple quantum well layer 6 includes a plurality of InGaN well layers and GaN barrier layers alternately stacked, and the thickness of the InGaN well layers may be 2 to 5nm and the thickness of the GaN barrier layers may be 8 to 20nm.
Illustratively, the overall thickness of the InGaN/GaN multiple quantum well layer 6 may be 50-130 nm with an in molar content of 13-25%.
Alternatively, the InGaN/GaN multiple quantum well layer 6 includes a plurality of InGaN well layers and GaN barrier layers alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer 7 in the InGaN/GaN multiple quantum well layer 6 are divided into an end InGaN well layer and an end GaN barrier layer, respectively, and the end InGaN well layer is located between the end GaN barrier layer and the p-type GaN layer 7. Mg is doped in both the end InGaN well layer and the end GaN barrier layer.
The end point InGaN well layer is positioned between the end point GaN barrier layer and the p-type GaN layer 7, has a certain hole storage capacity, and can improve the quantity and uniformity of holes entering the InGaN/GaN multiple quantum well layer 6; mg is doped in both the end-point InGaN well layer and the end-point GaN barrier layer, so that the number of holes entering the InGaN/GaN multiple quantum well layer 6 can be further increased, and the internal quantum efficiency of the finally obtained light emitting diode can be further increased.
Alternatively, the Al composition in the AlGaN electron blocking layer 8 may be 0.15 to 0.25. The effect of blocking electrons is good.
Alternatively, the thickness of the AlGaN electron blocking layer 8 may be 20 to 100nm. The quality of the obtained AlGaN electron blocking layer 8 is good.
Can provide enough holes and ensure that the whole cost of the light-emitting diode epitaxial wafer is not excessively high.
The thickness of the p-type contact layer 9 may be 10 to 50nm, for example.
It should be noted that, in other implementations provided in the present disclosure, the led epitaxial wafer may also include other hierarchies, which is not limited in this disclosure.
Fig. 3 is a flowchart of a method for preparing an led epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure, and referring to fig. 3, it can be seen that the embodiment of the present disclosure provides a method for preparing an led epitaxial wafer for improving internal quantum efficiency, and a method for preparing an led epitaxial wafer for improving internal quantum efficiency, including:
s101: a substrate is provided.
S102: and sequentially growing a buffer layer, an undoped GaN layer, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer, an n-type GaN layer, an InGaN/GaN multiple quantum well layer and a p-type GaN layer on the substrate. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer comprises an InAlGaN transition layer, an InGaN transition layer and a GaN transition layer, wherein the GaN transition layer is doped with Si.
The technical effects corresponding to the method for manufacturing the light emitting diode in fig. 3 may correspond to those of the light emitting diode structure shown in fig. 1, and thus will not be described herein.
Optionally, in step S102, the growth temperature of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is 300-400 ℃ lower than the growth temperature of the undoped GaN layer.
The growth temperature of the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer is lower than that of the undoped GaN layer by a range above, so that the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer can be grown at a lower temperature, N gaps existing in the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer are greatly reduced, and photon annihilation points which can be obtained later are effectively reduced.
Illustratively, the growth pressure of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer is 150-250 Torr. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer with uniform growth and fewer defects can be obtained.
Alternatively, the growth speed of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer is 500-800 rpm. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer with uniform growth and fewer defects can be obtained.
Alternatively, the growth temperature of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer may be 750-900 ℃. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer with better quality can be obtained.
Illustratively, the growth temperatures of the InAlGaN transition layer, the InGaN transition layer, and the GaN transition layer may all be the same. The quality of the low-temperature InAlGaN/InGaN/GaN superlattice optimizing layer can be ensured, and the overall cost can be controlled.
In other implementations provided by the present disclosure, the growth temperatures of the InAlGaN transition layer, the InGaN transition layer, and the GaN transition layer may also be set to 800 ℃, and 880 ℃, respectively, the growth rotational speed of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer is set to 600rpm, and the growth pressure of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer is set to 200Torr. The low-temperature InAlGaN/InGaN/GaN superlattice optimization layer with better quality can be obtained. The present disclosure is not limited in this regard.
The growth temperature of the undoped GaN layer may be 1000 to 1200 c, for example. The quality of the undoped GaN layer can be guaranteed to be good, and the formed N gaps are few.
Fig. 4 is a flowchart of another method for preparing an led epitaxial wafer for improving internal quantum efficiency according to an embodiment of the present disclosure, and referring to fig. 4, it can be known that the method for preparing an led epitaxial wafer according to the present disclosure may include:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: the surface of the substrate is treated for 6-10 min under the hydrogen atmosphere.
Illustratively, the temperature of the reaction chamber may be 1000-1200 ℃ and the pressure of the reaction chamber may be 200-500 Torr when treating the surface of the substrate.
In one implementation provided by the present disclosure, when the substrate is processed, the temperature of the reaction chamber may also be 1100 ℃, and the duration of processing the surface of the substrate may be 8 minutes.
Step S201 may further include: nitriding the surface of the substrate, and paving a layer of nitrogen atoms on the surface of the substrate. The rapid growth of gallium nitride material can be facilitated.
S202: a buffer layer is grown on the substrate.
Optionally, the temperature of the reaction cavity is controlled to be 450-600 ℃, the pressure of the reaction cavity is controlled to be 200-500 torr, and the GaN buffer layer is grown. Obtaining the buffer layer with better quality.
S203: and growing an undoped GaN layer on the buffer layer.
The growth pressure of the undoped GaN layer may be 100-300 Torr. The growth temperature of the undoped GaN layer may be 100to 1200 a. The present disclosure is not limited in this regard.
S204: and growing a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer on the undoped GaN layer.
Step S204 may refer to the corresponding description in step S102 shown in fig. 3, and thus will not be described herein.
S205: an n-type GaN layer is grown on the buffer layer.
Alternatively, the growth temperature of the n-type GaN layer may be 950 ℃ to 1200 ℃, and the growth pressure of the n-type GaN layer may be 200Torr to 500Torr.
S206: and growing an InGaN/GaN multiple quantum well layer on the n-type GaN layer.
In step S206, the InGaN/GaN multiple quantum well layer includes an InGaN well layer and a GaN barrier layer grown alternately.
Alternatively, the growth temperature and the growth pressure of the InGaN well layer are respectively 700-800 ℃ and 100-300 torr, and the growth temperature and the growth pressure of the GaN barrier layer are respectively 700-900 ℃ and 100-300 torr. The quality of the obtained InGaN/GaN multiple quantum well layer is good.
Alternatively, the thickness of the InGaN well layer is 2-4 nm, and the thickness of the GaN barrier layer is 5-10 nm. The quality of the obtained InGaN/GaN multiple quantum well layer is good.
Optionally, the InGaN/GaN multiple quantum well layer includes a plurality of InGaN well layers and GaN barrier layers alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer in the InGaN/GaN multiple quantum well layer are respectively divided into an end InGaN well layer and an end GaN barrier layer, and the end InGaN well layer is located between the end GaN barrier layer and the p-type GaN layer. The growth temperature of the end point InGaN well layer and the end point GaN barrier layer is lower than that of the InGaN well layer and the GaN barrier layer except the end point InGaN well layer and the end point GaN barrier layer in the InGaN/GaN multiple quantum well layer.
The growth quality of the end-point InGaN well layer and the end-point GaN barrier layer can be ensured, and enough time is provided for doping of Mg.
Illustratively, the growth temperatures of the end-point InGaN well layer and the end-point GaN barrier layer may be 20-50 ℃ lower than the growth temperatures of the other well barrier layers in the InGaN/GaN multiple quantum well layer, respectively.
The whole quality of the InGaN/GaN multi-quantum well layer can be ensured, and stable transition between the InGaN/GaN multi-quantum well layer and the p-type GaN layer can be realized.
S207: and growing an AlGaN electron blocking layer on the InGaN/GaN multi-quantum well layer.
The growth temperature of the AlGaN electron blocking layer may be 600-1000 ℃, and the growth pressure of the AlGaN electron blocking layer may be 100-300 Torr. The AlGaN electron blocking layer grown under the condition has better quality, and is beneficial to improving the luminous efficiency of the light-emitting diode.
S208: and growing a p-type GaN layer on the AlGaN electron blocking layer.
S209: and growing a p-type contact layer on the p-type GaN layer.
Alternatively, the growth pressure of the p-type contact layer may be 100Torr to 300Torr, and the growth temperature of the p-type contact layer may be 850℃to 1050 ℃.
In one implementation provided by the present disclosure, the growth temperature of the p-type contact layer may be 950 ℃, and the growth pressure of the p-type contact layer may be 200Torr.
It should be noted that, the light emitting diode epitaxial wafer for improving internal quantum efficiency and the preparation method thereof shown in fig. 4 provide a more detailed growth mode of the light emitting diode epitaxial wafer compared with the preparation method of the light emitting diode shown in fig. 1.
The structure of the led epitaxial wafer after the completion of step S209 may be seen in fig. 2.
It should be noted that, in the embodiment of the present disclosure, the growth method of the light emitting diode is implemented using a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition ) apparatus. Adopts high-purity H 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH 4) as N-type dopant, trimethylaluminum (TMAL) as aluminum source, magnesium-cyclopentadienyl (CP 2 Mg) as P-type dopant.
While the present disclosure has been described above by way of example, and not by way of limitation, any person skilled in the art will recognize that many modifications, adaptations, and variations of the present disclosure can be made to the present embodiments without departing from the scope of the present disclosure.

Claims (10)

1. The light-emitting diode epitaxial wafer for improving the internal quantum efficiency is characterized by comprising a substrate, a buffer layer, an undoped GaN layer, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer, an n-type GaN layer, an InGaN/GaN multiple quantum well layer and a p-type GaN layer which are sequentially laminated on the substrate,
the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer comprises an InAlGaN transition layer, an InGaN transition layer and a GaN transition layer, wherein the GaN transition layer is doped with Si.
2. The internal quantum efficiency improving light emitting diode epitaxial wafer of claim 1, wherein the concentration of Si doped in the GaN transition layer is 1 x 10 18 cm -3 ～1×10 19 cm -3 。
3. The led epitaxial wafer of claim 1, wherein the InAlGaN transition layer has an In composition of 10% to 50% and an Al composition of 3% to 20%.
4. A light emitting diode epitaxial wafer for improving internal quantum efficiency according to any one of claims 1 to 3 wherein the thickness of the low temperature InAlGaN/InGaN/GaN superlattice optimized layer is 30 to 70nm.
5. A light emitting diode epitaxial wafer for improving internal quantum efficiency according to any one of claims 1 to 3 wherein the InAlGaN transition layer has a thickness of 1 to 3nm, the InGaN transition layer has a growth thickness of 2 to 3nm, and the GaN transition layer has a growth thickness of 5 to 8nm.
6. The light-emitting diode epitaxial wafer for improving internal quantum efficiency according to any one of claims 1 to 3, wherein the InGaN/GaN multiple quantum well layer comprises a plurality of InGaN well layers and GaN barrier layers alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer in the InGaN/GaN multiple quantum well layer are divided into an end-point InGaN well layer and an end-point GaN barrier layer, respectively, and the end-point InGaN well layer is located between the end-point GaN barrier layer and the p-type GaN layer,
and Mg is doped in the end-point InGaN well layer and the end-point GaN barrier layer.
7. The preparation method of the light-emitting diode epitaxial wafer for improving the internal quantum efficiency is characterized by comprising the following steps of:
providing a substrate;
sequentially growing a buffer layer, an undoped GaN layer, a low-temperature InAlGaN/InGaN/GaN superlattice optimization layer, an n-type GaN layer, an InGaN/GaN multi-quantum well layer and a p-type GaN layer on the substrate,
the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer comprises an InAlGaN transition layer, an InGaN transition layer and a GaN transition layer, wherein the GaN transition layer is doped with Si.
8. The method for preparing an internal quantum efficiency enhanced light emitting diode epitaxial wafer of claim 7, wherein the growth temperature of the low temperature InAlGaN/InGaN/GaN superlattice optimization layer is 300-400 ℃ lower than the growth temperature of the undoped GaN layer.
9. The method for preparing an epitaxial wafer of a light-emitting diode for improving internal quantum efficiency according to claim 7, wherein the growth rotation speed of the low-temperature InAlGaN/InGaN/GaN superlattice optimization layer is 500-800 rpm.
10. The method for preparing a light emitting diode epitaxial wafer for improving internal quantum efficiency according to any one of claims 7 to 9, wherein the InGaN/GaN multiple quantum well layer comprises a plurality of InGaN well layers and GaN barrier layers alternately stacked, the InGaN well layer and the GaN barrier layer closest to the p-type GaN layer in the InGaN/GaN multiple quantum well layer are divided into an end InGaN well layer and an end GaN barrier layer, respectively, and the end InGaN well layer is located between the end GaN barrier layer and the p-type GaN layer,
and the growth temperature of the end-point InGaN well layer and the end-point GaN barrier layer is lower than that of the InGaN well layer and the GaN barrier layer except the end-point InGaN well layer and the end-point GaN barrier layer in the InGaN/GaN multiple quantum well layer.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102664188A (en) * 2012-05-10 2012-09-12 电子科技大学 Gallium nitride-based high-electron-mobility transistor with composite buffering layer
CN203850331U (en) * 2014-04-30 2014-09-24 同辉电子科技股份有限公司 Gallium nitride-based light-emitting diode epitaxial wafer
CN104617174A (en) * 2015-01-12 2015-05-13 西安神光皓瑞光电科技有限公司 Insert layer structure of photoelectric device
CN205264741U (en) * 2015-12-26 2016-05-25 中国电子科技集团公司第十三研究所 GaN -based LED epitaxial wafer
CN105742415A (en) * 2016-03-01 2016-07-06 聚灿光电科技股份有限公司 Ultraviolet GaN-based LED epitaxy structure and manufacturing method thereof
CN205385037U (en) * 2016-03-01 2016-07-13 聚灿光电科技股份有限公司 Ultraviolet gan base led epitaxial structure
CN105932115A (en) * 2016-05-03 2016-09-07 湘能华磊光电股份有限公司 Epitaxial growth method for improving antistatic performance of LED chip
CN106098882A (en) * 2016-07-25 2016-11-09 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN108807620A (en) * 2018-06-15 2018-11-13 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN113675303A (en) * 2021-08-20 2021-11-19 江西兆驰半导体有限公司 Nitride light-emitting diode epitaxial wafer and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006054737A1 (en) * 2004-11-18 2006-05-26 Showa Denko K.K. Gallium nitride-based semiconductor stacked structure, method for fabrication thereof, gallium nitride-based semiconductor device and lamp using the device
KR101843513B1 (en) * 2012-02-24 2018-03-29 서울바이오시스 주식회사 Gallium nitride-based light emitting diode
CN107068822A (en) * 2017-01-16 2017-08-18 湘能华磊光电股份有限公司 A kind of smooth extraction efficiency high LED epitaxial structure and its growing method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102664188A (en) * 2012-05-10 2012-09-12 电子科技大学 Gallium nitride-based high-electron-mobility transistor with composite buffering layer
CN203850331U (en) * 2014-04-30 2014-09-24 同辉电子科技股份有限公司 Gallium nitride-based light-emitting diode epitaxial wafer
CN104617174A (en) * 2015-01-12 2015-05-13 西安神光皓瑞光电科技有限公司 Insert layer structure of photoelectric device
CN205264741U (en) * 2015-12-26 2016-05-25 中国电子科技集团公司第十三研究所 GaN -based LED epitaxial wafer
CN105742415A (en) * 2016-03-01 2016-07-06 聚灿光电科技股份有限公司 Ultraviolet GaN-based LED epitaxy structure and manufacturing method thereof
CN205385037U (en) * 2016-03-01 2016-07-13 聚灿光电科技股份有限公司 Ultraviolet gan base led epitaxial structure
CN105932115A (en) * 2016-05-03 2016-09-07 湘能华磊光电股份有限公司 Epitaxial growth method for improving antistatic performance of LED chip
CN106098882A (en) * 2016-07-25 2016-11-09 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN108807620A (en) * 2018-06-15 2018-11-13 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN113675303A (en) * 2021-08-20 2021-11-19 江西兆驰半导体有限公司 Nitride light-emitting diode epitaxial wafer and preparation method thereof

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