CN112864286B - Preparation method of light emitting diode epitaxial wafer - Google Patents

Preparation method of light emitting diode epitaxial wafer Download PDF

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CN112864286B
CN112864286B CN202011572865.7A CN202011572865A CN112864286B CN 112864286 B CN112864286 B CN 112864286B CN 202011572865 A CN202011572865 A CN 202011572865A CN 112864286 B CN112864286 B CN 112864286B
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layer
source
inalgan
time
epitaxial wafer
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CN112864286A (en
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王群
郭炳磊
葛永晖
董彬忠
李鹏
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Abstract

The disclosure provides a preparation method of a light-emitting diode epitaxial wafer, belonging to the field of light-emitting diode manufacturing. When the InAlGaN electronic barrier layer grows, reaction gas and organic metal sources are alternately introduced into the reaction cavity, and the organic metal sources are intensively adsorbed on the surface of the multi-quantum well layer, so that a large amount of In and Al are incorporated In a short time to be matched with the lattice constant of the multi-quantum well layer. And part of the organic metal source reacts with a large amount of reaction gas to generate the InAlGaN film, the content of nitrogen In the InAlGaN film is more than that of In, and the possibility that In the InAlGaN film migrates to the p-type GaN layer is reduced. The interface between the InAlGaN electronic barrier layer and the p-type GaN layer is ensured to be clear, impurities in the p-type GaN layer can be reduced, and the crystal quality of the p-type GaN layer is improved so as to improve the overall quality of the light-emitting diode epitaxial wafer.

Description

Preparation method of light emitting diode epitaxial wafer
Technical Field
The disclosure relates to the field of light emitting diode manufacturing, in particular to a method for preparing a light emitting diode epitaxial wafer.
Background
A light emitting diode is a semiconductor electronic component capable of emitting light. As a novel high-efficiency, environment-friendly and green solid-state illumination light source, the solid-state illumination light source is rapidly and widely applied, such as traffic signal lamps, automobile interior and exterior lamps, urban landscape illumination, mobile phone backlight sources and the like, and the aim of improving the light emitting efficiency of a chip is continuously pursued by light emitting diodes.
The light emitting diode epitaxial wafer is a primary finished product in the light emitting diode preparation process. The conventional light emitting diode epitaxial wafer comprises a substrate, and an n-type GaN layer, a multi-quantum well layer, an InAlGaN electronic barrier layer and a p-type GaN layer which are sequentially stacked on the substrate, wherein the multi-quantum well layer comprises GaN barrier layers and InGaN well layers which are alternately stacked. When the InAlGaN electronic barrier layer grows, In elements In the InAlGaN electronic barrier layer are easily precipitated into the p-type GaN layer, and the light emitting efficiency of the light emitting diode is influenced.
Disclosure of Invention
The embodiment of the disclosure provides a method for preparing a light emitting diode epitaxial wafer, which can improve the growth quality of the light emitting diode epitaxial wafer and improve the light emitting efficiency of the light emitting diode epitaxial wafer. The technical scheme is as follows:
the embodiment of the disclosure provides a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer comprises GaN barrier layers and InGaN well layers which are alternately grown;
alternately introducing reaction gas and an organic metal source into the reaction cavity until an InAlGaN electronic barrier layer is formed on the multi-quantum well layer;
and growing a p-type GaN layer on the InAlGaN electronic barrier layer.
Optionally, the ratio of the time for introducing the organic metal source into the reaction cavity each time to the time for introducing the reaction gas into the reaction cavity each time is 1:2 to 1: 10.
Optionally, the time for introducing the organic metal source into the reaction cavity each time is 5-15 s.
Optionally, the time duration of introducing the reaction gas into the reaction cavity each time is 10-20 s.
Optionally, introducing an organic metal source and a reaction gas into the reaction chamber, including:
and alternately introducing reaction gas and an organic metal source into the reaction cavity for 5-20 times until the InAlGaN electronic barrier layer is formed on the multi-quantum well layer.
Optionally, the reaction gas includes an ammonia source, the organic metal source includes a Ga source, an Al source, and an In source, the organic metal source and the reaction gas are introduced into the reaction chamber, and the method further includes:
and the flow of the Ga source introduced into the reaction cavity is unchanged, and the flow of the Al source and the flow of the In source introduced into the reaction cavity each time are gradually increased.
Optionally, the ratio of the flow rate of the Al source to the flow rate of the In source is 1: 5-1: 20.
Optionally, the introducing an organic metal source and a reaction gas into the reaction chamber further includes:
the flow of the ammonia source which is introduced into the reaction cavity at each time is gradually reduced to zero.
Optionally, the growth temperature of the InAlGaN electronic barrier layer is 850-1000 ℃.
Optionally, the thickness of the InAlGaN electronic barrier layer is 10-20 nm.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
when the InAlGaN electronic barrier layer is grown, reaction gas and an organic metal source are alternately introduced into the reaction cavity, the organic metal source can be adsorbed on the surface of the multi-quantum well layer, and then reacts with part of the introduced reaction gas, so that the InAlGaN film is grown on the surface of the multi-quantum well layer in a reaction way. The organic metal source is intensively adsorbed on the surface of the multiple quantum well layer, so that a large amount of In and Al can be incorporated In a short time, the lattice constant of the InAlGaN film is relatively close to that of an InGaN well layer or a GaN barrier layer, and the growth quality of the InAlGaN film is improved. The part of the organic metal source accumulated on the surface far away from the multi-quantum well layer reacts with a large amount of subsequently introduced reaction gas to generate the InAlGaN film, the content of nitrogen In the InAlGaN film is more than that of In, and the possibility that the In the InAlGaN film is transferred to the p-type GaN layer is reduced. The steps are repeated until the InAlGaN film is accumulated to form the InAlGaN electronic barrier layer, the obtained InAlGaN electronic barrier layer has high quality, the possibility that In atoms In the InAlGaN electronic barrier layer permeate the p-type GaN layer is low, the interface between the InAlGaN electronic barrier layer and the p-type GaN layer is clear, impurities In the p-type GaN layer can be reduced, and the integral crystal quality of the InAlGaN electronic barrier layer and the p-type GaN layer is improved so as to improve the integral quality of the light-emitting diode epitaxial wafer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," "third," and the like, as used in the description and in the claims of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top", "bottom", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes.
Fig. 1 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 1, the method for manufacturing an led epitaxial wafer includes:
s101: a substrate is provided.
S102: an n-type GaN layer is grown on the substrate.
S103: and growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer comprises GaN barrier layers and InGaN well layers which are alternately grown.
S104: and alternately introducing reaction gas and an organic metal source into the reaction cavity until the InAlGaN electronic barrier layer is formed on the multi-quantum well layer.
S105: and growing a p-type GaN layer on the InAlGaN electron blocking layer.
When the InAlGaN electronic barrier layer is grown, reaction gas and an organic metal source are alternately introduced into the reaction cavity, the organic metal source can be adsorbed on the surface of the multi-quantum well layer, then the reaction gas reacts with the introduced partial reaction gas, and the InAlGaN film is grown on the surface of the multi-quantum well layer through reaction. The organic metal source is intensively adsorbed on the surface of the multi-quantum well layer, so that a large amount of In and Al can be incorporated In a short time, the lattice constant of the InAlGaN film is ensured to be closer to that of an InGaN well layer or a GaN barrier layer, the growth quality of the InAlGaN film is improved, and a high barrier can be established In the InAlGaN film due to the large amount of In and Al incorporation, so that the effect of effectively blocking electrons is achieved. The part of the organic metal source accumulated on the surface far away from the multi-quantum well layer reacts with a large amount of subsequently introduced reaction gas to generate the InAlGaN film, the content of nitrogen In the InAlGaN film is more than that of In, and the possibility that the In the InAlGaN film is transferred to the p-type GaN layer is reduced. The steps are repeated until the InAlGaN film is accumulated to form the InAlGaN electronic barrier layer, the obtained InAlGaN electronic barrier layer has high quality, the possibility that In atoms In the InAlGaN electronic barrier layer permeate the p-type GaN layer is low, the interface between the InAlGaN electronic barrier layer and the p-type GaN layer is clear, impurities In the p-type GaN layer can be reduced, and the integral crystal quality of the InAlGaN electronic barrier layer and the p-type GaN layer is improved so as to improve the integral quality of the light-emitting diode epitaxial wafer.
The InAlGaN electronic barrier layer is grown by adopting the mode, the situation that In atoms In the InAlGaN electronic barrier layer are precipitated and permeate into other layers is less, the distribution of the In atoms In the InAlGaN electronic barrier layer is ensured to be more uniform, the overall growth quality of the InAlGaN electronic barrier layer is more uniform, and the surface flatness of the InAlGaN electronic barrier layer is ensured.
The led epitaxial wafer structure after step S105 is executed can be seen in fig. 2.
Fig. 2 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 2, an led epitaxial wafer according to an embodiment of the present disclosure includes a substrate 1, and an n-type GaN layer 2, a multi-quantum well layer 3, an InAlGaN electronic barrier layer 4, and a p-type GaN layer 5 sequentially stacked on the substrate 1. The multiple quantum well layer 3 includes InGaN well layers 31 and GaN barrier layers 32 alternately stacked.
It should be noted that fig. 2 is provided herein for illustrating a specific possible basic structure of the light emitting diode epitaxial wafer, and in other implementations provided by the present disclosure, the light emitting diode epitaxial wafer may also include other hierarchical structures, which are not limited by the present disclosure.
Fig. 3 is a flowchart of another method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 3, the method for manufacturing an led epitaxial wafer includes:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: and under the hydrogen atmosphere, the time for treating the surface of the substrate is 6-10 min.
For example, the temperature of the reaction chamber may be 1000 to 1200 ℃ and the pressure of the reaction chamber may be 200to 500Torr when processing the surface of the substrate.
In one implementation provided by the present disclosure, the temperature of the reaction chamber may also be 1100 ℃ when processing the substrate, and the time period for processing the surface of the substrate may be 8 min.
Step S201 may further include: and nitriding the surface of the substrate, and paving a layer of nitrogen atoms on the surface of the substrate. Rapid growth of gallium nitride material may be facilitated.
S202: a buffer layer is grown on a substrate.
Optionally, controlling the temperature of the reaction cavity to be 450-600 ℃, and the pressure of the reaction cavity to be 200-500 torr, and growing a GaN three-dimensional nucleation layer; and then raising the temperature of the reaction cavity to 950-1200 ℃ to sequentially grow the GaN filling layer and the non-doped GaN layer. And obtaining the buffer layer with better quality.
S203: and growing an n-type GaN layer on the buffer layer.
Alternatively, the growth temperature of the n-type GaN layer may be 950 to 1200 deg.C, and the growth pressure of the n-type GaN layer may be 200to 500 Torr.
S204: and growing a multi-quantum well layer on the n-type GaN layer.
In step S204, the multiple quantum well layer includes an InGaN well layer and a GaN barrier layer that are alternately grown.
Illustratively, the growth temperature of the InGaN well layer is 720-829 ℃, and the growth temperature of the GaN barrier layer is 850-959 ℃.
When the growth temperature of the InGaN well layer and the growth temperature of the GaN barrier layer are within the above range, the obtained InGaN well layer and the obtained GaN barrier layer have good growth quality, and the interface between the InGaN well layer and the GaN barrier layer is clear.
Optionally, the thickness of the InGaN well layer is 2-4 nm, and the thickness of the GaN barrier layer is 9-20 nm. The obtained MQW layer has good quality.
S205: and alternately introducing reaction gas and an organic metal source into the reaction cavity until the InAlGaN electronic barrier layer is formed on the multi-quantum well layer.
The organic metal source includes a Ga source, an Al source, and an In source, and the reaction gas includes ammonia gas. The description is made on the premise that the organic metal source includes a Ga source, an Al source, and an In source, and the reaction gas includes ammonia gas.
In step S205, a ratio of a time period of introducing the organic metal source into the reaction chamber each time to a time period of introducing the reaction gas into the reaction chamber each time may be 1:2 to 1: 10.
When the ratio of the time length of introducing the organic metal source into the reaction cavity each time to the time length of introducing the reaction gas into the reaction cavity each time is within the above range, In and Al can have enough time to be adsorbed and accumulated on the multi-quantum well layer or the InAlGaN film deposited before, and the reaction gas introduced subsequently can fully react with the In and Al accumulated before after the introduction, so that the InAlGaN film with enough thickness is obtained, and simultaneously, waste caused by introducing excessive reaction gas is avoided, or the subsequent adsorption and accumulation of In and Al is influenced by the excessive reaction gas. The thickness of the finally obtained InAlGaN films is ensured to be uniform, and the finally obtained InAlGaN electronic barrier layer is uniform and has high overall quality.
Optionally, the time for introducing the organic metal source into the reaction cavity each time is 5-15 s.
When the time for introducing the organic metal source into the reaction cavity each time is within the range, the thicknesses of In and Al adsorbed and accumulated on the multiple quantum well layer or the InAlGaN film deposited before are reasonable, the InAlGaN film with proper thickness and good quality can be generated after the InAlGaN film reacts with the reaction gas, and the quality of the finally obtained InAlGaN electronic barrier layer is ensured.
Optionally, the flow rate of the Ga source introduced into the reaction chamber is not changed, and the flow rates of the Al source and the In source introduced into the reaction chamber each time are gradually increased.
The flow of the Ga source introduced into the reaction cavity is not changed, the Ga atoms can be stably adsorbed and accumulated on the multi-quantum well layer or the InAlGaN film deposited before, the flow of the Al source and the In source introduced into the reaction cavity is gradually increased, a potential barrier with height change can be formed In the finally obtained InAlGaN electronic barrier layer, the potential barrier with height change exists In the InAlGaN electronic barrier layer, the current carriers can be more effectively blocked, and more electrons can be reserved In the multi-quantum well layer for reaction luminescence.
For example, the flow rate of the Al source and the In source can be increased In a gradient manner In each time the Al source and the In source are introduced into the reaction cavity. The method can form a low potential barrier or a high potential barrier with larger width, and has better effect of blocking electrons.
For example, the flow rate of the Al source introduced into the reaction chamber at each time can be increased from 40-500 sccm to 100-1250 sccm. The InAlGaN electronic barrier layer with better quality can be obtained.
For example, the flow rate of the In source introduced into the reaction chamber at each time can be from 200-1000 sccm to 500-2500 sccm. The InAlGaN electronic barrier layer with better quality can be obtained.
In other implementations provided by the present disclosure, the flow rates of the Al source and the In source introduced into the reaction chamber each time may also be gradually reduced, which is not limited by the present disclosure.
Optionally, the ratio of the flow rate of the Al source to the flow rate of the In source fed into the reaction chamber each time is 1: 5-1: 20.
When the ratio of the flow rate of the Al source to the flow rate of the In source is In the range, the InAlGaN electronic barrier layer with better quality can be obtained.
Illustratively, the time for introducing the reaction gas into the reaction cavity each time is 10-20 s.
The time length of introducing the reaction gas into the reaction cavity each time is within the range, the reaction gas has enough time to react with the organic metal source, and the InAlGaN film with proper thickness can be obtained.
Optionally, the introducing an organic metal source and a reaction gas into the reaction chamber further includes: the flow of the ammonia source introduced into the reaction chamber at each time is gradually reduced to zero.
The flow of the ammonia source introduced into the reaction cavity is gradually reduced to zero every time, so that the complete reaction of the ammonia gas and the organic metal source can be ensured, and the phenomenon that the residual ammonia gas reacts with the subsequently introduced organic metal source to influence the adsorption process of the organic metal source is avoided.
Illustratively, the flow of the ammonia source which is fed into the reaction cavity in each time is gradually reduced to zero from 40-210L or 80-300L. The crystal quality of the InAlGaN electronic barrier layer obtained finally is better.
Step S205 may further include: and alternately introducing the reaction gas and the organic metal source into the reaction cavity for 5-20 times until the InAlGaN electronic barrier layer is formed on the multi-quantum well layer.
The reaction gas and the organic metal source are alternately introduced into the reaction cavity for 5-20 times, one InAlGaN film is generated each time, 5-20 InAlGaN films are stacked to release certain stress, and the crystal quality of the finally obtained InAlGaN electronic barrier layer formed by stacking the 5-20 InAlGaN films is improved.
Optionally, the thickness of the InAlGaN electron blocking layer is 10-20 nm.
The potential barrier in the InAlGaN electronic barrier layer can sufficiently block electrons, so that the thickness of the InAlGaN electronic barrier layer can be properly reduced, the electronic barrier effect is ensured, and the preparation cost required by the preparation of the light-emitting diode epitaxial wafer is reduced.
Illustratively, the growth temperature of the InAlGaN electronic barrier layer is 850-1000 ℃.
When the growth temperature of the InAlGaN electronic barrier layer is In the above range, the obtained InAlGaN electronic barrier layer has good quality, and In atoms In the InAlGaN electronic barrier layer are not easy to precipitate.
S206: and growing a p-type GaN layer on the InAlGaN electron blocking layer.
Alternatively, the growth pressure of the p-type GaN layer may be 100Torr to 300Torr, and the growth temperature of the p-type GaN layer may be 800 ℃ to 950 ℃.
In one implementation provided by the present disclosure, the growth temperature of the p-type GaN layer may be 900 ℃, and the growth pressure of the p-type GaN layer may be 200 Torr.
S207: and growing a p-type contact layer on the p-type GaN layer.
Alternatively, the growth pressure of the p-type contact layer may be 100Torr to 300Torr, and the growth temperature of the p-type contact layer may be 850 ℃ to 1050 ℃.
In one implementation provided by the present disclosure, the growth temperature of the p-type contact layer may be 950 ℃, and the growth pressure of the p-type contact layer may be 200 Torr.
The method for manufacturing the light emitting diode epitaxial wafer shown in fig. 3 provides a more detailed method for growing the light emitting diode epitaxial wafer compared to the method for manufacturing the light emitting diode shown in fig. 1.
S208: and annealing the light emitting diode epitaxial wafer.
Step S208 may include: adjusting the temperature to 650-850 ℃, and annealing the light-emitting diode epitaxial wafer for 5-15 minutes in a hydrogen atmosphere.
In one implementation provided by the present disclosure, the annealing temperature may be 750 ℃ and the annealing time may be 10 min.
The structure of the led epitaxial wafer after step S208 is completed can be seen in fig. 4.
Fig. 4 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 4, in another implementation manner provided by the present disclosure, the light emitting diode epitaxial wafer may include a substrate 1, and a buffer layer 6, an n-type GaN layer 2, a multi-quantum well layer 3, an InAlGaN electronic barrier layer 4, a p-type GaN layer 5, and a p-type contact layer 7 grown on the substrate 1.
Alternatively, the substrate 1 may be a sapphire substrate 1. Easy to manufacture and obtain.
Illustratively, the buffer layer 6 may include a GaN three-dimensional nucleation layer 61, a GaN fill-up layer 62, and an undoped GaN layer 63, which are sequentially stacked on the substrate 1. The lattice mismatch can be effectively alleviated.
In other implementations provided by the present disclosure, the buffer layer 6 may also be one of aluminum nitride, aluminum gallium nitride, or aluminum indium gallium nitride. The present disclosure is not so limited.
Alternatively, the doping element of the n-type GaN layer 2 may be Si, and the doping concentration of the Si element may be 1 × 1018～1×1019cm-3. The overall quality of the n-type GaN layer 2 is good.
Illustratively, the thickness of the n-type GaN layer 2 may be 1 to 5 μm. The obtained n-type GaN layer 2 has good overall quality.
In one implementation provided by the present disclosure, the thickness of the n-type GaN layer 2 may be 3 μm. The present disclosure is not so limited.
Illustratively, the MQW layer 3 includes a plurality of InGaN well layers 31 and GaN barrier layers 32 alternately stacked, the thickness of the InGaN well layers 31 may be 2-5 nm, and the thickness of the GaN barrier layers 32 may be 8-20 nm.
Illustratively, the overall thickness of the multiple quantum well layer 3 may be 50 to 130nm, and the In molar content may be 13 to 25%.
Optionally, the Al component in the InAlGaN electron blocking layer 4 can be 0.15-0.25. The effect of blocking electrons is better.
Optionally, the thickness of the InAlGaN electron blocking layer 4 can be 20-100 nm. The quality of the obtained InAlGaN electronic barrier layer 4 is better.
Enough cavities can be provided, and the overall cost of the light-emitting diode epitaxial wafer is not too high.
Optionally, the p-type GaN layer 5 can be doped with Mg, and the thickness of the p-type GaN layer 5 can be 100-200 nm.
Illustratively, the thickness of the p-type contact layer 7 may be 10 to 50 nm.
In the epitaxial wafer structure shown in fig. 3, compared with the epitaxial wafer structure shown in fig. 1, a buffer layer 6 is added between the substrate 1 and the n-type GaN layer 2, an InAlGaN electron blocking layer 4 for preventing electron overflow is added between the multi-quantum well layer 3 and the p-type GaN layer 5, and a p-type contact layer 7 is further grown on the p-type GaN layer 5. The obtained epitaxial wafer has better quality and luminous efficiency.
It should be noted that, in other implementations provided by the present disclosure, the light emitting diode epitaxial wafer may also include other hierarchical structures, which is not limited by the present disclosure.
It should be noted that, in the embodiment of the present disclosure, a VeecoK465iorC4orrbmoc (metal organic chemical vapor deposition) apparatus is used to implement a growth method of a light emitting diode. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, silane (SiH4) as an N-type dopant, trimethyl aluminum (TMAl) as an aluminum source, and magnesium dicylocene (CP)2Mg) as a P-type dopant.
Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (6)

1. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer comprises GaN barrier layers and InGaN well layers which are alternately grown;
alternately introducing reaction gas and an organic metal source into the reaction cavity until an InAlGaN electronic barrier layer is formed on the multi-quantum well layer, wherein the reaction gas comprises an ammonia source, the organic metal source comprises a Ga source, an Al source and an In source, the ratio of the time length of introducing the organic metal source into the reaction cavity each time to the time length of introducing the reaction gas into the reaction cavity each time is 1: 2-1: 10,
the flow of the Ga source introduced into the reaction cavity is unchanged, the flow of the Al source and the flow of the In source introduced into the reaction cavity each time are gradually increased, the flow of the ammonia source introduced into the reaction cavity each time is gradually reduced to zero, the flow of the Al source introduced into the reaction cavity each time can be increased to 100-1250 sccm from 40-500 sccm, the flow of the In source introduced into the reaction cavity each time can be from 200-1000 sccm to 500-2500 sccm, and the flow of the ammonia source introduced into the reaction cavity each time is gradually reduced to zero from 40-210L or 80-300L;
and growing a p-type GaN layer on the InAlGaN electronic barrier layer.
2. The method for preparing the light-emitting diode epitaxial wafer according to claim 1, wherein the time for introducing the organic metal source into the reaction cavity each time is 5-15 s.
3. The method for preparing the light-emitting diode epitaxial wafer according to claim 2, wherein the time for introducing the reaction gas into the reaction chamber each time is 10-20 s.
4. The method for preparing an LED epitaxial wafer according to any one of claims 1 to 3, wherein the step of introducing an organic metal source and a reaction gas into the reaction chamber comprises:
and alternately introducing reaction gas and an organic metal source into the reaction cavity for 5-20 times until the InAlGaN electronic barrier layer is formed on the multi-quantum well layer.
5. The method for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein,
the growth temperature of the InAlGaN electronic barrier layer is 850-1000 ℃.
6. The method for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the InAlGaN electron blocking layer has a thickness of 10 to 20 nm.
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