CN109860340B - Growth method of light-emitting diode epitaxial wafer - Google Patents
Growth method of light-emitting diode epitaxial wafer Download PDFInfo
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Abstract
The invention discloses a growth method of a light-emitting diode epitaxial wafer, and belongs to the technical field of semiconductors. The growth method comprises the following steps: placing a substrate into a reaction chamber; growing a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence; the growth process of the three-dimensional nucleation layer comprises a plurality of growth stages which appear in sequence, each growth stage comprises a low-temperature stage and a high-temperature stage which appears after the low-temperature stage, the temperature in the reaction chamber of the high-temperature stage is higher than the temperature in the reaction chamber of the low-temperature stage adjacent to the high-temperature stage, the temperature in the reaction chamber of each high-temperature stage rises one by one according to the appearance sequence of each high-temperature stage, and the temperature in the reaction chamber of each low-temperature stage rises one by one according to the appearance sequence of each low-temperature stage. The invention can improve the luminous efficiency of the LED.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a growth method of a light-emitting diode epitaxial wafer.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. As a novel efficient, environment-friendly and green solid-state illumination light source, LEDs are being rapidly and widely applied in the fields of traffic signal lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlight sources and the like. Therefore, improvement of light emitting efficiency is an ongoing goal of LEDs.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional LED epitaxial wafer comprises a substrate, a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the low-temperature buffer layer, the three-dimensional nucleating layer, the two-dimensional recovery layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate. The active layer is used for carrying out radiation recombination luminescence of electrons and holes, the N-type semiconductor layer is used for providing electrons for carrying out recombination luminescence, and the P-type semiconductor layer is used for providing holes for carrying out recombination luminescence. The active layer, the N-type semiconductor layer and the P-type semiconductor layer constitute a basic structure of the LED.
The substrate is used for providing a growth surface for epitaxial materials, and the low-temperature buffer layer is used for providing nucleation centers for the growth of the epitaxial materials. Since the substrate material and the epitaxial material are heterogeneous materials, a large lattice mismatch exists between the substrate and the N-type semiconductor layer. Stress and defects generated by lattice mismatch are more introduced into the epitaxial material and are continuously accumulated in the epitaxial growth process, so that the crystal quality of the active layer is reduced, and the luminous efficiency of the LED is finally influenced. In order to alleviate the adverse effect of stress and defects generated by lattice mismatch on the crystal quality of an active layer, the longitudinal growth of gallium nitride is generally carried out on a low-temperature buffer layer to form a plurality of mutually independent three-dimensional island-shaped structures, namely three-dimensional nucleation layers; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure, namely a two-dimensional recovery layer; the growth process of the three-dimensional nucleation layer and the two-dimensional recovery layer is utilized to release the stress generated by lattice mismatch, and simultaneously, the defects generated by lattice mismatch are interacted and annihilated.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
generally, the higher the growth temperature, the better the growth quality of gallium nitride. Therefore, the higher the growth temperature of the three-dimensional nucleation layer is, the better the crystal quality of the epitaxial material such as the active layer and the like which are grown subsequently is, and the higher the light emitting efficiency of the LED is. However, if the growth temperature of the three-dimensional nucleation layer is too high, the low-temperature buffer layer can be damaged, and the growth of the subsequent epitaxial material is influenced. Therefore, the growth temperature of the three-dimensional nucleation layer is limited, and the effect on the stress and the defects generated by the lattice mismatch is limited, so that the stress and the defects generated by the lattice mismatch extend into the active layer, the active layer has larger stress, the crystal quality of the active layer is poor, the compound light emission of electrons and holes in the active layer is influenced, and the light emitting efficiency of the LED is low.
Disclosure of Invention
The embodiment of the invention provides a growth method of a light-emitting diode epitaxial wafer, which can solve the problem that the light-emitting efficiency of an LED is limited by low crystal quality and large stress in the prior art. The technical scheme is as follows:
the embodiment of the invention provides a growth method of a light-emitting diode epitaxial wafer, which comprises the following steps:
placing a substrate into a reaction chamber;
growing a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the growth process of the three-dimensional nucleation layer comprises a plurality of growth stages which appear in sequence, each growth stage comprises a low-temperature stage and a high-temperature stage which appears after the low-temperature stage, the temperature in the reaction chamber of the high-temperature stage is higher than the temperature in the reaction chamber of the low-temperature stage adjacent to the high-temperature stage, the temperature in the reaction chamber of each high-temperature stage rises one by one according to the appearance sequence of each high-temperature stage, and the temperature in the reaction chamber of each low-temperature stage rises one by one according to the appearance sequence of each low-temperature stage.
Optionally, the temperature in the low temperature stage reaction chamber occurring first is 900 ℃ to 960 ℃, and the temperature in the high temperature stage reaction chamber occurring last is 1050 ℃ to 1100 ℃.
Optionally, the temperature difference between the two adjacent high-temperature stage reaction chambers is 20-60 ℃, and the temperature difference between the two adjacent low-temperature stage reaction chambers is 20-60 ℃.
Optionally, the temperature in the high-temperature stage reaction chamber is 20 to 60 ℃ higher than the temperature in the low-temperature stage reaction chamber adjacent to the high-temperature stage.
Optionally, the pressure in the high temperature stage reaction chamber is greater than the pressure in the low temperature stage reaction chamber adjacent to the high temperature stage.
Preferably, the pressure in each high-temperature stage reaction chamber is increased one by one according to the appearance sequence of each high-temperature stage, and the pressure in each low-temperature stage reaction chamber is increased one by one according to the appearance sequence of each low-temperature stage.
Optionally, the rotation speed of the high-temperature stage substrate is greater than the rotation speed of the low-temperature stage substrate adjacent to the high-temperature stage.
Preferably, the rotating speed of each high-temperature stage substrate is increased one by one according to the appearance sequence of each high-temperature stage, and the rotating speed of each low-temperature stage substrate is increased one by one according to the appearance sequence of each low-temperature stage.
Optionally, in the low-temperature stage, an aluminum source and a nitrogen source are introduced into the reaction chamber, and then a gallium source and a nitrogen source are introduced into the reaction chamber.
Preferably, the flow rate of the aluminum source introduced into the reaction chamber in each low-temperature stage is gradually reduced according to the sequence of the low-temperature stages.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the growth process of the three-dimensional nucleation layer is divided into a plurality of growth stages, each growth stage comprises a low-temperature stage and a high-temperature stage appearing after the low-temperature stage, so that the three-dimensional nucleation layer grows in an environment with alternately appearing low temperature and high temperature, stress and defects generated by lattice mismatch can be relieved, the warping of an epitaxial wafer is improved, meanwhile, the formation of a light-emitting center in an active layer is facilitated, and the crystal quality of the active layer is improved. The temperature of the reaction chambers in the high-temperature stage and the low-temperature stage is increased one by one according to the appearance sequence, the temperature for starting the growth of the three-dimensional nucleation layer is lower, the low-temperature buffer layer cannot be damaged, and the growth of epitaxial materials is facilitated; meanwhile, the temperature of the subsequent growth of the three-dimensional nucleation layer is gradually increased, the crystal quality of the three-dimensional nucleation layer can be improved by utilizing high-temperature growth, the crystal quality of the active layer is further improved, and the luminous efficiency of the LED is finally improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
FIG. 2 is a schematic representation of the temperature within the reaction chamber during growth of a three-dimensional nucleation layer provided by an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a light emitting diode epitaxial wafer formed by the growth method according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a growth method of a light-emitting diode epitaxial wafer. Fig. 1 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 1, the growing method includes:
step 101: the substrate is placed into a reaction chamber.
Specifically, sapphire may be used as the material of the substrate. Further, the epitaxial material may be grown on the [0001] plane of the sapphire.
Optionally, after step 101, the growing method may further include:
and processing the substrate at high temperature for 5-6 min under the hydrogen atmosphere.
Wherein the temperature in the reaction chamber is 1000-1100 ℃, and the pressure in the reaction chamber is 200-500 torr.
Through the cleaning of the substrate in the steps, impurities on the surface of the substrate are prevented from being mixed into the epitaxial material which grows subsequently, and the growth quality of the epitaxial wafer is improved.
Step 102: and a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on the substrate.
Fig. 2 is a schematic diagram of the temperature in the reaction chamber during the growth of a three-dimensional nucleation layer according to an embodiment of the present invention. Referring to fig. 2, in the present embodiment, the growth process of the three-dimensional nucleation layer includes a plurality of growth phases a that occur in sequence, each growth phase a including a low temperature phase B and a high temperature phase C that occurs after the low temperature phase B. The temperature in the reaction chamber of the high-temperature stage C is higher than that in the reaction chamber of the low-temperature stage B adjacent to the high-temperature stage C, the temperature in the reaction chamber of each high-temperature stage C is increased one by one according to the sequence of the high-temperature stages C, and the temperature in the reaction chamber of each low-temperature stage B is increased one by one according to the sequence of the low-temperature stages B.
For example, the three-dimensional nucleation layer growth process of fig. 2 includes three growth phases a1, a2, and A3 in sequence; growth phase a1 includes a low temperature phase B1 and a high temperature phase C1 occurring in sequence, growth phase a2 includes a low temperature phase B2 and a high temperature phase C2 occurring in sequence, and growth phase A3 includes a low temperature phase B3 and a high temperature phase C3 occurring in sequence. The temperature in the high temperature stage C1 reactor was higher than the temperature in the low temperature stage B1 reactor and the temperature in the low temperature stage B2 reactor, the temperature in the high temperature stage C2 reactor was higher than the temperature in the low temperature stage B2 reactor and the temperature in the low temperature stage B3 reactor, and the temperature in the high temperature stage C3 reactor was higher than the temperature in the low temperature stage B3 reactor. The temperature in the high-temperature stage C1 reaction chamber, the temperature in the high-temperature stage C2 reaction chamber and the temperature in the high-temperature stage C3 reaction chamber are increased one by one; the temperature in the low temperature stage B1 reaction chamber, the temperature in the low temperature stage B2 reaction chamber, and the temperature in the low temperature stage B3 reaction chamber were increased one by one.
According to the embodiment of the invention, the growth process of the three-dimensional nucleation layer is divided into a plurality of growth stages, and each growth stage comprises a low-temperature stage and a high-temperature stage appearing after the low-temperature stage, so that the three-dimensional nucleation layer grows in an environment with alternately appearing low temperature and high temperature, stress and defects generated by lattice mismatch can be relieved, the warping of an epitaxial wafer is improved, meanwhile, the formation of a light-emitting center in an active layer is facilitated, and the crystal quality of the active layer is improved. The temperature of the reaction chambers in the high-temperature stage and the low-temperature stage is increased one by one according to the appearance sequence, the temperature for starting the growth of the three-dimensional nucleation layer is lower, the low-temperature buffer layer cannot be damaged, and the growth of epitaxial materials is facilitated; meanwhile, the temperature of the subsequent growth of the three-dimensional nucleation layer is gradually increased, the crystal quality of the three-dimensional nucleation layer can be improved by utilizing high-temperature growth, the crystal quality of the active layer is further improved, and the luminous efficiency of the LED is finally improved.
Alternatively, the temperature within the first occurring low temperature stage reaction chamber may be from 900 ℃ to 960 ℃, and the temperature within the last occurring high temperature stage reaction chamber may be from 1050 ℃ to 1100 ℃. Taking fig. 2 as an example, the temperature in the low temperature stage B1 chamber may be 930 ℃ and the temperature in the high temperature stage C3 chamber may be 1080 ℃.
By limiting the lowest temperature and the highest temperature in the reaction chamber in the growth process of the three-dimensional nucleation layer, the growth of the adjacent low-temperature buffer layer and the two-dimensional recovery layer of the three-dimensional nucleation layer is considered under the condition of considering the growth quality of the three-dimensional nucleation layer, so that the overall crystal quality of the epitaxial wafer is optimal. Specifically, if the temperature in the reaction chamber at the first low-temperature stage is lower than 900 ℃ or the temperature in the reaction chamber at the last high-temperature stage is lower than 1050 ℃, the crystal quality of the three-dimensional nucleation layer may be affected due to the lower growth temperature of the whole three-dimensional nucleation layer, which is not favorable for the recombination luminescence of electrons and holes in the active layer and reduces the luminous efficiency of the LED; if the temperature in the reaction chamber at the first low-temperature stage is higher than 960 ℃, the low-temperature buffer layer may be damaged due to the high growth temperature of the part of the three-dimensional nucleation layer close to the low-temperature buffer layer, which affects the growth of the subsequent epitaxial material; if the temperature in the reaction chamber during the last occurring high temperature phase is higher than 1100 deg.c, the growth of the two-dimensional recovery layer may be affected due to the higher growth temperature of the part of the three-dimensional nucleation layer close to the two-dimensional recovery layer.
Preferably, the temperature in the first occurring low temperature stage reaction chamber may be from 910 ℃ to 950 ℃ and the temperature in the last occurring high temperature stage reaction chamber may be from 1060 ℃ to 1090 ℃.
Alternatively, the temperature difference between the two adjacent high-temperature stage reaction chambers can be 20-60 ℃, and the temperature difference between the two adjacent low-temperature stage reaction chambers can be 20-60 ℃. Taking fig. 2 as an example, the temperature in the low temperature stage B1 chamber may be 930 ℃, the temperature in the low temperature stage B2 chamber may be 970 ℃, and the temperature in the low temperature stage B3 chamber may be 1010 ℃.
By limiting the rising amplitude of the temperature in the reaction chamber in the high-temperature stage and the low-temperature stage, under the condition that the crystal quality of the three-dimensional nucleation layer is improved by considering the temperature rise, the negative influence on the adjacent low-temperature buffer layer or the two-dimensional recovery layer is avoided as much as possible. Specifically, if the temperature difference between the two adjacent high-temperature stage reaction chambers is less than 20 ℃ or the temperature difference between the two adjacent low-temperature stage reaction chambers is less than 20 ℃, the crystal quality of the three-dimensional nucleation layer may not be effectively improved due to the insignificant growth temperature change of the three-dimensional nucleation layer, and finally the light emitting efficiency of the LED is low; if the temperature difference between the two adjacent high-temperature stage reaction chambers is more than 60 ℃, or the temperature difference between the two adjacent low-temperature stage reaction chambers is more than 60 ℃, the low-temperature buffer layer or the two-dimensional recovery layer may be affected due to the large growth temperature change of the three-dimensional nucleation layer.
Preferably, the temperature difference between the two adjacent high-temperature stage reaction chambers can be 30-50 ℃, and the temperature difference between the two adjacent low-temperature stage reaction chambers can be 30-50 ℃.
Further, the number of growth stages can be less than 8, and the growth time of the three-dimensional nucleation layer is prevented from being too long to affect the low-temperature buffer layer and the two-dimensional recovery layer.
Preferably, the number of growth stages may be 4 to 6.
Alternatively, the temperature in the high temperature stage reaction chamber may be 20 ℃ to 60 ℃ higher than the temperature in the low temperature stage reaction chamber adjacent to the high temperature stage. If the temperature in the reaction chamber at the high temperature stage is higher than the temperature in the reaction chamber at the low temperature stage by less than 20 ℃, stress and defects generated by lattice mismatch can not be effectively relieved probably because the difference between the temperature in the reaction chamber at the high temperature stage and the temperature in the reaction chamber at the low temperature stage is small, and finally the effect of improving the luminous efficiency of the LED can not be achieved; if the temperature in the high-temperature stage reaction chamber is higher than the temperature in the low-temperature stage reaction chamber by more than 60 ℃, the temperature difference between the temperature in the high-temperature stage reaction chamber and the temperature in the low-temperature stage reaction chamber may affect the low-temperature buffer layer and the two-dimensional recovery layer.
Preferably, the temperature in the reaction chamber of the high temperature stage may be 30 to 50 ℃ higher than the temperature in the reaction chamber of the low temperature stage adjacent to the high temperature stage.
Optionally, the pressure in the reaction chamber at the high-temperature stage may be greater than the pressure in the reaction chamber at the low-temperature stage adjacent to the high-temperature stage, so that the three-dimensional nucleation layer grows in an environment where low pressure and high pressure alternately occur, stress and defects generated by lattice mismatch can be further alleviated, warpage of the epitaxial wafer is improved, formation of a light-emitting center in the active layer is facilitated, crystal quality of the active layer is improved, and light-emitting efficiency of the LED is finally improved.
Preferably, the pressure in the reaction chamber in each high-temperature stage can be increased one by one according to the sequence of the high-temperature stages, and the pressure in the reaction chamber in each low-temperature stage can be increased one by one according to the sequence of the low-temperature stages, so that the change mode of the pressure in the reaction chamber in the growth process of the three-dimensional nucleation layer is consistent with the change mode of the temperature in the reaction chamber, the crystal quality of the three-dimensional nucleation layer is favorably improved, and the luminous efficiency of the LED is optimal.
Further, the pressure in the reaction chamber during the growth phase may be 200torr to 600 torr. If the pressure in the reaction chamber is less than 200torr in the growth phase, the growth of the three-dimensional nucleation layer may be not facilitated due to the low pressure in the reaction chamber; if the pressure in the reaction chamber during the growth phase is greater than 600torr, the density of the three-dimensional nucleation layer may be low due to the high pressure in the reaction chamber, which is not favorable for the growth of the two-dimensional fill-and-level layer.
Preferably, the pressure in the reaction chamber during the growth phase may be 300torr to 500 torr.
Optionally, the rotation speed of the substrate at the high-temperature stage may be greater than that of the substrate at the adjacent low-temperature stage at the high-temperature stage, so that the growth rate of the three-dimensional nucleation layer is fast and slow, which is beneficial to relieving stress and defects generated by lattice mismatch, improving the warpage of the epitaxial wafer, and simultaneously, facilitating the formation of a light-emitting center in the active layer, improving the crystal quality of the active layer, and finally improving the light-emitting efficiency of the LED.
Preferably, the rotating speed of the substrate in each high-temperature stage can be increased one by one according to the sequence of the high-temperature stages, and the rotating speed of the substrate in each low-temperature stage can be increased one by one according to the sequence of the low-temperature stages, so that the change mode of the growth rate of the three-dimensional nucleation layer is consistent with the change mode of the temperature in the reaction chamber, the crystal quality of the three-dimensional nucleation layer is improved, and the luminous efficiency of the LED is optimal.
Further, the substrate may rotate at a speed of 600 RPM (RPM) to 1200 RPM during the growth phase. If the rotating speed of the substrate is less than 600 revolutions per minute in the growth stage, the growth efficiency of the three-dimensional nucleation layer can be influenced due to the slow rotating speed of the substrate; if the rotation speed of the substrate in the growth phase is greater than 1200 rpm, a vortex may be generated due to the fast rotation speed of the substrate in the growth phase, the growth atmosphere is unstable, and the growth effect is poor.
Preferably, the rotation speed of the substrate in the growth stage may be 800 rpm to 1000 rpm.
Optionally, in the low-temperature stage, an aluminum source and a nitrogen source may be introduced into the reaction chamber, and then a gallium source and a nitrogen source may be introduced into the reaction chamber. An aluminum source and nitrogen are introduced to form aluminum nitride, the barrier potential of the aluminum nitride is high, defects can be effectively prevented from extending upwards, and the crystal quality of the three-dimensional nucleation layer is further improved; and then introducing a gallium source and a nitrogen source to form gallium nitride, maintaining the main structure of the three-dimensional nucleation layer unchanged, and avoiding the cracking caused by more doped impurities such as aluminum and the like in the three-dimensional nucleation layer.
Furthermore, the time length of introducing the aluminum source into the reaction chamber in the low-temperature stage can be 1/5-3/5 of the time length of introducing the gallium source into the reaction chamber in the low-temperature stage.
Specifically, the time period for introducing the aluminum source into the reaction chamber in the low-temperature stage may be 0.5min to 1.5min, and the time period for introducing the gallium source into the reaction chamber in the low-temperature stage may be 1min to 3 min.
Preferably, the flow rate of the aluminum source introduced into the reaction chamber in each low-temperature stage can be reduced one by one according to the sequence of the appearance of each low-temperature stage. With the barrier effect of the aluminum nitride on the defect extension, the defects of the subsequent extension are less and less, the flow of the introduced aluminum source is correspondingly reduced, the defect extension is effectively blocked, aluminum doped in the three-dimensional nucleation layer can be reduced as far as possible, and the growth quality of the three-dimensional nucleation layer is improved.
Furthermore, the flow rate of the aluminum source introduced into the reaction chamber in two adjacent low-temperature stages can be different by 1-5 times. Taking fig. 2 as an example, the flow rate of the aluminum source introduced into the reaction chamber in the low temperature stage B1 may be X, the flow rate of the aluminum source introduced into the reaction chamber in the low temperature stage B2 may be X/2, and the flow rate of the aluminum source introduced into the reaction chamber in the low temperature stage B3 may be X/4, where X is greater than or equal to 20sccm and less than or equal to 50 sccm.
Specifically, the doping concentration of aluminum element in the aluminum nitride formed in the low temperature stage may be 2.5 × 1019/cm3～1020/cm3. Also as an example in FIG. 2, the doping concentration of aluminum in the aluminum nitride formed in the low temperature stage B1 may be 1020/cm3The doping concentration of aluminum element in the aluminum nitride formed in the low-temperature stage B2 may be 5 x 1019/cm3The doping concentration of the aluminum element in the aluminum nitride formed in the low-temperature stage B3 may be 2.5 x 1019/cm3。
In practical application, the gallium source and the nitrogen source can be continuously introduced into the reaction chamber at the low-temperature stage.
Specifically, the duration of the low temperature stage may be 1min to 5 min.
Furthermore, a gallium source and a nitrogen source can be continuously introduced into the reaction chamber during the high-temperature stage.
Specifically, the duration of the high temperature stage may be 1min to 5 min.
Specifically, the thickness of the three-dimensional nucleation layer can be 50min to 100 nm.
Fig. 3 is a schematic structural diagram of a light emitting diode epitaxial wafer formed by the growth method according to the embodiment of the invention. Where 10 denotes a substrate, 21 denotes a low-temperature buffer layer, 22 denotes a three-dimensional nucleation layer, 23 denotes a two-dimensional recovery layer, 31 denotes an N-type semiconductor layer, 32 denotes an active layer, and 33 denotes a P-type semiconductor layer. Referring to fig. 3, a low-temperature buffer layer 21, a three-dimensional nucleation layer 22, a two-dimensional recovery layer 23, an N-type semiconductor layer 31, an active layer 32, and a P-type semiconductor layer 33 are sequentially stacked on a substrate 10. Wherein the three-dimensional nucleation layer 22 comprises a plurality of mutually independent three-dimensional island-shaped structures, and the two-dimensional recovery layer 23 is grown on all the three-dimensional island-shaped structures and among the three-dimensional island-shaped structures to fill and level the depressions among the three-dimensional island-shaped structures.
In particular implementations, this step 102 may include:
firstly, growing a low-temperature buffer layer on a substrate;
secondly, growing a three-dimensional nucleating layer on the low-temperature buffer layer;
thirdly, growing a two-dimensional recovery layer on the three-dimensional nucleation layer;
fourthly, growing an N-type semiconductor layer on the two-dimensional recovery layer;
fifthly, growing an active layer on the N-type semiconductor layer;
and a sixth step of growing a P-type semiconductor layer on the active layer.
In this embodiment, a Veeco K465i or C4 Metal Organic compound Chemical Vapor Deposition (MOCVD) apparatus is used to realize the growth of the epitaxial material. Specifically, high purity hydrogen (H) gas is used2) High purity nitrogen (N)2) And one of the mixed gases of high-purity hydrogen and high-purity nitrogen as carrier gas, high-purity ammonia (NH)3) As the nitrogen source, trimethyl gallium (english abbreviation: TMGa) and triethylgallium (TEGa) as gallium sources, trimethylindium (TMAl) as indium sources, trimethylaluminum (TMAl) as aluminum sources, Silane (SiH)4) As N-type dopant, magnesium dicocene (CP)2Mg) as a P-type dopant.
Specifically, the material of the low-temperature buffer layer can adopt undoped gallium nitride or aluminum nitride; the low-temperature buffer layer may have a thickness of 15nm to 30 nm.
Further, the first step may include:
controlling the temperature in the reaction chamber to be 530-560 ℃, and the pressure in the reaction chamber to be 200-500 torr, and growing a low-temperature buffer layer on the substrate.
In particular, the material of the two-dimensional recovery layer may be undoped gallium nitride; the thickness of the two-dimensional healing layer may be between 2 μm and 3.5 μm.
Further, the third step may include:
controlling the temperature in the reaction chamber to be 1000-1100 ℃, and the pressure in the reaction chamber to be 200-600 torr, and growing a two-dimensional recovery layer on the three-dimensional nucleation layer.
Specifically, the material of the N-type semiconductor may employ N-type doped (e.g., silicon) gallium nitride; the thickness of the N-type semiconductor layer may be 2 to 3 μm.
Further, the fourth step may include:
controlling the temperature in the reaction chamber to be 1000-1100 ℃, and the pressure in the reaction chamber to be 200-300 torr, and growing the N-type semiconductor layer on the two-dimensional recovery layer.
Optionally, before the fourth step, the growing method may further include:
and growing a stress release layer on the two-dimensional recovery layer.
Accordingly, an N-type semiconductor layer is grown on the stress relieving layer.
Specifically, the stress release layer may include a plurality of first sublayers and a plurality of second sublayers, which are alternately stacked; the first sublayer can be made of undoped indium gallium nitride, and the second sublayer can be made of undoped gallium nitride; the thickness of the first sub-layer can be 1 nm-3 nm, and the thickness of the second sub-layer can be 40 nm-50 nm; the number of the second sublayers is equal to that of the first sublayers, and the number of the first sublayers can be 2 to 20.
Further, growing a stress relief layer on the two-dimensional restoration layer may include:
controlling the temperature in the reaction chamber to be 800-1100 ℃, and the pressure in the reaction chamber to be 100-500 torr, and growing a stress release layer on the two-dimensional recovery layer.
Specifically, the active layer may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the material of the quantum well can adopt undoped indium gallium nitride, and the material of the quantum barrier can adopt undoped gallium nitride; the thickness of the quantum well can be 2 nm-3 nm, and the thickness of the quantum barrier can be 8 nm-11 nm; the number of quantum barriers is equal to that of quantum wells, and the number of quantum wells can be 11-13; the thickness of the active layer may be 130nm to 160 nm.
Further, the fifth step may include:
controlling the pressure in the reaction chamber to be 200torr, and growing an active layer on the N-type semiconductor layer; wherein the temperature in the reaction chamber is 760-780 ℃ when the quantum well grows, and the temperature in the reaction chamber is 860-890 ℃ when the quantum barrier grows.
Specifically, the P-type semiconductor layer may be made of P-type doped (e.g., magnesium) gallium nitride; the thickness of the P-type semiconductor layer may be 50nm to 80 nm.
Further, the sixth step may include:
controlling the temperature in the reaction chamber to be 940-980 ℃ and the pressure in the reaction chamber to be 200-600 torr, and growing the P-type semiconductor layer on the active layer.
Optionally, before the sixth step, the growing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, the electron blocking layer may be made of P-type doped aluminum gallium nitride, such as AlyGa1-yN, y is more than or equal to 0.15 and less than or equal to 0.25; the thickness of the electron blocking layer may be 30nm to 50 nm.
Further, growing an electron blocking layer on the active layer may include:
controlling the temperature in the reaction chamber to be 930-970 ℃ and the pressure in the reaction chamber to be 100torr, and growing the electron blocking layer on the active layer.
Preferably, before growing the electron blocking layer on the active layer, the growth method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, the material of the low-temperature P-type layer can adopt P-type doped gallium nitride; the thickness of the low-temperature P-type layer may be 20nm to 60 nm.
Further, growing the low temperature P-type layer on the active layer may include:
controlling the temperature in the reaction chamber to be 750-800 ℃, and the pressure in the reaction chamber to be 100-600 torr, and growing a low-temperature P-type layer on the active layer.
Optionally, after the sixth step, the growing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, the contact layer may adopt P-type doped indium gallium nitride or gallium nitride; the thickness of the contact layer may be 10nm to 30 nm.
Further, growing a contact layer on the P-type semiconductor layer may include:
controlling the temperature in the reaction chamber to be 650-750 ℃, and the pressure in the reaction chamber to be 100-600 torr, and growing a contact layer on the P-type semiconductor layer.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A growth method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
placing a substrate into a reaction chamber;
growing a low-temperature buffer layer, a three-dimensional nucleating layer, a two-dimensional recovery layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
the growth process of the three-dimensional nucleation layer comprises a plurality of growth stages which appear in sequence, each growth stage comprises a low-temperature stage and a high-temperature stage which appears after the low-temperature stage, the temperature in the reaction chamber of the high-temperature stage is higher than the temperature in the reaction chamber of the low-temperature stage adjacent to the high-temperature stage, the temperature in the reaction chamber of each high-temperature stage rises one by one according to the appearance sequence of each high-temperature stage, and the temperature in the reaction chamber of each low-temperature stage rises one by one according to the appearance sequence of each low-temperature stage.
2. The growth method of claim 1, wherein the temperature within the low temperature stage reaction chamber that occurs first is 900 ℃ to 960 ℃, and the temperature within the high temperature stage reaction chamber that occurs last is 1050 ℃ to 1100 ℃.
3. The growing method according to claim 1 or 2, wherein the temperature difference between two adjacent high temperature stage reaction chambers is 20 ℃ to 60 ℃ and the temperature difference between two adjacent low temperature stage reaction chambers is 20 ℃ to 60 ℃.
4. The growth method according to claim 1 or 2, wherein the temperature in the high-temperature stage reaction chamber is 20 to 60 ℃ higher than the temperature in the low-temperature stage reaction chamber adjacent to the high-temperature stage.
5. The growth method according to claim 1 or 2, wherein a pressure in the high-temperature stage reaction chamber is greater than a pressure in the low-temperature stage reaction chamber adjacent to the high-temperature stage.
6. The growth method according to claim 5, wherein the pressure in each of the high-temperature stage reaction chambers increases one by one in the order in which each of the high-temperature stages occurs, and the pressure in each of the low-temperature stage reaction chambers increases one by one in the order in which each of the low-temperature stages occurs.
7. The growth method according to claim 1 or 2, wherein the rotation speed of the high-temperature stage substrate is greater than the rotation speed of the low-temperature stage substrate adjacent to the high-temperature stage.
8. The growth method according to claim 7, wherein the rotation speed of each high-temperature stage substrate is increased one by one according to the appearance sequence of each high-temperature stage, and the rotation speed of each low-temperature stage substrate is increased one by one according to the appearance sequence of each low-temperature stage.
9. The growth method according to claim 1 or 2, wherein in the low-temperature stage, an aluminum source and a nitrogen source are introduced into the reaction chamber, and then a gallium source and a nitrogen source are introduced into the reaction chamber.
10. The growing method according to claim 9, wherein the flow rate of the aluminum source introduced into the reaction chamber in each of the low-temperature stages is reduced one by one in the order in which the low-temperature stages occur.
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