CN103337573A - Epitaxial wafer of semiconductor light emitting diode and manufacturing method of epitaxial wafer - Google Patents
Epitaxial wafer of semiconductor light emitting diode and manufacturing method of epitaxial wafer Download PDFInfo
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Abstract
The invention discloses an epitaxial wafer of a semiconductor light emitting diode, and relates to the technical field of semiconductors. The epitaxial wafer comprises a substrate, and a low-temperature buffer layer, a high-temperature buffer layer, a compound N-type layer, a compound multi-quantum well layer and a compound P-type layer which grow on the substrate sequentially, wherein the compound multi-quantum well layer comprises a first multi-quantum well layer and a second multi-quantum well layer growing on the first multi-quantum well layer; the first multi-quantum well layer is in a multi-cycle structure; each cycle comprises a potential well layer and a barrier layer growing on the potential well layer; and the barrier layer of each cycle of the first multi-quantum well layer is doped with Si. Si doped in the barrier layers of the first multi-quantum well layer of the epitaxial wafer can inhibit spiral island structures from forming on the surfaces of the barrier layers, so that the surface characteristics of the barrier layers are good, and the crystalline quality is improved. In addition, the invention discloses a manufacturing method of the epitaxial wafer of the semiconductor light emitting diode.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of epitaxial wafer of semiconductor light-emitting-diode and manufacture method thereof.
Background technology
Be the III group-III nitride of representative and their alloy indium gallium nitrogen (InGaN) with gallium nitride (GaN), indium nitride (InN), aluminium nitride (AlN), because of its good physics and chemical property, be widely used in light-emitting diode.
LED epitaxial slice comprises substrate and the low temperature buffer layer, high temperature buffer layer, compound N-type layer, compound multiple quantum well layer and the compound P type layer that stack gradually on substrate.Wherein compound multiple quantum well layer comprises first multiple quantum well layer and second multiple quantum well layer that is layered on first multiple quantum well layer, this first multiple quantum well layer and this second multiple quantum well layer are formed by alternately laminated potential well layer (InGaN layer) and barrier layer (GaN layer), wherein, first multiple quantum well layer works to discharge stress, make that the crystal mass of second multiple quantum well layer is better, the luminous efficiency height.When making first multiple quantum well layer, because potential well layer needs low-temperature epitaxy, and barrier layer needs high growth temperature, therefore among the process from the low-temperature transformation to high temperature, can cause potential well layer to decompose.Someone proposes growing gallium nitride under the low temperature (GaN) cap rock protection potential well layer, and then improves the growth temperature of barrier layer.
In realizing process of the present invention, the inventor finds that there is following problem at least in prior art:
When making first multiple quantum well layer, the growth temperature of the barrier layer that the method by the growing GaN cap rock improves, still be lower than the required temperature of normal growth barrier layer, make when barrier layer is grown at low temperatures, the surface forms the spiral island structure, cause the surface characteristic of barrier layer of first multiple quantum well layer poor, so cause the crystal mass of second multiple quantum well layer poor, luminous efficiency is low.
Summary of the invention
The epitaxial wafer and the manufacture method thereof that the purpose of this invention is to provide a kind of semiconductor light-emitting-diode, can avoid the surface of the barrier layer of first multiple quantum well layer to form the spiral island structure, improve the surface characteristic of the barrier layer of first multiple quantum well layer, guarantee crystal mass and the luminous efficiency of second multiple quantum well layer.
To achieve these goals, on the one hand, the embodiment of the invention provides a kind of epitaxial wafer of semiconductor light-emitting-diode, comprise substrate and the low temperature buffer layer of growing at described substrate successively, high temperature buffer layer, compound N-type layer, compound multiple quantum well layer and compound P type layer, described compound multiple quantum well layer comprises first multiple quantum well layer and second multiple quantum well layer of growing at described first multiple quantum well layer, described first multiple quantum well layer is the multicycle structure, each cycle comprises potential well layer and the barrier layer of growing at described potential well layer, and the barrier layer in described first each cycle of multiple quantum well layer is doped with Si respectively.
In one embodiment of the invention, in described first multiple quantum well layer, described Si is entrained in the position away from described potential well layer of described barrier layer.
In another embodiment of the present invention, 10%～90% of described barrier layer thickness is doped with described Si.
Preferably, effective doping content of described Si is 5 * 10
16～1 * 10
19/ cm
3
Preferably, the thickness of described barrier layer is 10～15nm.
In an embodiment more of the present invention, the periodicity of described first multiple quantum well layer is 2～6.
On the other hand, the embodiment of the invention provides a kind of method of making the semiconductor light-emitting-diode epitaxial wafer, comprising:
One substrate is provided;
Low temperature growth buffer layer, high temperature buffer layer, compound N-type layer, compound multiple quantum well layer and compound P type layer successively on described substrate, wherein, described compound multiple quantum well layer comprises first multiple quantum well layer and second multiple quantum well layer of growing at described first multiple quantum well layer, described first multiple quantum well layer is the multicycle structure, each cycle comprises potential well layer and the barrier layer of growing at described potential well layer
Wherein, during the barrier layer in described first each cycle of multiple quantum well layer of growing, Si mixes in described barrier layer.
In one embodiment of the invention, in described first multiple quantum well layer, described Si is entrained in the position away from described potential well layer of described barrier layer.
In another embodiment of the present invention, 10%～90% of described barrier layer thickness is doped with described Si.
In an embodiment more of the present invention, the growth temperature of described barrier layer is 820～950 ℃, and growth pressure is 100Torr～500Torr, and V/III mol ratio is 300～5000.
The beneficial effect that the technical scheme that the embodiment of the invention provides is brought is:
When the barrier layer of first multiple quantum well layer is grown at low temperatures, the surface that the Si that barrier layer mixes can suppress barrier layer forms the spiral island structure, therefore the surface characteristic of barrier layer is good, and this makes that further the crystal mass that is layered in second multiple quantum well layer on first multiple quantum well layer is good, luminous efficiency is high.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The structural representation of the epitaxial wafer of the semiconductor light-emitting-diode that Fig. 1 provides for the embodiment of the invention;
Fig. 2 is the detailed construction schematic diagram of compound multiple quantum well layer in the epitaxial wafer shown in Figure 1;
The flow chart of the method for the manufacturing semiconductor light-emitting-diode epitaxial wafer that Fig. 3 provides for the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Embodiment one
Present embodiment provides a kind of epitaxial wafer of semiconductor light-emitting-diode, participates in Fig. 1, and this epitaxial wafer comprises substrate 1 and the low temperature buffer layer 2, high temperature buffer layer 3, compound N-type layer, compound multiple quantum well layer and the compound P type layer that stack gradually on substrate 1.This compound multiple quantum well layer comprises first multiple quantum well layer 8 and second multiple quantum well layer 9 of growing at first multiple quantum well layer 8.In conjunction with Fig. 2, first multiple quantum well layer 8 is the multicycle structure, and each cycle comprises potential well layer b1 and the barrier layer a1 that grows at potential well layer b1.The barrier layer a1 in each cycle of first multiple quantum well layer 8 is doped with Si respectively, the part of doping Si among Fig. 2 bend region representation barrier layer a1.
Further, in first multiple quantum well layer 8, Si is entrained in the position away from potential well layer b1 of barrier layer a1.
The advantage of technique scheme is: at the Si that undopes near the position of potential well layer, can avoid Si to be diffused into forming in the potential well layer non-radiative compound.Further, 10%～90% of barrier layer thickness is doped with Si, and the such doping thickness ratio of Si can either suppress dislocation, is unlikely to Si again and is diffused in the trap.
Further, effective doping content of Si is 5 * 10
16～1 * 10
19/ cm
3, so effective doping content can either suppress dislocation, and how high be unlikely to doping content again, brings extra defective.
Further, the thickness of barrier layer is 10～15nm, and it is compound at well region that such scope can be good at limiting charge carrier, and has played the effect that improves the quantum well crystal mass.
Further, the periodicity of first multiple quantum well layer is 2～6, and such periodicity had both played the effect that improves crystal mass, and it is too much to be unlikely to periodicity again, and the quantum well crystal mass that causes growing later descends.
As shown from the above technical solution, when the barrier layer of first multiple quantum well layer is grown at low temperatures, the surface that the Si that barrier layer mixes can suppress barrier layer forms the spiral island structure, therefore the surface characteristic of barrier layer is good, and this makes that further the crystal mass that is layered in second multiple quantum well layer on first multiple quantum well layer is good, luminous efficiency is high.
In addition, barrier layer doping Si can reduce the point defect density of barrier layer on the one hand, thereby can improve the crystal mass of the barrier layer of growing under low temperature, can effectively shield polarization field simultaneously.
Embodiment two
Present embodiment provides a kind of method of making the semiconductor light-emitting-diode epitaxial wafer, and this method is utilized Thomas Swan(AIXTRON subsidiary) CCS MOCVD system implements, and this method is with high-purity hydrogen (H
2) or nitrogen (N
2) as carrier gas, with trimethyl gallium (TMGa) or triethyl-gallium (TEGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia (NH
3) respectively as Ga, Al, In and N source, with silane (SiH
4), two luxuriant magnesium (Cp2Mg) are respectively as N, P type dopant.
Particularly, with reference to figure 3, and in conjunction with Fig. 1 and Fig. 2, the method that present embodiment is made the semiconductor light-emitting-diode epitaxial wafer comprises the steps:
Step S1, one substrate 1 is provided and substrate 1 is carried out heat cleaning and nitrogen treatment: the surface of substrate 1 (for example 1180 ℃), pure hydrogen atmosphere interior heat in 1050～1200 ℃ of temperature ranges being cleaned substrate 1, then substrate 1 is cooled to 630 ℃, under this temperature, carry out nitrogen treatment, in the present embodiment, substrate 1 is the material that is fit to gallium nitride and the growth of other semiconductor epitaxial material, as gallium nitride single crystal, sapphire, monocrystalline silicon, single-crystal silicon carbide etc.;
Step S2, at low temperature growth buffer layer 2 on the substrate 1: after substrate 1 is handled, temperature is dropped to 500 ℃～650 ℃ (for example 630 ℃ under), in substrate 1 these low temperature buffer layer 2 Doped GaN of superficial growth one deck low temperature buffer layer 2(), in this growth course, growth pressure be 300～760Torr(for example growth pressure be 400Torr), V/III mol ratio be 600～3000(for example V/III mol ratio be 900), wherein the thickness of low temperature buffer layer 2 be 20～30nm(for example thickness be 25nm);
Step S3, at low temperature buffer layer 2 growth high temperature buffer layers 3: behind low temperature buffer layer 2 growth endings, stop to feed the TMGa(trimethyl gallium), the temperature of substrate 1 is increased to 1000～1200 ℃ (for example being increased to 1170 ℃), low temperature buffer layer 2 is carried out thermal anneal process, the thermal annealing time is 5～10 minutes (for example 5 minutes), after the thermal anneal process, with adjustment to 1000～1200 ℃ (for example being adjusted to 1180 ℃), at these high temperature buffer layers 3 of low temperature buffer layer 2 growth one deck high temperature buffer layer 3(GaN that undopes), in this growth course, growth pressure be 100～600Torr(for example growth pressure be 200Torr), V/III mol ratio be 300～3000(for example V/III mol ratio be 1500), wherein the thickness of high temperature buffer layer 3 be 0.8～2 μ m(for example thickness be 1.2 μ m);
Step S4, at the high temperature buffer layer 3 growth first N-type layer 4: behind high temperature buffer layer 3 growth endings, at high temperature buffer layer 3 growth one decks first N-type layer 4, in this growth course, growth pressure be 100～600Torr(for example growth pressure be 150Torr), V/III mol ratio be 300～3000(for example V/III mol ratio be 1800), growth temperature is 1000～1200 ℃ (for example growth temperature is 1180 ℃), wherein the thickness of the first N-type layer 4 0.2～1 μ m(for example thickness be 0.8 μ m), the first N-type layer 4 is doped with SiH4, and doping content is from 1 * 10
17/ cm
3Change to 5 * 10
18/ cm
3
Step S5, behind 5: the first N-type layer 4 growth ending of the first N-type layer 4 growth, the second N-type layer, at the first N-type layer, 4 growth one deck, the second N-type layer 5, in this growth course, growth pressure be 100～600Torr(for example growth pressure be 150Torr), V/III mol ratio be 300～3000(for example V/III mol ratio be 1800), growth temperature is 1000 ℃～1200 ℃ (for example growth temperature is 1180 ℃), wherein the thickness of the second N-type layer 5 be 1.2～3.5 μ m(for example thickness be 3.5 μ m), the second N-type layer 5 is doped with SiH4, and doping content is stable;
Step S6, behind 6: the second N-type layer 5 growth ending of growth regulation three N-type layers on the second N-type layer 5, at the second N-type layer, 5 growth one deck the 3rd N-type layer 6, in this growth course, growth pressure be 100～600Torr(for example growth pressure be 150Torr), V/III mol ratio be 300～3000(for example V/III mol ratio be 2800), growth temperature is 1000～1200 ℃, and (for example growth temperature is 1180 ℃,), wherein the thickness of the 3rd N-type layer 6 be 10～100nm(for example thickness be 20nm), the 3rd N-type layer 6 is doped with SiH4, doping content is stable, and doping content is lower than the mean concentration of the first N-type layer 4, is lower than the doping content of the second N-type layer 5, far below the doping content of the 4th N-type layer 7, its objective is in order to improve the mobility of charge carrier rate;
Step S7, behind 7: the three N-type layer of growth regulation four N-type layers, 6 growth ending on the 3rd N-type layer 6, at the 3rd N-type layer 6 growth one deck the 4th N-type layer 7, in this growth course, growth pressure be 100～600Torr(for example growth pressure be 150Torr), V/III mol ratio be 300～3000(for example V/III mol ratio be 2800); Growth temperature is 1000～1200 ℃ (for example growth temperature is 1180 ℃), wherein the thickness of the 4th N-type layer 7 be 10～50nm(for example thickness be 10nm), the 4th N-type layer 7 is doped with SiH4, doping content is stable, doping content is higher than the doping content of the second N-type layer 5, the 4th N-type layer 7 is the highest zones of whole N-type regional concentration, its objective is in order to obtain higher carrier concentration;
Step S8, behind the 4th N-type layer 7 growth one deck first Multiple Quantum Well (MQW) layer 8:N type layer 7 growth ending, at N-type layer 7 growth one deck first multiple quantum well layer 8, first multiple quantum well layer 8 is the multicycle structure, periodicity be 2～6(for example periodicity be 4), each cycle comprises potential well layer b1(In
aGa
1-aN layer, 0＜a＜1) and be layered in barrier layer (GaN layer) a1(on the potential well layer b1 for example each cycle comprises In
0.3Ga
0.7N layer and GaN layer), wherein the growth technique condition of each cycle potential well layer b1 is: growth temperature is 720～850 ℃ (for example growth temperature is 780 ℃), growth pressure be 100～500Torr(for example growth pressure be 200Torr), V/III mol ratio be 300～5000(for example V/III mol ratio be 4500), the thickness of each cycle potential well layer b1 be 2～3nm(for example thickness be 2.5nm); The barrier layer a1 in each cycle is doped with Si respectively, and Si is entrained in the position away from potential well layer b1 of barrier layer a1.Particularly, 10%～90%(of barrier layer thickness for example 50%) be doped with Si, effective doping content of Si is 5 * 10
16～1 * 10
19/ cm
3(for example effectively doping content is 2 * 10
17/ cm
3Need to prove that effectively doping content refers to the maximum impurity concentration that can activate, " activation " is will mix impurity ionization among the Si by certain means here, form the process of conductive mechanism), the part of doping Si among Fig. 2 bend region representation barrier layer a1.The growth technique condition of each cycle barrier layer a1 is: growth temperature is 820～950 ℃ (for example growth temperature is 900 ℃), growth pressure be 100～500Torr(for example growth pressure be 200Torr), V/III mol ratio be 300～5000(for example V/III mol ratio be 4500), the thickness of each cycle barrier layer a1 be 10～15nm(for example thickness be 12nm);
Step S9, behind 9: the first multiple quantum well layer 8 growth ending of first multiple quantum well layer 8 growth one deck second Multiple Quantum Well (MQW) layer, at first multiple quantum well layer, 8 growth one decks, second multiple quantum well layer 9, this second multiple quantum well layer 9 is the multicycle structure, periodicity be 3～6(for example periodicity be 5), each cycle comprises potential well layer b2(In
bGa
1-bN layer, 0＜b＜1) and be layered in barrier layer (GaN) a2(on the potential well layer b2 for example each cycle comprises In
0.3Ga
0.7N layer and GaN layer).Wherein the growth technique condition of each cycle potential well layer b2 is: growth temperature is 720～820 ℃ (for example growth temperature is 780 ℃), growth pressure be 100～500Torr(for example growth pressure be 200Torr), V/III mol ratio be 300～5000(for example V/III mol ratio be 4500), the thickness of each cycle potential well layer b2 be 2～3nm(for example thickness be 2.5nm); The growth technique condition of each cycle barrier layer a2 is: growth temperature is 820～920 ℃ (for example growth temperature is 900 ℃), growth pressure be 100～500Torr(for example growth pressure be 200Torr), V/III mol ratio be 300～5000(for example V/III mol ratio be 4500), the gross thickness of each cycle barrier layer a2 be 10～15nm(for example thickness be 12nm), wherein, barrier layer a2 undopes; Step S10 behind 10: the second multiple quantum well layer 9 growth ending of second multiple quantum well layer 9 growth one decks the one P type layer, is Al at second multiple quantum well layer, 9 growth one decks the one P type layer, 10, the one P type layer 10
xGa
1-xThe N material, 0＜x＜1, play the effect that electronics stops, in the growth course of the one P type layer 10, growth temperature is 950～1080 ℃ (for example temperature is 1020 ℃), growth pressure be 50～500Torr(for example growth pressure be 300Torr), V/III mol ratio be 1000～20000(for example V/III mol ratio be 12000), wherein the thickness of a P type layer 10 be 10～200nm(for example growth thickness be 20nm), the energy gap of the one P type layer 10 is 4～5.5eV, P type layer 10 is doped with Mg(magnesium), P type layer 10 is doped with two luxuriant magnesium (Cp2Mg), in the Mg of doping and the P type layer 10 mol ratio of Ga be 1/100～1/4(for example mol ratio be: Mg/Ga=1/4);
Step S11, behind 11: a P type layer of a P type layer 10 growth one deck the 2nd P type layer, 10 growth ending, at a P type layer 10 growth one deck the 2nd P type layer 11, the 2nd P type layer 11 is the GaN material, in the growth course of the 2nd P type layer 11, growth pressure 200Torr, V/III mol ratio 8000, growth temperature is 850～1050 ℃ (for example growth temperature is 1000 ℃), wherein the thickness of the 2nd P type layer 11 be 100～800nm(for example thickness be 0.4 μ m), the 2nd P type layer 11 is doped with two luxuriant magnesium (Cp2Mg), in the Mg of doping and the 2nd P type layer 11 mol ratio of Ga be 1/100～1/4(for example mol ratio be: 1/80);
Step S12, behind 12: the two P type layer of the 2nd P type layer 11 growth one deck the 3rd P type layer, 11 growth ending, at the 2nd P type layer 11 growth one deck the 3rd P type layer 12, the 3rd P type layer 12 is the GaN material, it is contact layer, in the growth course of the 3rd P type layer 12, growth pressure be 100～760Torr(for example growth pressure be 200Torr), V/III mol ratio is for example V/III mol ratio 10000 of 1000～20000(), growth temperature is (for example growth temperature is 1050 ℃) between 850～1050 ℃, wherein the thickness of the 3rd P type layer 12 be 5～20nm(for example thickness be 15nm), the 3rd P type layer 10 is doped with two luxuriant magnesium (Cp2Mg), in the Mg of doping and the 3rd P type layer 12 mol ratio of Ga be 1/100～1/4(for example mol ratio be: Mg/Ga=1/50);
Step S13, post-processed: behind the 3rd P type layer 12 growth ending, the temperature of reaction chamber is down to 650～850 ℃ (for example being down to 800 ℃), carry out annealing in process 5～15min(in the pure nitrogen gas atmosphere and for example handle 10min), be down to room temperature then, so far, the epitaxial wafer of semiconductor light-emitting-diode completes.
Need to prove, after the epitaxial wafer of semiconductor light-emitting-diode completes, at the 3rd P type layer 12 growth layer of transparent conductive layer (ITO) 13, at P electrode 14 of transparency conducting layer 13 welding, at N electrode 15 of the second N-type layer, 5 welding, semiconductor light-emitting-diode completes like this.Behind the semiconducter process processing procedures such as the cleaning of semiconductor light-emitting-diode process, deposition, photoetching and etching, be divided into the led chip that size is 11 * 11mil.Through the led chip test, measuring current 20mA, single little chip optical output power is 11.5mW or 11.0mW.And traditional epitaxial growth mode, the power output of single little chip light of identical chips processing procedure is 10.2mW.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the epitaxial wafer of a semiconductor light-emitting-diode, comprise substrate and the low temperature buffer layer of growing at described substrate successively, high temperature buffer layer, compound N-type layer, compound multiple quantum well layer and compound P type layer, described compound multiple quantum well layer comprises first multiple quantum well layer and second multiple quantum well layer of growing at described first multiple quantum well layer, described first multiple quantum well layer is the multicycle structure, each cycle comprises potential well layer and the barrier layer of growing at described potential well layer, it is characterized in that the barrier layer in described first each cycle of multiple quantum well layer is doped with Si respectively.
2. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 1 is characterized in that, in described first multiple quantum well layer, described Si is entrained in the position away from described potential well layer of described barrier layer.
3. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 2 is characterized in that, 10%～90% of described barrier layer thickness is doped with described Si.
4. as the epitaxial wafer of claim 2 or 3 described semiconductor light-emitting-diodes, it is characterized in that effective doping content of described Si is 5 * 10
16～1 * 10
19/ cm
3
5. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 4 is characterized in that, the thickness of described barrier layer is 10～15nm.
6. the epitaxial wafer of semiconductor light-emitting-diode as claimed in claim 4 is characterized in that, the periodicity of described first multiple quantum well layer is 2～6.
7. method of making the semiconductor light-emitting-diode epitaxial wafer comprises:
One substrate is provided;
Low temperature growth buffer layer, high temperature buffer layer, compound N-type layer, compound multiple quantum well layer and compound P type layer successively on described substrate, wherein, described compound multiple quantum well layer comprises first multiple quantum well layer and second multiple quantum well layer of growing at described first multiple quantum well layer, described first multiple quantum well layer is the multicycle structure, each cycle comprises potential well layer and the barrier layer of growing at described potential well layer
It is characterized in that during the barrier layer in described first each cycle of multiple quantum well layer of growing, Si mixes in described barrier layer.
8. the method for manufacturing semiconductor light-emitting-diode epitaxial wafer as claimed in claim 7 is characterized in that, in described first multiple quantum well layer, described Si is entrained in the position away from described potential well layer of described barrier layer.
9. semiconductor light-emitting-diode epitaxial wafer as claimed in claim 8 is characterized in that, 10%～90% of described barrier layer thickness is doped with described Si.
10. the method for manufacturing semiconductor light-emitting-diode epitaxial wafer as claimed in claim 9 is characterized in that, the growth temperature of described barrier layer is 820～950 ℃, and growth pressure is 100Torr～500Torr, and V/III mol ratio is 300～5000.
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