KR20060079424A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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KR20060079424A
KR20060079424A KR1020040117613A KR20040117613A KR20060079424A KR 20060079424 A KR20060079424 A KR 20060079424A KR 1020040117613 A KR1020040117613 A KR 1020040117613A KR 20040117613 A KR20040117613 A KR 20040117613A KR 20060079424 A KR20060079424 A KR 20060079424A
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layer
silicon layer
forming
silicon
insulating
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KR1020040117613A
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Korean (ko)
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KR100640969B1 (en
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정명진
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동부일렉트로닉스 주식회사
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Priority to KR1020040117613A priority Critical patent/KR100640969B1/en
Priority to JP2005343355A priority patent/JP4495073B2/en
Priority to DE102005059455A priority patent/DE102005059455A1/en
Priority to CNB2005101359900A priority patent/CN100533765C/en
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Abstract

본 발명은 스트레인드 절연층 하부에 절연막을 형성함으로써, 소자 동작시 채널 감소에 따른 문제점을 해결할 수 있는 반도체 소자 및 이의 형성 방법에 관한 것으로, 이의 반도체 소자의 제조 방법은 제 1 실리콘층 상에 게르마늄을 성장시켜 제 2 실리콘층을 형성하는 단계와, 상기 제 2 실리콘층 상에 제 1 절연막을 증착하는 단계와, 상기 제 1 절연막 상부에 소정 부위가 오픈되는 제 1 감광막을 형성하는 단계와, 상기 제 1 감광막을 마스크로 하여 상기 제 1 절연막 및 제 2 실리콘층의 소정 두께를 제거하여 홀을 형성하는 단계와, 상기 제 1 절연막 및 제 1 감광막을 제거하는 단계와, 상기 홀 내벽에 제 2 절연막을 형성하는 단계와, 상기 홀 하부의 제 2 절연막이 노출되도록 상기 제 2 실리콘층을 제거하는 단계와, 상기 제 2 실리콘층 상에 게르마늄을 성장시켜 제 3 실리콘층을 형성하는 단계와, 상기 제 3 실리콘층, 제 2 실리콘층 및 제 1 실리콘층을 선택적으로 제거하고 제거된 영역에 절연막을 채워 소자 격리막을 형성하는 단계와, 상기 제 3 실리콘층 상부 소정 부위에 게이트 절연막 및 게이트 폴리층을 형성하는 단계와, 상기 게이트 절연막 및 게이트 폴리층 측벽에 스페이서를 형성하는 단계와, 상기 게이트 폴리층 및 스페이서를 마스크로 이용하여 상기 제 3 실리콘층 에 불순물 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The present invention relates to a semiconductor device and a method of forming the semiconductor device that can solve the problems caused by channel reduction during operation of the device by forming an insulating film under the strained insulating layer, the manufacturing method of the semiconductor device is germanium on the first silicon layer Growing a second silicon layer to form a second silicon layer, depositing a first insulating film on the second silicon layer, forming a first photosensitive film having a predetermined portion open on the first insulating film, and Forming a hole by removing a predetermined thickness of the first insulating film and the second silicon layer using the first photosensitive film as a mask, removing the first insulating film and the first photosensitive film, and a second insulating film on the inner wall of the hole Forming a metal layer; removing the second silicon layer to expose the second insulating layer under the hole; and forming germanium on the second silicon layer. Forming a third silicon layer by selectively removing the third silicon layer, the second silicon layer, and the first silicon layer, and filling an insulating layer with the removed region to form a device isolation layer; Forming a gate insulating layer and a gate poly layer on a predetermined portion of the layer; forming a spacer on sidewalls of the gate insulating layer and the gate poly layer; and using the gate poly layer and the spacer as a mask to the third silicon layer. And forming an impurity region.

스트레인드 실리콘, 누설전류(Leakage Current), DIBL(Drain Induced Barrier Lowing), 접합 붕괴전압(Junction Breakdown Voltage)Strained Silicon, Leakage Current, Drain Induced Barrier Lowing, Junction Breakdown Voltage

Description

반도체 소자 및 이의 제조 방법{Semiconductor Device and Method for Manufacturing the Same}Semiconductor device and method for manufacturing the same

도 1 내지 도 6은 본 발명의 반도체 소자의 형성 방법을 나타낸 공정 단면도1 to 6 are cross-sectional views illustrating a method of forming a semiconductor device of the present invention.

*도면의 주요 부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *

10 : 기판 3 : 제 1 실리콘층10 substrate 3 first silicon layer

5 : 제 2 실리콘층 11 : 제 1 절연막5: second silicon layer 11: first insulating film

12 : 제 1 감광막 15 : 홀12: first photosensitive film 15: hole

17 : 제 2 절연막 23 : 제 3 실리콘층17: second insulating film 23: third silicon layer

31 : 격리 절연막 41 : 게이트 절연막31 insulating film 41 gate insulating film

42 : 게이트 폴리 43a/43b : 소오스 영역/드레인 영역42: gate poly 43a / 43b: source region / drain region

본 발명은 반도체 소자에 관한 것으로 특히, 스트레인드 절연층 하부에 절연막을 형성함으로써, 소자 동작시 채널 감소에 따른 문제점을 해결할 수 있는 반도체 소자 및 이의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of forming the same, by forming an insulating film under a strained insulating layer, thereby solving a problem caused by channel reduction during device operation.

실리콘(Si) 기판 위에 게르마늄(Ge) 단편을 올려놓고 온도 공정을 통하여 실 리콘(Si) 위의 게르마늄(Ge)을 성장시키고 그 위에 실리콘(Si)을 접합하여 또 한번의 열 공정을 거치면 격자의 크기가 게르마늄(Ge)과 동일한 격자의 크기를 가지는 스트레인드 실리콘(Strained Si)이 성장된다. Placing a germanium (Ge) fragment on a silicon (Si) substrate, growing germanium (Ge) on silicon (Si) through a temperature process, and bonding silicon (Si) on it, undergoing another thermal process, Strained Si having a lattice size equal to that of germanium (Ge) is grown.

이러한 스트레인드 실리콘층(Strained Si)은 반도체 소자(Device)는 소자의 크기가 점점 줄어들 때, 전자와 홀의 전자 이동도가 같이 줄어드는 문제가 발생하여, 전자와 홀의 이동도를 높이고자 고안된 기판형이다.The strained silicon layer (Strained Si) is a substrate type designed to increase the mobility of electrons and holes, because the semiconductor device (Device) has a problem that the electron mobility of the electrons and holes decreases as the size of the device is gradually reduced .

한편, 이러한 스트레인드 실리콘(Strained Si)을 이용한 반도체 소자의 하나로 스트레인드 실리콘 MOSFET이 있다. On the other hand, one of the semiconductor devices using the strained silicon (Strained Si) is a strained silicon MOSFET.

상기 스트레이트 실리콘층은 일반 실리콘층(Si)위에 게르마늄(Ge)을 성장시켜 실리콘(Si) 원자와 원자 사이를 게르마늄(Ge)의 원자 간격만큼 늘리고 그 위에 실리콘(Si)을 성장시켜 형성한다. 이 경우, 상기 스트레인드 실리콘층(strained Si)은, 기존의 실리콘(Si) 격자의 간격보다 훨씬 넓어진 격자 구조를 가지는 기판으로 형성된다.The straight silicon layer is formed by growing germanium (Ge) on a general silicon layer (Si) by increasing the atomic interval of germanium (Ge) between silicon (Si) atoms and atoms and growing silicon (Si) thereon. In this case, the strained Si layer is formed of a substrate having a lattice structure that is much wider than a gap of a conventional silicon (Si) lattice.

그러나, 스트레인드 실리콘층을 이용함으로써, 전자와 홀의 이동도를 높여 반도체 소자의 효율(performance)을 높였지만 반도체 소자가 나노(Nano) 계열의 크기로 떨어짐으로 인하여 발생되는 누설전류(Leakage Current) 그로 인한 DIBL(Drain Induced Barrier Lowing)과 누설전류 증가로 인한 접합 붕괴전압(Junction Breakdown Voltage)은 해결할 수 없었다.However, the use of the strained silicon layer increases the mobility of electrons and holes, thereby increasing the efficiency of the semiconductor device. However, the leakage current caused by the semiconductor device falling to the size of the nano series is therefore reduced. The DBL (Drain Induced Barrier Lowing) and the Junction Breakdown Voltage due to the increased leakage current could not be solved.

상기와 같은 종래의 스트레인드 실리콘층을 이용한 반도체 소자는 다음과 같 은 문제점이 있다.The semiconductor device using the conventional strained silicon layer as described above has the following problems.

스트레인드 실리콘층을 이용함으로써, 전자와 홀의 이동도를 높여 반도체 소자의 효율(performance)을 높였지만 반도체 소자가 나노(Nano) 계열의 크기로 떨어짐으로 인하여 발생되는 누설전류(Leakage Current) 그로 인한 DIBL(Drain Induced Barrier Lowing)과 누설전류 증가로 인한 접합 붕괴전압(Junction Breakdown Voltage)은 해결할 수 없었다.By using the strained silicon layer, the electron and hole mobility is increased to increase the efficiency of the semiconductor device, but the leakage current caused by the semiconductor device falling to the size of the nano series is caused by the DIBL. (Drain Induced Barrier Lowing) and Junction Breakdown Voltage due to increased leakage current could not be solved.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 스트레인드 절연층 하부에 절연막을 형성함으로써, 소자 동작시 채널 감소에 따른 문제점을 해결할 수 있는 반도체 소자 및 이의 형성 방법을 제공하는 데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, by providing an insulating film under the strain insulating layer, to provide a semiconductor device and a method of forming the same that can solve the problems caused by channel reduction during device operation, the object There is this.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자는 실리콘층 상에 게르마늄이 성장시켜 스트레인드 실리콘으로 형성된 기판과, 상기 기판의 소정 부위에 형성된 소자 격리막과, 상기 소자 격리막을 제외한 기판 상의 영역 중 소정 부위에 형성된 게이트 폴리층과, 상기 게이트 폴리층 양측에 대응되어 상기 기판에 정의된 소오스/드레인 영역 및 상기 소오스/드레인 영역 하부에 형성되며, 상기 소자 격리막과 연결되는 절연막을 포함하여 이루어짐에 그 특징이 있다.A semiconductor device of the present invention for achieving the above object is a substrate formed of strained silicon by the growth of germanium on the silicon layer, the device isolation film formed on a predetermined portion of the substrate, and the region on the substrate except the device isolation film A gate poly layer formed at a predetermined portion, a source / drain region defined in the substrate corresponding to both sides of the gate poly layer, and an insulating layer formed under the source / drain region and connected to the device isolation layer. There is a characteristic.

상기 게이트 폴리 측벽에는 스페이서가 더 형성된다.Spacers are further formed on the gate poly sidewalls.

상기 소오스/드레인 영역은 상기 스페이서 및 게이트 폴리 양측의 액티브 영역에 형성된다.The source / drain regions are formed in active regions on both sides of the spacer and the gate poly.

또한, 동일한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 제 1 실리콘층 상에 게르마늄을 성장시켜 제 2 실리콘층을 형성하는 단계와, 상기 제 2 실리콘층 상에 제 1 절연막을 증착하는 단계와, 상기 제 1 절연막 상부에 소정 부위가 오픈되는 제 1 감광막을 형성하는 단계와, 상기 제 1 감광막을 마스크로 하여 상기 제 1 절연막 및 제 2 실리콘층의 소정 두께를 제거하여 홀을 형성하는 단계와, 상기 제 1 절연막 및 제 1 감광막을 제거하는 단계와, 상기 홀 내벽에 제 2 절연막을 형성하는 단계와, 상기 홀 하부의 제 2 절연막이 노출되도록 상기 제 2 실리콘층을 제거하는 단계와, 상기 제 2 실리콘층 상에 게르마늄을 성장시켜 제 3 실리콘층을 형성하는 단계와, 상기 제 3 실리콘층, 제 2 실리콘층 및 제 1 실리콘층을 선택적으로 제거하고 제거된 영역에 절연막을 채워 소자 격리막을 형성하는 단계와, 상기 제 3 실리콘층 상부 소정 부위에 게이트 절연막 및 게이트 폴리층을 형성하는 단계와, 상기 게이트 절연막 및 게이트 폴리층 측벽에 스페이서를 형성하는 단계와, 상기 게이트 폴리층 및 스페이서를 마스크로 이용하여 상기 제 3 실리콘층 에 불순물 영역을 형성하는 단계를 포함하여 이루어짐에 또 다른 특징이 있다.In addition, the method of manufacturing a semiconductor device of the present invention for achieving the same object comprises the steps of forming a second silicon layer by growing germanium on the first silicon layer, and depositing a first insulating film on the second silicon layer Forming a hole in the upper portion of the first insulating layer by removing a predetermined thickness of the first insulating layer and the second silicon layer using the first photosensitive layer as a mask; Removing the first insulating film and the first photoresist film, forming a second insulating film on the inner wall of the hole, and removing the second silicon layer to expose the second insulating film under the hole; Growing germanium on the second silicon layer to form a third silicon layer, and selectively removing and removing the third silicon layer, the second silicon layer, and the first silicon layer. Forming an isolation layer by filling an insulating layer in a region, forming a gate insulating layer and a gate poly layer on a predetermined portion of the third silicon layer, forming spacers on sidewalls of the gate insulating layer and the gate poly layer, Another aspect is that the method includes forming an impurity region in the third silicon layer using the gate poly layer and the spacer as a mask.

이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자 및 이의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

도 1 내지 도 6은 본 발명의 반도체 소자의 형성 방법을 나타낸 공정 단면도이다.1 to 6 are process cross-sectional views showing a method of forming a semiconductor device of the present invention.

본 발명의 반도체 소자의 제조 방법은 먼저, 도 1과 같이, 제 1 실리콘층(3) 상에 에피텍셜(Epitaxial Growth) 성장을 통하여 게르마늄(Ge)을 성장시켜 제 2 실리콘층(5)을 형성한다. In the method of manufacturing a semiconductor device of the present invention, first, as shown in FIG. 1, germanium (Ge) is grown on the first silicon layer 3 to form a second silicon layer 5 by epitaxial growth. do.

이어, 상기 제 2 실리콘층(5) 상에 제 1 절연막(11)을 증착한다.Subsequently, a first insulating layer 11 is deposited on the second silicon layer 5.

이어, 상기 제 1 절연막(11) 상에 감광막을 도포하고, 이를 노광 및 현상하여 상기 제 1 절연막(11) 상부에 소정 부위가 오픈되는 제 1 감광막(12)을 형성한다.Subsequently, a photoresist film is coated on the first insulating film 11, and the photoresist film is exposed and developed to form a first photoresist film 12 having a predetermined portion open on the first insulating film 11.

도 2와 같이, 상기 제 1 감광막(12)을 마스크로 하여 상기 제 1 절연막(11) 및 제 2 실리콘층(5)의 소정 두께를 제거하여 홀(hole)(15)을 형성한다.As illustrated in FIG. 2, holes 15 are formed by removing predetermined thicknesses of the first insulating layer 11 and the second silicon layer 5 using the first photoresist layer 12 as a mask.

이어, 상기 제 1 절연막(11)을 제거한다. Next, the first insulating layer 11 is removed.

이어, 상기 제 1 감광막(12)을 제거한다.Next, the first photosensitive film 12 is removed.

이어, 상기 홀(15) 내벽에 포함하여 상기 제 2 실리콘층(5a) 상부에 소정 두께로 제 2 절연막(17)을 형성한다. 상기 제 2 절연막(17)을 평탄화하여 상기 제 2절연막(17)을 상기 홀(15) 내벽에만 남긴다.Subsequently, the second insulating layer 17 is formed on the inner wall of the hole 15 to have a predetermined thickness on the second silicon layer 5a. The second insulating layer 17 is planarized to leave the second insulating layer 17 only on the inner wall of the hole 15.

도 3과 같이, 상기 제 2 절연막(17) 및 제 2 실리콘층(5a)을 소정 두께 제거하여, 상기 홀(15) 하부의 제 2 절연막(17a)이 노출되도록 한다.As shown in FIG. 3, the second insulating layer 17 and the second silicon layer 5a are removed by a predetermined thickness so that the second insulating layer 17a under the hole 15 is exposed.

도 4 및 도 5와 같이, 상기 제 2 실리콘층(5c) 상에 게르마늄을 계속적으로 성장시켜 제 3 실리콘층(23)을 형성한다.4 and 5, germanium is continuously grown on the second silicon layer 5c to form a third silicon layer 23.

도 6과 같이, 상기 제 3 실리콘층(23a), 제 2 실리콘층(5c) 및 제 1 실리콘층(3)을 선택적으로 제거하고 제거된 영역에 절연막을 채워 소자 격리막(31)을 형성한다.As shown in FIG. 6, the device isolation layer 31 is formed by selectively removing the third silicon layer 23a, the second silicon layer 5c, and the first silicon layer 3 and filling an insulating layer in the removed region.

이어, 상기 제 3 실리콘층(23) 상부에 게이트 절연막 및 게이트 폴리층을 전 면 증착한 후 이를 동일 폭으로 제거하여 소정 부위에 게이트 절연막(41) 및 게이트 폴리층(42)을 형성한다.Subsequently, the gate insulating layer and the gate poly layer are entirely deposited on the third silicon layer 23, and the gate insulating layer 41 and the gate poly layer 42 are formed at predetermined portions by removing the gate insulating layer and the gate poly layer.

이 때, 상기 게이트 절연막(41)의 폭은 소오스/드레인 영역(44a, 44b)의 디플리션(Fully Depletion) 지점에 위치하도록 하여 누설 경로(Leakage Path)가 길어지게 한다.In this case, the width of the gate insulating layer 41 is positioned at the fully depletion point of the source / drain regions 44a and 44b to increase the leakage path.

이어, 상기 게이트 절연막(41) 및 게이트 폴리층(42) 측벽에 스페이서(43)를 형성한다.Subsequently, spacers 43 are formed on sidewalls of the gate insulating layer 41 and the gate poly layer 42.

이어, 상기 게이트 폴리층(42) 및 스페이서(43)를 마스크로 이용하여 상기 제 3 실리콘층(23a)에 불순물 영역을 형성하여 소오스/드레인 영역(44a, 44b)을 정의한다. 이 때, 도시되지 않았지만, LDD(Lightly Doped Drain)을 더 형성할 수도 있다.Subsequently, source / drain regions 44a and 44b are defined by forming an impurity region in the third silicon layer 23a using the gate poly layer 42 and the spacer 43 as a mask. At this time, although not shown, a lightly doped drain (LDD) may be further formed.

본 발명의 반도체 소자는 도 6과 같이, 제 1 실리콘층(3) 상에 게르마늄이 성장시켜 스트레인드 실리콘(5c, 23)으로 형성된 기판(10)과, 상기 기판의 소정 부위에 형성된 소자 격리막(31)과, 상기 소자 격리막(31)을 제외한 기판(10) 상의 영역 중 소정 부위에 형성된 게이트 폴리층(42) 및 게이트 절연막(41)의 적층체와, 상기 게이트 폴리층(42) 양측에 대응되어 상기 기판에 정의된 소오스/드레인 영역(44a, 44b) 및 상기 소오스/드레인 영역(44a, 44b) 하부에 형성되며, 상기 소자 격리막(31)과 연결되는 절연막(17a, 17b)을 포함하여 이루어진다. 그리고, 상기 게이트 폴리(41) 측벽에는 스페이서(43)가 더 형성된다. 그리고, 상기 소오스/드레인 영역(44a, 44b)은 상기 스페이서(43) 및 게이트 폴리(42) 양측의 기판(10) 액티브 영역에 형성된다.As shown in FIG. 6, the semiconductor device of the present invention includes a substrate 10 formed of strained silicon 5c and 23 by growing germanium on the first silicon layer 3, and an isolation layer formed on a predetermined portion of the substrate. 31, a laminate of the gate poly layer 42 and the gate insulating layer 41 formed at a predetermined portion of regions on the substrate 10 except for the device isolation layer 31, and both sides of the gate poly layer 42. And formed under the source / drain regions 44a and 44b and the source / drain regions 44a and 44b defined in the substrate, and include insulating layers 17a and 17b connected to the device isolation layer 31. . In addition, spacers 43 are further formed on sidewalls of the gate poly 41. The source / drain regions 44a and 44b are formed in the active region of the substrate 10 on both sides of the spacer 43 and the gate poly 42.

본 발명은 스트레인드 실리콘층(Strained Si) 내부 소오스/드레인 하부에 절연막을 형성함으로써 MOSFET 동작시 채널 감소에 따른 문제점을 해결할 수 있는 반도체 소자 및 이의 제조 방법으로써 저전력, 저전압, 고속의 소자(Device)가 요구되어지는 현실에서 반도체 소자의 최소 피치 크기를 줄이면서 누설전류를 해결하고 이로 인한 접합 붕괴전압이 감소되어 동작전원이 고전압에서도 동작이 가능하게 할 수 있다.The present invention provides a semiconductor device capable of solving the problem of channel reduction during MOSFET operation by forming an insulating film under a source / drain under a strained silicon layer, and a method of manufacturing the same, which is a low power, low voltage, high speed device. In the reality that the minimum pitch size of the semiconductor device is required, the leakage current is solved and the resulting junction collapse voltage is reduced, thereby enabling the operating power source to operate even at a high voltage.

상기와 같은 본 발명의 반도체 소자 및 이의 형성 방법은 다음과 같은 효과가 있다.As described above, the semiconductor device and the method of forming the same according to the present invention have the following effects.

본 발명은 스트레인드 실리콘층(Strained Si) 내부 소오스/드레인 하부에 절연막을 형성함으로써, 점점 미세화 되고 있는 반도체 소자(Device)에서 Si의 격자에 의한 전자 및 홀의 이동도(mobility)의 감소를 개선함과 동시에 누설전류 (Leakage Current)와 그로 인해 존재하는 DIBL(Drain Induced Barrier Lowing)과 접합 붕괴전압 (Junction Breakdown Voltage)을 줄여 나노(Nano)급 이하 소자(Device)와 고전압 소자(Device)에서도 스트레인드 실리콘 소자(Strained Si MOSFET) 구현이 가능하게 할 수 있다. The present invention improves the reduction of mobility of electrons and holes due to the lattice of Si in an increasingly finer semiconductor device by forming an insulating film under the source / drain inside the strained Si layer. At the same time, strain is reduced in nano-grade devices and high-voltage devices by reducing leakage current and the resulting induced induced barrier low (DIBL) and junction breakdown voltage. It may be possible to implement a strained Si MOSFET.

Claims (4)

실리콘층 상에 게르마늄이 성장시켜 스트레인드 실리콘으로 형성된 기판;A substrate formed of strained silicon by growing germanium on a silicon layer; 상기 기판의 소정 부위에 형성된 소자 격리막;An isolation layer formed on a predetermined portion of the substrate; 상기 소자 격리막을 제외한 기판 상의 영역 중 소정 부위에 형성된 게이트 폴리층;A gate poly layer formed on a predetermined portion of an area on the substrate other than the device isolation layer; 상기 게이트 폴리층 양측에 대응되어 상기 기판에 정의된 소오스/드레인 영역; 및Source / drain regions defined on the substrate corresponding to both sides of the gate poly layer; And 상기 소오스/드레인 영역 하부에 형성되며, 상기 소자 격리막과 연결되는 절연막을 포함하여 이루어짐을 특징으로 하는 반도체 소자.And an insulating layer formed under the source / drain region and connected to the device isolation layer. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리 측벽에는 스페이서가 더 형성된 것을 특징으로 하는 반도체 소자.And a spacer is further formed on the gate poly sidewall. 제 2항에 있어서,The method of claim 2, 상기 소오스/드레인 영역은 상기 스페이서 및 게이트 폴리 양측의 액티브 영역에 형성되는 것을 특징으로 하는 반도체 소자.And the source / drain regions are formed in active regions at both sides of the spacer and the gate poly. 제 1 실리콘층 상에 게르마늄을 성장시켜 제 2 실리콘층을 형성하는 단계;Growing germanium on the first silicon layer to form a second silicon layer; 상기 제 2 실리콘층 상에 제 1 절연막을 증착하는 단계;Depositing a first insulating film on the second silicon layer; 상기 제 1 절연막 상부에 소정 부위가 오픈되는 제 1 감광막을 형성하는 단계;Forming a first photosensitive film having a predetermined portion open on the first insulating film; 상기 제 1 감광막을 마스크로 하여 상기 제 1 절연막 및 제 2 실리콘층의 소정 두께를 제거하여 홀을 형성하는 단계;Forming a hole by removing a predetermined thickness of the first insulating film and the second silicon layer using the first photosensitive film as a mask; 상기 제 1 절연막 및 제 1 감광막을 제거하는 단계;Removing the first insulating film and the first photosensitive film; 상기 홀 내벽에 제 2 절연막을 형성하는 단계;Forming a second insulating film on the inner wall of the hole; 상기 홀 하부의 제 2 절연막이 노출되도록 상기 제 2 실리콘층을 제거하는 단계;Removing the second silicon layer to expose the second insulating layer under the hole; 상기 제 2 실리콘층 상에 게르마늄을 성장시켜 제 3 실리콘층을 형성하는 단계;Growing germanium on the second silicon layer to form a third silicon layer; 상기 제 3 실리콘층, 제 2 실리콘층 및 제 1 실리콘층을 선택적으로 제거하고 제거된 영역에 절연막을 채워 소자 격리막을 형성하는 단계;Selectively removing the third silicon layer, the second silicon layer and the first silicon layer and filling an insulating layer with the removed region to form an isolation layer; 상기 제 3 실리콘층 상부 소정 부위에 게이트 절연막 및 게이트 폴리층을 형성하는 단계;Forming a gate insulating layer and a gate poly layer on a predetermined portion of the third silicon layer; 상기 게이트 절연막 및 게이트 폴리층 측벽에 스페이서를 형성하는 단계;Forming a spacer on sidewalls of the gate insulating layer and the gate poly layer; 상기 게이트 폴리층 및 스페이서를 마스크로 이용하여 상기 제 3 실리콘층 에 불순물 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.And forming an impurity region in the third silicon layer by using the gate poly layer and the spacer as a mask.
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