JPH09121053A - Vertical field-effect transistor and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease on resistance while ensuring the breakdown strength sufficiently between the source and the drain. SOLUTION: A lightly doped n<-> type drain region 2 is formed on a semiconductor substrate 1 of n<+> type silicon and p-type base regions 3 are formed, while spaced apart from each other, on the surface part of the drain region 2 followed by formation of a heavily doped n<+> type source region 4 in each base region 3. A pair of gate electrodes 16A, 16B are formed above each base region 3 while being split through an underlying insulation film. Directly under the split gate electrodes 16A, 16B in the drain region 2, a heavily doped n<+> region 12A having rectangular cross-section is formed while spaced apart from the underlying insulation film at the upper part thereof, touching the semiconductor substrate 1 at the lower part thereof and spaced apart from the base region 3 at each side part thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field effect transistor and a method for manufacturing the same, and more particularly, to reduce on-resistance while ensuring excellent high frequency operation characteristics such as short rise time and sufficient drain breakdown voltage. It is about technology.

[0002]

2. Description of the Related Art FIG. 15 shows a sectional structure of a conventional vertical field effect transistor. As shown in FIG. 15, a semiconductor substrate 1 made of n ⁺ type silicon is formed by an epitaxial growth method or the like. been n ^- -type drain region 2 made of low-concentration region is formed, the base region 3 made of p-type region is formed at a distance from each other in a surface portion of the drain region 2, each base region 3 n ⁺ The source regions 4 each formed of a high-concentration mold region are formed. still,
Drain region 2 and source region 4 in each base region 3
A gate electrode 16 is formed on the channel region, which is a region between and, via the under-gate insulating film 5. The base region 3 and the source region 4 are formed by double diffusion in a self-aligned manner using the gate electrode 16 as a mask.
The gate electrode 16 is covered with the gate coating insulating film 7. A source electrode 15 is formed on a region of the base region 3 that is not in contact with the gate electrode 16, and a drain electrode 17 is formed on the lower surface of the semiconductor substrate 1.

In the vertical field effect transistor having such a structure, by applying a voltage to the gate electrode 16, the channel region in the base region 3 is inverted and a current flows from the drain region 2 to the source region 4. Flows.

FIG. 16 shows the depletion layer region 3 when the voltage applied to the gate electrode 16 is below the threshold value and the gate electrode 16 is in the off state.
FIG. 17 shows the state of the depletion layer region 30 when the voltage applied to the gate electrode 16 is higher than the threshold value and the gate electrode 16 is in the ON state. That is, when the state shown in FIG. 16 changes from the off state shown in FIG. 17 to the state shown in FIG. 17, charges are attracted directly below the gate electrode 16, so that the depletion layer region 30 below the gate electrode 16 is pushed downward and split into left and right sides. However, a space s is formed between the depletion layer regions 30. Note that, in FIGS. 16 and 17, the extension of the depletion layer region 30 is indicated by the alternate long and short dash line.

FIG. 18 is a vertical field effect transistor which realizes high frequency operation characteristics superior to the vertical field effect transistor shown in FIG. 15 such as a shorter rise time (rise and fall times). The cross-sectional structure of is shown. As shown in FIG. 18, the vertical field effect transistor has a structure in which the gate electrodes 16A, 16 are divided into right and left.
B, and by reducing the area where the gate electrodes 16A and 16B contact the drain region 2,
Ingenuity has been made to reduce the capacitance between drains.

In the vertical field effect transistor as described above, since the switching is performed by the gate electrode, the driving current is small and high-speed switching is possible, and a large current density can be obtained. Have advantages.

[0007]

However, in the conventional vertical field effect transistor, there is a problem that the voltage supplied to the load becomes small because the ON resistance Ron is generally large. ON resistance Ron is
As shown in FIG. 19 in which FIG. 15 is partially enlarged, the sum of the resistance components existing in the current path between the drain and the source, that is, RS (source resistance), Rch (channel resistance), Ra (drain region) In the horizontal direction), Rb (vertical resistance in the drain region) and Rd (drain resistance), and the channel resistance Rch and the vertical resistance Rb in the drain region occupy most of them.

In particular, in a vertical field effect transistor having the left and right divided gate electrodes 16A and 16B as shown in FIG. 18, the depletion layer region 30 has a gate electrode 16A and a gate as shown in FIG. Since it spreads to a region immediately below the electrode 16B and the amount of accumulated charge attracted to the region directly below the electrode 16B decreases, the resistance of the horizontal resistance Ra in the drain region is added to the resistance Rb in the vertical direction in the drain region. Also has the problem of becoming larger.

It is relatively easy to set the channel resistance Rch to a sufficiently small value by increasing the gate voltage to the rated voltage (for example, 10 V). Therefore, in order to reduce the on-resistance Ron, it is required to reduce the vertical resistance Rb and the horizontal resistance Ra in the drain region as much as possible. That is, in the vertical field effect transistor having the divided gate electrode, the capacitance between the gate and the drain can be reduced and the rise time can be shortened, while the horizontal resistance Ra in the drain region is increased. There is a problem.

On the other hand, between the source-drain breakdown voltage BVds and the on-resistance Ron, generally Ron = KBVds
^Since the relationship of ^{2 to 3} exists, it is desired to reduce the horizontal resistance Ra and the vertical resistance Rb of the drain region while securing the breakdown voltage BVds between the source and the drain.

In view of the above, according to the present invention, the resistance in the horizontal direction Ra and the resistance in the vertical direction Rb of the drain region are secured while ensuring excellent high frequency operation characteristics such as short rise time and sufficient source-drain breakdown voltage. Smaller on resistance R
An object of the present invention is to provide a vertical field effect transistor capable of reducing ON and increasing a voltage supplied to a load, and a manufacturing method thereof.

[0012]

In order to achieve the above object, the present invention is to form a resistance-reducing region composed of a high concentration impurity region extending in the vertical direction between base regions in a drain region. .

Specifically, the means for solving the problems according to the invention of claim 1 is that a vertical field effect transistor is formed on a semiconductor substrate made of a high-concentration impurity region of a first conductivity type and on the semiconductor substrate. A drain region formed of a low-concentration impurity region of the first conductivity type, a base region formed of a pair of second conductivity type impurity regions formed on the surface of the drain region at intervals, and the pair of bases. A source insulating layer formed of a high-concentration impurity region of the first conductivity type formed inside each of the regions, and a region between the drain region and the source region in the pair of base regions with a gate insulating film interposed therebetween. And a gate electrode formed at a distance from each other and in contact with the first-conductivity-type high-concentration impurity region in the drain region and between the base region and the gate insulating film, respectively. It is an arrangement and a drag reduction region made of a high concentration impurity region of the first conductivity type formed at intervals.

According to the structure of the first aspect, since the gate electrode is divided, it is difficult to form the carrier storage layer in the drain region immediately below the gate electrode when the field effect transistor is turned on, so that the on-resistance becomes large. However, the resistance reduction is formed by the first-conductivity-type high-concentration impurity region formed in the drain region in contact with the first-conductivity-type high-concentration impurity region and spaced apart from each base region and the gate insulating film. Since the region is provided, when the state is changed from the off state to the on state, carriers of the first conductivity type, such as electrons, are transferred from the resistance reduction region formed of the high concentration impurity region of the first conductivity type to the region of the drain region immediately below the gate electrode. Is supplied, the depletion layer region under the gate electrode is pushed further downward, the carrier path becomes thicker and the carrier concentration becomes higher, which reduces the horizontal resistance Ra in the drain region. Further, since the resistance reducing region is formed of the high-concentration impurity region of the first conductivity type, the resistance Rb in the vertical direction is small in the resistance reducing region.

According to a second aspect of the present invention, the resistance reducing region is formed in a trapezoidal cross section in addition to the configuration of the first aspect.

[0016] Specifically, the means for solving the problems according to the invention of claim 3 is to provide a method for manufacturing a vertical field effect transistor according to the first method.
A first step of forming a first low-concentration impurity region of a first conductivity type on a semiconductor substrate made of a high-concentration impurity region of a conductive type; and a predetermined opening on the first low-concentration impurity region. A second step of forming a first resist pattern having a width, and ion-implanting a first conductivity type impurity into the first low-concentration impurity region using the first resist pattern as a mask, A third step of forming a resistance-reducing region composed of a high-concentration impurity region of the first conductivity type in the first low-concentration impurity region; and a second conductivity type of a second region above the first low-concentration impurity region. Forming a low-concentration impurity region, and forming a drain region composed of the first low-concentration impurity region and the second low-concentration impurity region,
A fifth step of forming a pair of gate electrodes on the drain region via a gate insulating film and spaced from each other; and a second resist between the pair of gate electrodes on the semiconductor substrate. A sixth step of forming a pattern, and ion implantation using the pair of gate electrodes and the second resist pattern as a mask so that a space is provided on the surface of the drain region and a space is formed between the drain region and the resistance reduction region. A seventh step of forming a pair of base regions made of a second conductivity type impurity region so as to be spaced apart from each other, and a pair of gate electrodes and a predetermined number of gate electrodes outside the pair of gate electrodes on the semiconductor substrate. Third at intervals
And an ion implantation process using the pair of gate electrodes, the second resist pattern and the third resist pattern as a mask to form a first resist pattern inside each of the pair of base regions. And a ninth step of forming a source region made of a conductive high-concentration impurity region.

According to the structure of claim 3, when the first conductivity type impurity is ion-implanted into the first low concentration impurity region using the first resist pattern having a predetermined opening width as a mask, the first low concentration impurity region is formed. A resistance-reducing region made of a high-concentration impurity region of the first conductivity type is formed in the region. afterwards,
When the second low-concentration impurity region of the first conductivity type is formed on the first low-concentration impurity region, a drain region including the first low-concentration impurity region and the second low-concentration impurity region is formed. On the upper side of the resistance reduction region in
There is a conductivity type low concentration impurity region. When ions are implanted using the pair of gate electrodes and the second resist pattern formed between the pair of gate electrodes as a mask, a space is provided between the drain region and the resistance reducing region. As a result, a pair of base regions made of the second conductivity type impurity region is formed. When ions are implanted using the pair of gate electrodes, the second resist pattern, and the third resist pattern, which is formed outside the pair of gate electrodes, at a predetermined interval as a mask, first ion implantation is performed inside each of the pair of base regions. A source region formed of a conductive type high concentration impurity region is formed.

According to a fourth aspect of the present invention, in the structure of the third aspect, the third step is a step of ion-implanting impurities of the first conductivity type while changing the incident energy while keeping the dose amount substantially constant. It is intended to add a configuration including the above.

According to a fifth aspect of the present invention, in the structure of the third aspect, the third step is to change the dose amount, increase the incident energy when the dose amount is large, and increase the incident energy when the dose amount is small. A configuration is added that includes a step of ion-implanting the first-conductivity-type impurities while reducing the size, and then thermally diffusing the ion-implanted first-conductivity-type impurities.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION A vertical field effect transistor according to a first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a cross-sectional view of a vertical field effect transistor according to the first embodiment. As shown in FIG. 1, a semiconductor substrate 1 made of n ⁺ type silicon is epitaxially grown. The drain region 2 formed of the formed n ⁻ -type low concentration region is formed, and the base regions 3 formed of p-type regions are formed on the surface of the drain region 2 at intervals from each other. A source region 4 made of an n ⁺ type high concentration region is formed. A pair of left and right gate electrodes 16A and 16B are formed on each base region 3 with an under-gate insulating film 5 interposed therebetween.
The contact area between the gate electrodes 16A and 16B and the drain region 2 is reduced. The region between the drain region 2 and the source region 4 in each base region 3, that is, the region immediately below the gate electrodes 16A and 16B in each base region 3 serves as a channel region. The base region 3 and the source region 4 are formed in a self-aligned manner by using the pair of gate electrodes 16A and 16B and the resist pattern formed so as to straddle these as a mask. Further, the pair of gate electrodes 16A and 16B is covered with the gate covering insulating film 7. A source electrode 15 is formed on a region of the base region 3 which does not face the gate electrode 16, and a drain electrode 17 is formed on the lower face of the semiconductor substrate 1.

A feature of the first embodiment is that in the drain region 2 formed to have a thickness of h = h1 + h2 by an epitaxial growth method or the like, a region immediately below between the left and right divided gate electrodes 16A and 16B is formed. , So that the upper portion is spaced from the under-gate insulating film 5 by h1 and the lower portion is in contact with the semiconductor substrate 1 and each side portion is spaced from the base region 3, the height is h2 and the width is N ⁺ with a rectangular cross section that is W1
A mold high concentration region 12A is formed.

As described above, since the n ⁺ -type high concentration region 12A having a rectangular cross section is formed in the drain region 2, the vertical resistance Rb and the horizontal resistance Ra in the drain region 2 are reduced. , The on-resistance Ron becomes smaller.

Resistance R in the vertical direction in the drain region 2
The reason why b becomes small is obvious. Therefore, the reason why the horizontal resistance Ra in the drain region 2 becomes small will be described below. In the conventional structure shown in FIG. 16, when 0 V is applied to the source electrode 15 and the voltage applied to the gate electrode 16 is increased, electrons as carriers are attracted to the depletion layer region 30 as shown in FIG. As a result, the depletion layer region 30 below the gate electrode 16
Are pushed downward and separated into left and right sides, a region having a large number of carriers having a space s is formed between the depletion layer regions 30, and the state changes from the off state to the on state. Since the drain region 2 is originally a low concentration region, the drain region 2
The horizontal resistance Ra at is large. However, FIG.
When the gate electrodes 16A and 16B are divided as shown in FIG. 8, the charges attracted by the gate electrodes 16A and 16B are small, and the space s between the depletion layer regions 30 is s.
Becomes smaller, the resistance Ra in the horizontal direction in the drain region 2 becomes larger. On the other hand, when the n ⁺ type high concentration region 12A is formed in the drain region 2 as in the first embodiment, electrons are supplied from the n ⁺ type high concentration region 12A, and the n ⁺ type high concentration region 12A is directly under the gate electrodes 16A and 16B. As the electric charge of the gate electrode 16 increases, as shown in FIG.
Since the depletion layer regions 30 on the lower sides of A and 16B are pushed further downward, the carrier path becomes thicker and the carrier concentration becomes larger, the horizontal resistance Ra in the drain region 2 becomes smaller.

By the way, in Japanese Patent Laid-Open 6-120509 discloses a vertical field effect transistor having a gate electrode as shown in FIG. 15 is not divided into two is shown, n ⁺ -type high concentration in FIG. 1 A structure has been reported in which the region 12A extends directly below the under-gate insulating film 5. That is, the structure in which the height h1 of the region above the drain region 2 in the first embodiment is 0 is reported.

Hereinafter, a vertical type having an n ⁺ type high concentration region where the height h1 of the upper side of the drain region 2 is 0 and having a pair of left and right gate electrodes 16A and 16B as in the first embodiment. When applied to the field effect transistor (hereinafter, the field effect transistor having such a structure is referred to as a comparative example), the low concentration of finite height h1 between the drain region 2 and the under-gate insulating film 5 is obtained. The difference from the vertical field effect transistor according to the first embodiment in which the region is provided will be described.

As shown in FIG. 14, in the first embodiment, the resistance reduction region is formed only by the n ⁺ -type high concentration region 12A, in the comparative example, the drag reduction region n ⁺ -type high Concentration region 12A and n ⁺ type high concentration region 12D
It is composed of both. Therefore, in the comparative example, the boundary surface 26 of the depletion layer region comes into contact with the resistance reduction region when the drain voltage Vd1 is relatively low, but in the first embodiment, the boundary surface 25 of the depletion layer region 25. Comes into contact with the resistance reduction region when the drain voltage Vd2 is relatively high. It can be said that the drain withstand voltage is the drain voltage until the boundary surfaces 25 and 26 of the depletion layer region come into contact with the resistance reduction region. Therefore, in the first embodiment, Vd2−Vd1 =
The drain breakdown voltage is increased by ΔV. If the drain voltage is made higher than the drain withstand voltage, the depletion layer region spreads to the channel region in the base region 3 formed of the p-type region having a higher impurity concentration than the n ⁻ -type low concentration region, so that the electric field in the channel region is increased. Since the electrons are accelerated due to the large electric field, the channel current cannot be controlled by the gate electrodes 16A and 16B.

In addition, the first embodiment is different from the comparative example in that
The capacitance Cgd between the gate and the drain is small, and the high frequency characteristics are excellent. That is, the capacitance between the gate and the drain is Cgd = ε × S / d (where ε: dielectric constant,
S: Area between electrodes, d: Distance between gate electrode and drain electrode), and the distance d between the gate electrode and drain electrode can be replaced with the distance between the gate electrode and the resistance reduction region. Compared to the comparative example, the first embodiment has a large distance between the gate electrode and the resistance-reduced region, and thus the capacitance Cgd between the gate and the drain is small, so that the high-frequency characteristics are excellent.

In the first embodiment shown in FIG. 1, each gate electrode 16A, 16B has a length of 0.5 μm, the distance between the gate electrodes 16A, 16B is 0.5 μm, and the thickness of the under-gate insulating film 5 is 0.5 μm. When the thickness is 10 nm, h 1 = 20 μm, h 2 = 5 μm, W of the n ⁺ -type high concentration region 12 A having a rectangular cross section,
When 1 = 0.3 μm, the on-resistance Ron is 0.0
5Ω, source-drain breakdown voltage BV _ds is 500 V,
It was possible to realize a cutoff frequency of 200 MHz.

A method of manufacturing the vertical field effect transistor according to the first embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 2, a drain region 2 of an n ⁻ type low concentration region is formed on a semiconductor substrate 1 of n ⁺ type silicon by an epitaxial growth method or the like.
After being formed to a thickness of 2, a resist pattern 20 having an opening having a width W1 corresponding to a region for forming an n ⁺ type high concentration region having a rectangular cross section is formed by photolithography. Then, using the resist pattern 20 as a mask, arsenic ions are implanted into the drain region 2 to form n ^{+ with a} rectangular cross section.
A high concentration region 12A of the mold is formed. The arsenic ion implantation conditions are such that the dose amount is kept substantially constant and the incident energy is changed from a high value to a low value in several steps.

Next, as shown in FIG. 3, the resist pattern 20 is removed by plasma ashing or the like, and the drain region 2 is further exposed by an epitaxial growth method or the like.
It is grown to a thickness of 1 to form a drain region 2 having a thickness of h1 + h2. The height h2 and width w1 of the n ⁺ -type high concentration region 12A having a rectangular cross section and the drain region 2
Thickness n1 of the additional n ⁻ -type low concentration region which is the upper part of the
Is determined from the mutual balance of desired ON resistance, high frequency characteristics, and drain breakdown voltage.

Next, as shown in FIG. 4, an under-gate insulating film 5 made of a thin oxide film is formed on the surface of the semiconductor substrate 1 made of n ⁻ type silicon, and then a large number of films are formed on the under-gate insulating film 5. A crystalline silicon film is formed on the entire surface. After that, the gate electrode 16 is divided into the left and right sides with respect to the polycrystalline silicon film.
Dry etching is performed using a resist pattern corresponding to the portions for forming A and 16B as a mask to form left and right divided gate electrodes 16A and 16B.

Next, as shown in FIG. 5, the first shape having a shape for closing the space between the left and right divided gate electrodes 16A and 16B.
After forming the resist pattern 18 of
Boron ions are implanted using A, 16B and the first resist pattern 18 as a mask, and then thermal diffusion is performed to form the base region 3. Next, the gate electrodes 16A, 1
After the second resist pattern 19 is formed on both sides of 6B at a predetermined interval, the gate electrodes 16A, 16B and the first resist pattern 19 are formed.
Using the second resist patterns 18 and 19 as masks, arsenic ions are implanted, and then thermal diffusion is performed to form the source regions 4. Then, as shown in FIG. 6, the first and second resist patterns 18 and 19 are removed by plasma ashing or the like.

Next, as shown in FIG. 7, a gate coating insulating film 7 is formed over the entire surface by a CVD method so as to cover the gate electrodes 16A and 16B, and then the under-gate insulating film 5 and the gate coating insulating film 7 are formed. An opening is formed in the source electrode formation region, and then the source electrode 15 is formed in the opening.

A vertical field effect transistor according to the second embodiment of the present invention will be described below with reference to FIG.

FIG. 9 is a sectional view of a vertical field effect transistor according to the second embodiment. In the second embodiment shown in FIG. 9, the same members as those in the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

A feature of the second embodiment is that h = h1 +
In the drain region 2 formed to have a thickness of h2, a region directly below the left and right divided gate electrodes 16A and 16B has a space of h1 between the upper part and the lower gate insulating film 5, and a lower part. Is in contact with the semiconductor substrate 1 and each side portion is spaced from the base region 3 by an n ⁺ -type high concentration region 12B having a trapezoidal cross section with a height of h2. Thus, by making the n ⁺ -type high concentration region 12B into a trapezoidal shape in which the cross-sectional shape becomes smaller as it goes upward, the distance between the n ⁺ -type high concentration region 12B and the base region 3 becomes almost constant in any part. The drain breakdown voltage can be improved. That is, the slope of the side surface of the n ⁺ type high-concentration region 12B becomes substantially parallel to the slope of the boundary surface of the depletion layer region 30 that develops from the base region 3, so that the drain breakdown voltage is further improved.

In the second embodiment shown in FIG. 9, the length of each gate electrode 16A, 16B is 0.5 μm, the distance between the gate electrodes 16A, 16B is 0.5 μm, and the thickness of the under-gate insulating film 5 is 0.5 μm. N ⁺ type high concentration region 1 at 10 nm
2B h1 = 20 .mu.m, h2 = 5 .mu.m, upper width W1 =
Assuming 0.3 μm, the on-resistance Ron is 0.05
Ω, a drain withstand voltage BV of 700 V, and a cutoff frequency of 200 MHz could be realized. As described above, in the second embodiment, the drain breakdown voltage higher than that in the first embodiment can be achieved.

A method of manufacturing a vertical field effect transistor according to the second embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 10, after forming a drain region 2 made of an n ⁻ type low concentration region with a thickness of h 2 on a semiconductor substrate 1 made of n ⁺ type silicon by an epitaxial growth method or the like, A resist pattern 20 having an opening of W2 is formed by photolithography in a portion corresponding to a region for forming an n ⁺ type high concentration region having a rectangular cross section. Then, arsenic ions are implanted using the resist pattern 20 as a mask to form an n ⁺ -type high concentration region 12C having a rectangular cross section. This arsenic implantation condition changes the incident energy from a high value to a low value in several steps, and also reduces the dose amount as the incident energy decreases.

Next, as shown in FIG. 11, the resist pattern 20 is removed by plasma ashing or the like, and then heat treatment is performed to form an n ⁺ -type high concentration region 12 having a rectangular cross section.
By diffusing C-doped arsenic ions, an n ⁺ -type high-concentration region 12B having a trapezoidal cross section is formed.

Next, as shown in FIG. 12, the drain region 2 is further grown to a thickness of h1 by the epitaxial growth method or the like to form the drain region 2 having a thickness of h1 + h2. The n ⁺ type high concentration region 12 having a rectangular cross section is used.
The height h2 and width W1 of C and the thickness h1 of the additional n ⁻ -type low-concentration region to be the drain region are determined from the mutual balance of desired ON resistance, high frequency characteristics, and drain breakdown voltage.

Next, as in the manufacturing method of the first embodiment, as shown in FIG. 13, after the under-gate insulating film 5 made of a thin oxide film is formed on the surface of the semiconductor substrate 1, the under-gate insulating film 5 is formed. The polycrystalline silicon film formed on the entire surface of the film 5 is dry-etched using the resist pattern as a mask to divide the gate electrodes 16A, 1 divided into left and right.
6B is formed. After that, ion implantation and thermal diffusion are performed to form the base region 3 and the source region 4, and then the source electrode 15 is formed. Note that FIG. 13 shows the state of the depletion layer region 30 when the vertical field effect transistor according to the second embodiment is in the on state.

[0045]

According to the vertical field effect transistor according to the first aspect of the present invention, when the state changes from the off state to the on state, the resistance reducing region to the drain region which are the high-concentration impurity regions of the first conductivity type are formed. Since the electrons are supplied to the region directly under the gate electrode in, the depletion layer region under the gate electrode is pushed further downward, the carrier path becomes thicker and the carrier concentration becomes higher, so that the horizontal resistance Ra in the drain region is increased. In addition, since the resistance reduction region is formed of the high-concentration impurity region of the first conductivity type, the resistance Rb in the vertical direction is reduced in the resistance reduction region.
For this reason, the on-resistance is reduced despite the division of the gate electrode, so that the on-resistance can be reduced while ensuring excellent high-frequency operating characteristics such as short rise time and sufficient gate-drain breakdown voltage. A vertical field effect transistor capable of increasing the voltage supplied to the load can be realized.

According to the vertical field effect transistor of the second aspect of the present invention, since the resistance reducing region has a trapezoidal cross section, when the drain-source voltage is increased, the channel in the base region is increased. Since the depletion layer region that develops from the region toward the resistance reduction region can spread more uniformly and longer than the resistance reduction region having a rectangular cross section, it becomes difficult for the depletion layer regions to contact each other. The breakdown voltage between them is improved.

According to the vertical field effect transistor of the third aspect of the present invention, the first conductivity type impurities are ion-implanted into the first low concentration impurity region, and the first low concentration impurity region is first ion-implanted. After forming the resistance reduction region including the high-concentration impurity region of one conductivity type, the first low-concentration impurity region is formed on the first low-concentration impurity region.
In order to form the second low-concentration impurity region of the conductivity type, the high-concentration first conductivity type which is in contact with the high-concentration impurity region of the first conductivity type on the semiconductor substrate in the drain region and is spaced from the gate insulating film. A resistance reducing region including a concentration impurity region is formed. Then, ion implantation is performed using the pair of gate electrodes and the second resist pattern as a mask to form a pair of base regions, and then ion implantation is performed using the pair of gate electrodes, the second resist pattern and the third resist pattern as a mask. To form a source region, the drain region is in contact with the first-conductivity-type high-concentration impurity region of the semiconductor substrate and is spaced apart from each base region and the gate insulating film. It is possible to reliably form the vertical field effect transistor according to the first aspect of the present invention, which includes the resistance-reducing region formed of the region.

According to the method of manufacturing a vertical field effect transistor according to the fourth aspect of the invention, the third step in the third aspect of the invention is to change the incident energy while keeping the dose amount substantially constant. Since the step of ion-implanting impurities of one conductivity type is included, the resistance reducing region having a rectangular cross section can be formed in the drain region.

According to the method of manufacturing the vertical field effect transistor according to the fifth aspect of the invention, the third step in the third aspect of the invention is to change the dose amount and to change the incident energy when the dose amount is large. Since a step of ion-implanting the first-conductivity-type impurity while making the incident energy small when the ion-implantation is made large and the dose amount is small, and thermally diffusing the ion-implanted first-conductivity-type impurity,
In the drain region, the lower part is doped with a relatively high concentration of impurities, while the upper part is doped with a relatively low concentration of impurities, and thermal diffusion reduces the trapezoidal cross-sectional resistance of the drain region. Regions can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a vertical field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 3 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 4 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 5 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 6 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the first embodiment.

FIG. 8 is a cross-sectional view illustrating a state of a depletion layer region when the vertical field effect transistor according to the first embodiment is in an on state.

FIG. 9 is a sectional view of a vertical field effect transistor according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the second embodiment.

FIG. 11 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the second embodiment.

FIG. 12 is a cross-sectional view showing a step in the method of manufacturing the vertical field effect transistor according to the second embodiment.

FIG. 13 is a cross-sectional view illustrating a state of a depletion layer region when the vertical field effect transistor according to the second embodiment is in an on state.

FIG. 14 is a cross-sectional view illustrating a state of a depletion layer region when the vertical field effect transistors according to the first embodiment and the comparative example are in an on state.

FIG. 15 is a cross-sectional view of a first conventional vertical field effect transistor.

FIG. 16 is a cross-sectional view illustrating a state of a depletion layer region when a first conventional vertical field effect transistor is in an off state.

FIG. 17 is a cross-sectional view illustrating a state of a depletion layer region when a first conventional vertical field effect transistor is in an on state.

FIG. 18 is a cross-sectional view illustrating a state of a depletion layer region when a second conventional vertical field effect transistor is in an on state.

FIG. 19 is a partial enlarged cross-sectional view illustrating a resistance component of a first conventional vertical field effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor substrate 2 drain region 3 base region 4 source region 5 under-gate insulating film 7 gate coating insulating film 12A n ⁺ type high concentration region of rectangular cross section 12B n ⁺ type high concentration region of trapezoidal cross section 12C n of rectangular cross section ⁺ Type high concentration region 12D n ⁺ type high concentration region added in the comparative example 15 source electrode 16, 16A, 16B gate electrode 17 drain electrode 18 first resist pattern 19 second resist pattern 20 resist pattern 25 depletion layer region Interface 26 Depletion layer boundary 30 Depletion area

Claims (5)

[Claims] 1. A semiconductor substrate made of a high-concentration impurity region of the first conductivity type, a drain region made of a low-concentration impurity region of the first conductivity type formed on the semiconductor substrate, and a surface portion of the drain region. A base region formed of a pair of second conductivity type impurity regions spaced apart from each other, and a source region formed of a first conductivity type high concentration impurity region formed inside each of the pair of base regions. A gate electrode formed on the region of the pair of base regions between the drain region and the source region with a gate insulating film interposed therebetween, and the drain region having the first conductive layer. A high-concentration impurity region of the first conductivity type formed in contact with the high-concentration impurity region of the first type and formed at intervals between the base region and the gate insulating film. A vertical field-effect transistor characterized by comprising: 2. The vertical field effect transistor according to claim 1, wherein the resistance reducing region is formed in a trapezoidal cross section. 3. A first step of forming a first low-concentration impurity region of the first conductivity type on a semiconductor substrate made of a high-concentration impurity region of the first conductivity type, and the first low-concentration impurity region. A second step of forming a first resist pattern having a predetermined opening width on the upper surface of the first resist pattern, and ion-implanting impurities of the first conductivity type in the first low-concentration impurity region using the first resist pattern as a mask. By implanting the first impurity into the first low-concentration impurity region,
A third step of forming a resistance-reducing region made of a conductive type high-concentration impurity region; and forming a second conductive type second low-concentration impurity region on the first low-concentration impurity region, A fourth step of forming a drain region including a first low concentration impurity region and a second low concentration impurity region; and a pair of gate electrodes on the drain region with a gate insulating film interposed therebetween. A fifth step of forming a second resist pattern between the pair of gate electrodes on the semiconductor substrate, and a sixth step of forming a second resist pattern between the pair of gate electrodes and the second resist pattern. By implanting ions as a mask, a pair of base regions composed of impurity regions of the second conductivity type are formed so as to be spaced apart from each other on the surface of the drain region and also spaced apart from the resistance reduction region. A seventh step of forming a mask region, and an eighth step of forming a third resist pattern on the semiconductor substrate outside the pair of gate electrodes at a predetermined distance from the pair of gate electrodes. A source region formed of a high-concentration impurity region of the first conductivity type inside each of the pair of base regions by implanting ions using the pair of gate electrodes, the second resist pattern, and the third resist pattern as a mask. And a ninth step of forming a vertical field effect transistor. 4. The method according to claim 3, wherein the third step includes a step of ion-implanting a first conductivity type impurity while changing an incident energy while keeping a dose amount substantially constant. Method for manufacturing vertical field effect transistor. 5. The third step is to ion-implant the impurities of the first conductivity type while changing the dose amount and increasing the incident energy when the dose amount is large and decreasing the incident energy when the dose amount is small. The method of manufacturing a vertical field effect transistor according to claim 3, further comprising the step of thermally diffusing the ion-implanted first conductivity type impurities.