JP2005175011A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, in an area below an extension region of a field effect transistor, the concentration of dopants which form a halo region is high, thereby forms a neutral region, resulting in increasing parasitic capacitance and that a substrate suspension effect becomes noticeable in an SOI transistor. <P>SOLUTION: Before or after forming a gate electrode 8 of the field effect transistor, dopants of a first conductivity type are introduced in a lower concentration than that of dopants of a second conductivity type of the halo region 6 at a zero or small tilt angle into a position 13 corresponding to the area below the extension region 5 of the first conductivity type in a semiconductor layer 3. Consequently, the dopants of the second conductivity type which form the halo region 6 are compensated for below the extension region 5, resulting in reducing the neutral region. As a result, parasitic capacitance between the source/drain region 4-side face and the neutral region is reduced and parasitic capacitance between the extension region 5 and the neutral region is also reduced. Moreover, in the SOI transistor, the substrate suspension effect is suppressed and thereby the operation becomes stable. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor having a structure (silicon-on-insulator structure, SOI structure) having a layered semiconductor substrate in which a transistor is formed on an insulator, and the method thereof. It relates to a manufacturing method.

  In a fine field-effect transistor used in LSI, for the purpose of improving element characteristics by suppressing the short channel effect, etc., an extension region in which a first conductivity type impurity is shallowly introduced at a high concentration, and A halo region which is a second conductivity type region adjacent to the extension region is provided. An example of a field effect transistor provided with an extension region and a halo region is shown in FIG. FIG. 38 shows an example in which these structures are applied to an SOI-MOSFET.

  Here, the SOI-MOSFET refers to a field effect transistor formed on a semiconductor layer over an insulating substrate. SOI is an acronym for English notation of “silicon on insulator” and refers to a technique of providing a semiconductor layer (referred to as an SOI layer) on an insulator. A transistor employing SOI technology is referred to as an SOI-MOSFET. The purpose of using the SOI technology for a field effect transistor is to increase the speed and power consumption of an electronic circuit, particularly an integrated circuit.

  FIG. 38B is a top view, and FIG. 38A is a cross-sectional view taken along the line B-B ′ of FIG. A gate electrode 8 is provided on a semiconductor layer 3 of a substrate (referred to as an SOI substrate) having a structure in which an embedded insulating layer 2 and a semiconductor layer 3 are stacked on a supporting substrate 1 with a gate insulating film 7 interposed therebetween. An extension region 5 (also referred to as a source / drain extension region) into which a first conductivity type impurity is introduced at a high concentration is provided on the surface side of the semiconductor layer 3 on both sides of the gate electrode, and is provided outside the extension region 5. As a result, the source / drain region 4 into which the high-concentration first conductivity type impurity is introduced deeper than the extension region is formed. The semiconductor layer under the gate electrode sandwiched between the two extension regions 5 forms a channel formation region 9 into which a second conductivity type impurity is introduced at a low concentration. When an appropriate voltage is applied to the gate electrode 8, a channel of the first conductivity type is formed in the channel formation region 9, and the transistor becomes conductive. A halo region 6 in which a second conductivity type impurity is introduced at a higher concentration than the other regions of the channel formation region is provided in a region of the channel formation region 9 that is in contact with the tip of the extension region 5. However, the halo region 6 is a part of the low concentration region of the second conductivity type, and the impurity concentration of the halo region is lower than that of the source / drain region and the extension region. The purpose of providing the halo region is to suppress the short channel effect.

The support substrate 1 is typically a silicon substrate, the buried insulating layer 2 is typically SiO ₂ , and the semiconductor layer 3 is typically single crystal silicon. In this specification, the first conductivity type refers to the same conductivity type as the carrier forming the channel in the field effect transistor, and the second conductivity type refers to a conductivity type different from the first conductivity type.

FIG. 41 shows a structure disclosed in Japanese Patent Laid-Open No. 11-87719 (Patent Document 1) as an example of an SOI-MOSFET having a configuration different from the structure of FIG. In the structure of FIG. 41, the first conductivity type region 12 in contact with the buried insulating film 2 is provided below the channel formation region 9 in the semiconductor layer 3 of the transistor of FIG. The method of manufacturing the transistor of FIG. 41 described in Patent Document 1 will be described with reference to FIG. 42 in the case of an n-channel transistor in which the first conductivity type is n-type. First, an n-type impurity is uniformly implanted by ion implantation into an SOI substrate composed of the support substrate 1, the buried insulating layer 2, and the semiconductor layer 3, and annealed at 900 ° C. for 60 minutes to make the semiconductor layer n-type (see FIG. 42 (a)). Next, a p-type impurity is introduced into the surface portion of the semiconductor layer 3 to form the gate insulating film 7 on the surface of the semiconductor layer 3 (FIG. 42B). Next, B ⁺ ions are implanted by oblique ion implantation to form a p-type halo region 6 (FIG. 42C). Subsequently, As ⁺ is ion-implanted vertically to form the extension region 5, and then the gate electrode sidewall 23 is formed. Then, As ⁺ is ion-implanted vertically using the gate electrode 8 and the gate electrode sidewall 23 as a mask. Thereby, the source / drain region 4 is formed, and the configuration of FIG. 41 is obtained.
JP 11-87719 A

(First issue)
The halo region 6 is normally formed by implanting second conductivity type impurity (symbol 15) ions obliquely using the gate electrode 8 as a mask after the gate electrode 8 is formed. In this case, due to the property of oblique ion implantation, the concentration of the second conductivity type impurity is high in the region away from the gate electrode, and the concentration of the second conductivity type impurity is relatively low in the portion covered with the gate electrode.

  This situation is shown in FIG. FIG. 39 shows the impurity distribution in the A-A ′ cross section of FIG. Compared to the region of the semiconductor layer that is covered with the gate electrode and does not have the extension region ("region III" in FIG. 38A), the region that is not covered with the gate electrode and is located below the extension region (FIG. 38). In (A) “region II”), the concentration of the second conductivity type impurity forming the halo region is high. The impurity concentration of the second conductivity type in the halo region is adjusted so as to satisfy the necessary concentration in the “region III” where the channel is formed. As a result, in the “region II”, the transistor operation is particularly required. Impurity concentrations may increase to the extent that they are not.

On the other hand, the neutral region 10 which is a region where the semiconductor layer is not depleted is present in the substrate of the field effect transistor. This is shown in FIGS. 40 and 43. Since the neutral region acts as a substrate electrode, a parasitic capacitance C ₁ is provided between the neutral region 10 and the extension region 5, and a parasitic capacitance C ₂ is provided between the side surface of the source / drain region 4 and the neutral region 10. Is attached. Note that the carrier concentration in the neutral region is substantially the same as the impurity concentration.

  Here, when the impurity concentration increases in the lower region (region II) of the extension region 5, the neutral region 10 expands. When the neutral region is enlarged, the neutral region is expanded below the extension region. As a result, the upper end of the neutral region approaches the extension region, the parasitic capacitance C1 between the lower end of the extension region and the neutral region increases, the side surface of the source / drain region and the neutral region approach, and the source / drain region There arises a problem that the parasitic capacitance C2 between the side surface and the neutral region increases.

In the case of an SOI-MOSFET, when the thickness of the SOI layer is reduced or the impurity concentration of the channel region is lowered, a transistor having no neutral region called a fully depleted SOI-MOSFET is obtained. However, when the SOI layer is relatively thick, or when the impurity concentration of the channel region is high, even a SOI-MOSFET becomes a transistor called a partially depleted SOI-MOSFET having a neutral region. The increase in the impurity distribution in the lower portion of the extension region 5, the parasitic capacitance _{C 1} and the parasitic capacitance _{C 2} is described above that increases problem likewise occurs with conventional MOSFET on a bulk substrate even in the partial depletion type SOI-MOSFET To do. FIG. 40A shows a case of a partially depleted transistor, and FIG. 43 shows a case of a transistor on a normal bulk substrate, but the problem is the same.

When the parasitic capacitance C ₁ and the parasitic capacitance C ₂ is a parasitic capacitance around the neutral region is increased, reduces the operating speed of the circuit, power consumption is a problem that increases. Therefore, it is necessary to take measures to suppress the parasitic capacitance around the neutral region in the field effect transistor in which the halo region is formed by oblique ion implantation.

(Second issue)
In the partially depleted SOI-MOSFET, surplus second conductivity type carriers generated by impact ionization or the like (holes in an n-channel transistor; in this specification, the conductivity type of a carrier forming a channel is defined as a first conductivity type). Is accumulated in the neutral region, the potential distribution in the SOI layer changes due to the electric field caused by the excess second conductivity type carriers, and abnormalities such as threshold voltage fluctuations and current value fluctuations occur. appear. Such an abnormal operation is called a substrate floating effect. If the impurity concentration is high in the region below the extension region 5 (region II), a large amount of holes accumulate in the neutral region, so that the amount of potential fluctuation in the transistor increases and the substrate floating effect increases. This is shown in FIG. In FIG. 40B, an arrow indicates an electric field by excess second conductivity type carriers accumulated in the neutral region. The direction of the electric field is drawn for the case of an n-channel transistor. The opposite is true for p-channel transistors.

The substrate floating effect also occurs when the potential of the neutral region electrostatically coupled to the drain electrode varies with the variation of the drain voltage. When the neutral region in this case is large, the parasitic capacitance C ₁ and the parasitic capacitance C ₂ is increased, change in the potential is increased, the substrate floating effect is conspicuous.

  Therefore, from the viewpoint of reducing the substrate floating effect of the SOI-MOSFET, it is necessary to take measures to reduce the neutral region in the transistor in which the halo region is formed by oblique ion implantation.

(Third issue)
The field effect transistor of FIG. 41 described in Patent Document 1 is characterized in that since the deep first conductivity type region 12 is provided below the channel formation region, it is difficult to form a neutral region in the channel formation region. .

  However, due to the influence of the deep first conductivity type region 12 provided below the channel formation region 9 below the gate electrode, the potential of the channel formation region varies compared to the case where the deep first conductivity type region 12 is not provided. As a result, the potential distribution of the transistor fluctuates. More specifically, the threshold voltage of the transistor changes from the case where the normal design without the first conductivity type region 12 is provided, and in the specifications such as the threshold voltage, Performance compatibility is lost.

  Further, when the deep first conductivity type region 12 is provided, the potential increases near the interface between the semiconductor layer 3 and the buried insulating layer 2 located below the channel formation region (in the case of an n-channel transistor or in the case of a p-channel transistor). As a result, leakage current (referred to as a punch-through current, a back channel current, etc.) through a region where the potential has increased (in the case of an n-channel transistor, a region in which the potential has decreased in the case of a p-channel transistor). There is also a problem that it becomes easier to flow.

  Therefore, a technique for reducing the neutral region of the SOI-MOSFET without providing the first conductivity type region below the channel formation region is desired.

[Features of the invention]
The field effect transistor of the present invention includes a gate electrode provided on a semiconductor region via a gate insulating film, a second conductivity type channel formation region in a region including the lower portion of the gate electrode in the semiconductor region, A region in which a first conductivity type impurity having a higher concentration than the second conductivity type impurity in the second conductivity type channel formation region is introduced into a region including the surface of the semiconductor region in contact with the gate electrode in the two conductivity type channel formation region A field effect transistor having a region where the first conductivity type impurity is introduced in a direction perpendicular to the surface of the semiconductor region at a position in contact with the gate electrode in the region where the first conductivity type impurity is introduced. It has a maximum value of the second conductivity type impurity concentration at the lower position.

  In the field effect transistor of the present invention, the region into which the first conductivity type impurity is introduced is an extension region that is in contact with the gate electrode, and a region that is farther from the gate electrode than the extension region. Source / drain regions into which the first conductivity type impurity is introduced to a position deeper than the extension region, and a region of the first conductivity type in a region below the extension region in the second conductivity type channel formation region. It has a halo counter ion implantation region into which the counter impurity is introduced at a lower concentration than the second conductivity type impurity at the same position.

  In the field effect transistor of the present invention, the maximum counter impurity concentration is below the position of the pn junction at the lower end of the extension region in the direction perpendicular to the surface of the semiconductor region at the position having the extension region. It has a value.

  In the field effect transistor of the present invention, the second conductivity type channel formation region sandwiched between the extension regions on both sides below the gate electrode is the first conductivity type at any position in the vertical direction. The counter impurity is not introduced.

  In the field effect transistor of the present invention, a gate electrode is provided on a semiconductor surface via a gate insulating film, and an extension in which a first conductivity type impurity is introduced at a high concentration on the semiconductor surface on both sides of the gate electrode. A field effect transistor having a source / drain region in which impurities of the first conductivity type are introduced at a high concentration outside the extension region and deeper than the extension region, and the second conductivity type region under the extension region Has a halo counter ion implantation region into which a first conductivity type impurity having a lower concentration than the second conductivity type impurity concentration is introduced over a certain depth, and is sandwiched between two extension regions. The position is characterized by not having the halo counter ion implantation region at any depth of the semiconductor.

  In the field effect transistor of the present invention, the semiconductor region is formed on an insulator. The field effect transistor of the present invention is formed over an SOI substrate.

  In the field effect transistor of the present invention, the semiconductor region is provided in a bulk semiconductor substrate.

  In the field effect transistor of the present invention, the second conductivity type is formed at a lower concentration than the first conductivity type impurity introduced for the extension region in the region surrounding the lower portion of the extension region and the side portion on the gate electrode side. It has a halo region into which impurities are introduced, and has a maximum value of the counter impurity concentration in the halo region in a direction perpendicular to the surface of the semiconductor region at the position where the extension region is provided.

  In the field effect transistor of the present invention, a halo region in which a second conductivity type impurity is introduced at a lower concentration than the extension region is formed so as to surround the tip of the extension region and the lower portion of the extension region. It is characterized by.

  The field effect transistor manufacturing method of the present invention includes a gate insulating film forming step of forming a gate insulating film on a semiconductor region, a gate electrode forming step of forming a gate electrode on the gate insulating film, A second conductivity type channel formation region forming step of forming a second conductivity type channel formation region at a position including a lower side of the gate electrode; and a first surface side of the semiconductor region at a position not having the gate electrode. An extension region forming step of forming a first conductivity type extension region by introducing a conductivity type impurity, and a second conductivity type impurity is introduced into the lower portion of the extension region and the side portion having the gate electrode in the semiconductor region; A halo region forming step for forming a halo region, and a lower portion of the extension region in the semiconductor region. A halo counter ion implantation region forming step of forming a halo counter ion implantation region by introducing a conductivity type counter impurity, wherein the halo counter ion implantation region forming step includes the extension region. The counter impurity of the first conductivity type is introduced so as to have the maximum value of the counter impurity concentration below the extension region in a direction perpendicular to the surface.

  In the field effect transistor manufacturing method of the present invention, the halo counter ion implantation region forming step is lower than the second conductivity type impurity at a position having the maximum value of the counter impurity concentration in the halo counter ion implantation region. The counter impurity of the first conductivity type is introduced into the concentration.

  In the field effect transistor of the present invention, after the formation of the gate electrode of the field effect transistor, a low concentration or a low concentration or zero angle or lower inclination of the first conductivity type extension region with respect to the vertical direction of the semiconductor region. A medium concentration of the first conductivity type impurity is introduced.

  In the method for manufacturing a field effect transistor according to the invention, the semiconductor region is provided on an insulator.

  In the field effect transistor manufacturing method of the present invention, the semiconductor region is a bulk semiconductor substrate.

  The field effect transistor manufacturing method of the present invention includes an insulating film forming step of forming an insulating film on the semiconductor region, and the extension region forming step and the halo region forming step after the insulating film forming step. And a step of forming the halo counter ion implantation region.

  In the field effect transistor manufacturing method of the present invention, the extension region forming step is performed without the insulating film formed by the insulating film forming step.

  In the field effect transistor manufacturing method of the present invention, the halo counter ion implantation region forming step is performed after the gate electrode forming step.

  In the field effect transistor manufacturing method of the present invention, the halo counter ion implantation region forming step is performed after forming side walls on both sides of the gate electrode.

  In the field effect transistor manufacturing method of the present invention, the halo region forming step introduces the second conductivity type impurity by oblique ion implantation.

  Note that in the present invention and this specification, upper and lower terms use the side on which the gate electrode is provided as the upper side with respect to the substrate (the support substrate 1 and the semiconductor substrate 22). The term “vertical” refers to the perpendicular to the surface of the semiconductor layer 3 or the semiconductor substrate 22 in the field effect transistor.

[Action]
An object of the present invention is to reduce the second conductivity type impurity concentration under the extension region without forming the first conductivity type region in the channel region in a field effect transistor having a halo region, particularly an SOI-MOSFET having a halo region. Compensating is to reduce the neutral region and improve the characteristics of the field effect transistor.

More specifically, by reducing the neutral region, the parasitic capacitance C ₁ formed between the neutral region and the extension region is formed between the side surface of the source / drain region and the neutral region. reducing the parasitic capacitance C _2, to measure the reduction in the improvement of the operating speed and power consumption, and it is an object to reduce the substrate floating effect in SOI-MOSFET.

  In the present invention, before or after the formation of the gate electrode, the first conductivity type having a lower concentration than the second conductivity type impurity in the halo region at a position corresponding to the extension region of the first conductivity type at a zero degree or a small inclination. Impurities are introduced. As a result, the second conductivity type impurity is compensated in the lower portion of the extension region, so that a neutral region is not formed under the extension or in the vicinity of the extension region.

  As a result, the neutral region is reduced, and the parasitic capacitance between the side surface of the source / drain region and the neutral region and the parasitic capacitance between the extension region and the neutral region are both reduced. It operates at higher speed and lower power than a circuit using transistors.

  Further, since the neutral region is reduced, the substrate floating effect is suppressed and the operation of the transistor is stabilized. In addition, deterioration of various characteristics associated with the substrate floating effect, such as an increase in leakage current, is suppressed.

  In particular, if a low-concentration first conductivity type impurity is introduced under the extension region after the gate is formed, the first conductivity type impurity is not introduced into the channel region. The variation in threshold voltage can be reduced or eliminated.

  After the formation of the gate electrode, a low-concentration or medium-concentration first-conductivity type impurity is introduced below the first-conductivity-type extension region at zero or a small inclination. As a result, the second conductivity type impurity is compensated in the lower portion of the extension region, so that a neutral region is not formed under the extension or in the vicinity of the extension region.

  As a result, the neutral region is reduced, and the parasitic capacitance between the side surface of the source / drain region and the neutral region and the parasitic capacitance between the extension region and the neutral region are both reduced. It operates at higher speed and lower power than a circuit using transistors.

  In addition, since the neutral region is reduced, the substrate floating effect is suppressed in the field effect transistor formed over the insulator, and the operation of the transistor is stabilized. In addition, deterioration of various characteristics associated with the substrate floating effect, such as an increase in leakage current, is suppressed.

  Further, since the counter implantation is not performed below the channel region, the change in the potential distribution of the channel region accompanying the counter implantation is extremely small, and the variation in transistor characteristics such as the threshold voltage is also small. In addition, since the halo counter ion implantation is performed at a low concentration that does not reverse the conductivity type of the second conductivity type region to the first conductivity type, no leakage current is generated by the halo counter ion implantation.

(First embodiment)
The best mode for carrying out the invention will be described by taking as an example the case where a semiconductor region in which a field effect transistor is formed is a semiconductor layer on an insulator.

[Construction]
A typical embodiment of the invention relating to the structure of a transistor is shown in FIGS. 1 (a) and 1 (b). 1B is a top view, and FIG. 1A is a cross-sectional view taken along the line BB ′ of FIG. 1B. In an SOI substrate in which a buried insulating layer 2 and a semiconductor layer 3 are stacked on a supporting substrate 1, a gate electrode 8 is provided on the semiconductor layer 3 with a gate insulating film 7 interposed therebetween. The semiconductor layer on both sides of the gate electrode is provided with an extension region 5 into which a first conductivity type impurity is introduced at a high concentration above the gate electrode, and on the outside of the extension region 5 is a high concentration first conductivity type impurity. However, the source / drain region 4 introduced deeper than the extension region is formed. The semiconductor layer under the gate electrode sandwiched between the two extension regions 5 forms a channel formation region 9 in which impurities of the second conductivity type are introduced at a medium concentration or a low concentration. When an appropriate voltage is applied to the gate electrode 8, a channel of the first conductivity type is formed in the channel formation region 9, and the transistor becomes conductive. In the channel formation region 9, a halo region 6 into which a second conductivity type impurity is moderately introduced is provided in a region in contact with the tip of the extension region 5.

  The halo region 6 refers to a region including the region indicated as the halo counter ion implantation region 13 in the drawing. That is, the halo counter ion implantation region 13 is a partial region in the halo region 6. The concentration of the first conductivity type impurity in the high conductivity concentration first conductivity type region composed of the extension region 5 and the source / drain region 4 is the same as that in the channel formation region 9 in which the second conductivity type impurity is introduced at a low concentration. It is higher than the impurity concentration of the second conductivity type. The halo region 6 is a part of the second conductivity type low concentration region, and the second conductivity type impurity concentration of the halo region is lower than that of the source / drain region and the extension region.

  In the halo region 6, a halo counter ion implantation region 13 in which a first conductivity type impurity is implanted at a low concentration is provided at a position located below the extension region 5. The first conductivity type impurity is introduced into the halo counter ion implantation region 13, but the concentration of the first conductivity type impurity does not exceed the concentration of the second conductivity type impurity at each position in the halo counter ion implantation region 13. As shown in FIG. 1A, in the lateral cross section of the transistor, the portion where the source / drain region 4 is formed is the region I, the extension region 5 and the halo counter ion implantation region 13 are formed. A region consisting of the region II, the channel formation region 9 and the semiconductor layer therebelow is referred to as a region III.

  Note that, in the step of injecting the second conductivity type impurity to form the halo region 6, the range 32 into which the second conductivity type impurity (referred to as a halo impurity in this specification) is introduced is shown in FIG. In addition, in the step of implanting the first conductivity type impurity to form the extension region 5, the region 33 into which the first conductivity type impurity is introduced is shown in FIG. 2B, and the halo counter ion implantation region 6 is formed. In order to do this, in the step of implanting the first conductivity type impurity, the ranges 34 into which the first conductivity type impurity (referred to herein as a halo counter impurity) is introduced are shown in FIG.

  3A and 3B show the impurity concentration distribution in the A-A ′ cross section of FIG. 1A, which is a cross section including the halo counter-doped region. FIG. 3A shows the concentration of the first conductivity type impurity other than the halo counter ion implantation, the concentration of the second conductivity type impurity, and the concentration of the first conductivity type impurity by the halo counter ion implantation. The halo counter ion implantation refers to ion implantation for forming a halo counter ion implantation region. The first conductivity type impurities other than the halo counter ion implantation in FIG. 3A are halo counter ions such as ion implantation for forming source / drain regions and ion implantation for forming extension regions. A first conductivity type impurity introduced in a process other than ion implantation for forming an implantation region. In the A-A ′ cross section of FIG. 1A, “first conductivity type impurities other than halo counter ion implantation” are mainly first conductivity type impurities that form source / drain regions. The second conductivity type impurity in FIG. 3A is an impurity introduced to form a halo region, a channel ion implantation step (implantation for adjusting the impurity concentration of the channel region, mainly for the entire element region). Second conductivity, such as impurities introduced by ion implantation) and impurities introduced by well implantation step (ion implantation for forming wells, which is usually performed by ion implantation with high energy into the element region and element isolation region) Refers to type impurities. The definition regarding these impurities is the same also in the same drawing (FIG. 36A) described later. FIG. 3B shows a net impurity concentration distribution which is an absolute value of a difference between the first and second conductivity type impurity concentrations.

  The first conductivity type halo counter impurity is introduced into the region II below the extension region, but the concentration of the halo counter impurity does not exceed the concentration of the second conductivity type impurity (FIG. 3A). As a result of the first conductivity type halo counter impurity compensating for the second conductivity type halo impurity, the net concentration of the second conductivity type impurity is lowered while maintaining the second conductivity type in the region II. This is shown in FIG. The second conductivity type impurity having a higher concentration than that of the channel formation region is introduced into the halo region 6. From the viewpoint of the net impurity concentration of the second conductivity type, the second conductivity type impurity in the halo region 6 excluding the halo counter ion implantation region is introduced. The net impurity concentration of the second conductivity type is higher than the net impurity concentration of the second conductivity type in the channel formation region, but the second conductivity type net impurity concentration in the halo counter ion implantation region of the halo region 6 is different from that of the channel formation region. It may be lower than the net impurity concentration of the second conductivity type in the region.

  In the prior art, the impurity concentration of the second conductivity type in the region II is extremely high, reflecting that the halo region is formed by oblique ion implantation. In the invention shown in FIGS. In FIG. 5, since the second conductivity type impurity is compensated by the first conductivity type halo counter impurity, the net impurity concentration of the second conductivity type impurity is suppressed. In the region where the net impurity concentration of the second conductivity type impurity is low, it is difficult to form a neutral region. As a result, it is difficult to form a neutral region below the extension region 5 and near the tip of the extension region 5. The range of 10 is reduced. This is illustrated in FIGS. 4 (a) and 4 (b). In the conventional form, the range of the neutral region 10 is large as shown in FIGS. 40 (a) and 40 (b).

When the neutral region is reduced, the distance between the extension region 5 and the neutral region 10 is increased, so that the parasitic capacitance C ₁ between the neutral region 10 and the extension region 5 is reduced and the source / drain region 4 is Since the distance of the neutral region 10 is increased, the parasitic capacitance C ₂ between the side surface of the source / drain region 4 and the neutral region 10 is reduced. As a result, the first problem is solved.

  In addition, when the neutral region is reduced, when the substrate floating effect occurs, the amount of carriers accumulated in the neutral region (carriers having a conductivity type opposite to that of the normal channel) is reduced, and the neutral region is reduced. Since the electric field from the accumulated carriers is two-dimensionally dispersed as shown in FIG. 4B, the threshold fluctuation due to the substrate floating effect is suppressed, so that the second problem is solved.

  In the prior art of Patent Document 1 (FIG. 41), since the lower part of the channel region is set to the first conductivity type in order to reduce the neutral region, the potential distribution of the channel region is the first conductive type in the lower part of the channel region. Although the transistor characteristics such as threshold voltage change in comparison with the case where it is not formed into a mold, in the present invention, halo counter ion implantation is performed only under the extension region 5 and the first conductive material is formed under the channel region. Since the impurity of the type is not implanted, the change in the potential distribution of the channel region due to the addition of the structure of the present invention to a normal transistor is extremely small, and fluctuations in transistor characteristics such as threshold voltage are suppressed. The problem is solved.

[Production method]
A typical embodiment of a method for manufacturing a transistor will be described with reference to FIGS. 5 and 6 are cross-sectional views at positions corresponding to the BB ′ cross-section of FIG. 1B, which is a drawing for explaining the structure of the transistor. A second conductivity type impurity serving as a channel impurity is introduced into the SOI substrate in which the insulating layer 2 and the semiconductor layer 3 are embedded on the support substrate 1 by ion implantation, and then the surface of the semiconductor layer 3 is thermally oxidized or in nitrogen. A gate insulating film 7 is provided by heat treatment or the like, polysilicon is deposited by a CVD method, and the gate electrode 8 is formed by processing silicon by an etching process such as normal lithography and RIE (reactive ion etching). Subsequently, the side surface of the gate electrode 8 is thermally oxidized thinly to form the sidewall insulating film 14 (at this time, the surface of the semiconductor layer 3 is also oxidized simultaneously). Subsequently, the second conductivity type impurity 15 is introduced by oblique ion implantation using the gate electrode 8 as a mask to form the halo region 6 into which the second conductivity type impurity is introduced at a low concentration, and the configuration shown in FIG. Get.

  Subsequently, the first conductivity type impurity 16 is ion-implanted perpendicularly using the gate electrode as a mask to form the extension region 5 into which the first conductivity type impurity is introduced at a high concentration, and the configuration of FIG. obtain.

  Subsequently, the first conductivity type impurity 17 is ion-implanted vertically so as to spread under the extension region 5 using the gate electrode as a mask, and the halo counter ion implantation in which the first conductivity type impurity is introduced at a low concentration is performed. Region 13 is formed to obtain the configuration of FIG.

  Subsequently, a gate electrode sidewall 23 made of an insulator is formed by film deposition by CVD or the like and a sidewall formation step by etchback, and first conductivity type impurities are ion-implanted using the gate electrode 8 and the gate electrode sidewall 23 as a mask, After forming the source / drain regions 4 into which the first conductivity type impurity is introduced at a high concentration, the heat treatment is performed to activate the impurities, and then a metal such as cobalt is deposited by a deposition technique such as sputtering, and then the heat treatment is performed. Then, unreacted metal is removed by etching to form a silicide region 18 on the gate electrode 8 and the source / drain regions, an interlayer insulating film 19 is subsequently formed, and the contact metal 20 and the wiring 21 are formed. Formed by a normal contact formation process and wiring formation process, the configuration shown in FIG. 6B is obtained.

[Example of element dimensions and process conditions]
An example of element dimensions and process conditions will be described with reference to FIGS. The surface of the SOI substrate in which the buried insulating layer 2 having a thickness of 100 nm and the semiconductor layer 3 made of silicon having a thickness of 50 nm are stacked on the support substrate 1 is sacrificially oxidized by 5 to 10 nm, and boron serving as a channel impurity is dosed 3 ×. It introduce | transduces by ion implantation on the conditions of about 10 ^{< 12} > cm ^<-2 > ^-3 * 10 ^{< 13} > cm ^<-2 >.

Next, the surface of the semiconductor layer 3 is thermally oxidized to provide a gate insulating film having a thickness of 2 nm. Next, 150 nm of polysilicon is deposited by CVD (Chemical Vapor Deposition, Chemical Vapor Deposition), and this is performed by normal lithography and RIE (Reactive Ion Etching, Reactive Ion Etching) processes. The gate electrode 8 having a gate length of 100 nm is formed by processing to a width of 100 nm (where the width refers to the width in the source-drain direction, which corresponds to the gate length). Subsequently, the side surface of the gate electrode 8 is thermally oxidized thinly to form a sidewall insulating film 14 having a thickness of 2 to 10 nm. Subsequently, as the second conductivity type impurity ions 15, boron is implanted by obliquely ion-implanting BF2 ions under conditions of a dose amount of 5 × 10 ¹² cm ⁻² to 3 × 10 ¹³ cm ⁻² using the gate electrode 8 as a mask. A halo region 6 introduced into silicon and doped with boron, which is an impurity of the second conductivity type, is formed at a low concentration to obtain the configuration shown in FIG. The angle of oblique ion implantation for forming the halo region is typically 10 to 45 degrees, more typically 20 to 30 degrees.

Subsequently, as the first conductivity type impurity ions 16, arsenic is ion-implanted vertically with an implantation energy of 1 to 5 keV and a dose amount of 2 × 10 ¹⁴ cm ⁻² to an amount of 2 × 10 ¹⁵ cm ⁻² . The extension region 5 into which arsenic, which is an impurity, is introduced at a high concentration is formed to obtain the configuration shown in FIG.

Subsequently, as the first conductivity type impurity ions 17, arsenic ions are implanted with a gate electrode as a mask, and an implantation energy of 100 keV and a dose of 4 × 10 ¹² cm ⁻² to 3 × 10 ¹³ cm ⁻ so as to spread below the extension region 5. Ions are implanted vertically in an amount of about ² to form a halo counter ion implantation region 13 into which arsenic, which is a first conductivity type impurity, is introduced at a low concentration, thereby obtaining the configuration of FIG.

Subsequently, 100 nm of SiO ₂ is deposited by the CVD method, and this is etched back to form the gate electrode side wall 23, and arsenic as the first conductivity type impurity is implanted using the gate electrode 8 and the gate electrode side wall 23 as a mask. Ions are implanted at an energy of 50 to 200 keV and a dose of 1 to 3 × 10 ¹⁵ cm ⁻² to form a source / drain region 4 into which a first conductivity type impurity is introduced at a high concentration. Subsequently, a heat treatment is performed at 1000 ° C. for several seconds to activate the impurities introduced by ion implantation. Subsequently, cobalt is deposited by sputtering to a thickness of 10 to 25 nm, and heat treatment is performed, so that a silicidation reaction proceeds between cobalt and polysilicon forming the gate and between cobalt and silicon forming the source / drain. Subsequently, unreacted metal is removed by etching to form a silicide region 18 on the top of the gate electrode 8 and the top of the source / drain region, and then SiO ₂ is deposited by CVD to have a thickness of 500. An interlayer insulating film 19 having a thickness of ˜1000 nm is formed, and the interlayer insulating film 19 is planarized by a CMP method (chemical mechanical polishing method), and then a contact metal 20 and a wiring 21 are formed by a normal contact forming process and a wiring forming process. 6B is obtained.

  Here, implantation of second conductivity type impurity ions 15 for forming a halo region (referred to as halo ion implantation in this specification) and implantation of first conductivity type impurity ions 16 for forming an extension region (this specification). Three ion implantation steps of the first conductivity type impurity ions 17 for forming the halo counter-doped region (referred to as “halo counter ion implantation” in this specification) in this order. Although an example of implementation is shown, the order of the three may be arbitrarily changed.

  In general, in the extension ion implantation with a high dose amount, the amount of contaminants such as metal adhering to or invading the wafer during ion implantation is the largest. In the case where importance is placed on preventing it from being carried in, extension ion implantation may be performed last among the three. For the same reason, the halo counter ion implantation, the halo ion implantation, the extension ion implantation, and the one with the lowest dose may be performed in this order (examples are shown in FIGS. 7A and 7B in the order of steps). 8 (a) and 8 (b), which correspond to the drawings of FIGS.

  Further, in the case where the surface of the semiconductor layer is made amorphous by extension ion implantation, ion channeling can be reduced in an ion implantation process performed subsequently by performing ion implantation through the formed amorphous layer. For the purpose of preventing channeling, one or both of halo ion implantation and halo counter ion implantation may be performed after extension ion implantation.

  It is to be noted that impurity ions implanted in a portion where each region (source / drain region, etc.) forming a field effect transistor is sufficiently activated to make the semiconductor have the first or second conductivity type. Generally, after obtaining a process such as a heat treatment, in the description of the manufacturing process in this specification, after the point in time when ions forming the region are implanted even before the activation of the impurity, the region Use the name. For example, even after halo ion implantation and before activation by heat treatment, a region into which an impurity forming a halo region is introduced is called a halo region.

[Simulation results on performance improvement]
In the n-channel partially depleted SOI-MOSFET having a gate length of 70 nm, a silicon layer thickness of 50 nm, and a p-type (second conductivity type) halo region shown in FIG. A proposed structure in which a halo counter ion implantation region is formed by adding a step of ion implantation of As ⁺ ions (first conductivity type) at 100 keV and a dose amount of 6.0 × 10 ¹² cm ⁻² , and the As ⁺ ion implantation is performed. FIG. 10A and FIG. 10B show the simulation results of the potential distribution and the drain current in the two conventional structures in which the halo counter ion implantation region is not formed and is not added.

  FIG. 10A shows a potential distribution in the lateral direction in the silicon layer at a position 5 nm above the back side interface of the silicon layer. In the figure, the portion where the potential distribution is flat at the center is the neutral region, but the width of the neutral region is clearly reduced in the proposed structure. When the neutral region is reduced, the parasitic capacitances indicated as C1 and C2 in FIG. 4A are reduced, and it can be seen that the parasitic capacitance is reduced in the proposed structure.

  Further, in both the conventional structure and the proposed structure, the ion implantation conditions such as halo ion implantation and channel ion implantation that control the impurity distribution in the channel formation region are the same as shown in FIG. In addition, in the proposed structure, the off-current is improved by about one digit. This is because in the conventional structure, holes generated by impact ionization of channel carriers at the drain end accumulate in the neutral region, thereby lowering the threshold voltage of the transistor and increasing the off-current. On the other hand, in the proposed structure, as shown in FIG. 10A, the neutral region is small and the amount of accumulated holes is small, so that the threshold voltage is prevented from lowering and the off-current is reduced.

[Form of impurity distribution]
A desirable form of the first conductivity type impurity distribution formed by the halo counter ion implantation will be described with reference to FIGS. 11 to 13 show the impurity distribution in the vertical direction (the cross section indicated by the symbol CC ′ in FIG. 1) at the position where the extension region exists.

  As shown in FIGS. 11 to 13, in the transistor of the present invention, the position where the concentration of the first conductivity type impurity introduced by the halo counter ion implantation becomes maximum is below the pn junction at the lower end of the extension region. Is desirable. This is because the object of the present invention is to reduce the net impurity concentration (absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity concentration) in the second conductivity type region below the extension region. This is because the device characteristics are improved. In the present invention, it is most desirable to set the impurity concentration of the second conductivity type to always exceed the concentration of the first conductivity type impurity introduced by the halo counter ion implantation below the lower end of the extension region.

  When the halo region is formed, the halo region having a relatively high concentration of the second conductivity type impurity is distributed over a certain depth below the extension region. In order to effectively reduce the net impurity concentration in such a halo region, it is desirable to introduce the first conductivity type impurity into a region in a certain depth direction where the second conductivity type impurity concentration is distributed. This requirement can be realized by positioning the position where the first conductivity type impurity concentration is maximum below the position of the pn junction at the lower end of the extension region.

  FIG. 11A shows the case where the SOI layer is thin, or the case where the halo counter ion implantation is performed with high energy, and the first conductivity type impurity introduced by the halo counter ion implantation in the SOI layer 3 is inside the SOI layer. , Monotonically increasing in the depth direction. In this case, the position where the first conductivity type impurity concentration becomes maximum is the interface between the SOI layer 3 and the buried insulating layer 2 or in the vicinity of the interface (for the reason different from the ion implantation condition, that is, the influence of the interface in the very vicinity of the interface). This is because the impurity concentration may decrease, so it is not necessarily the maximum at the interface, and is lower than the pn junction at the lower end of the extension region. Further, the concentration of the first conductivity type impurity introduced by the halo counter ion implantation does not exceed the concentration of the second conductivity type impurity.

  FIG. 11B shows the case where the SOI layer is thick or the halo counter ion implantation is performed at a slightly low energy, and the first conductivity type impurity introduced by the halo counter ion implantation is in the depth direction within the SOI layer. Increases toward the bottom, reaches the maximum below the pn junction at the lower end of the extension region, and then decreases toward the depth. The concentration of the first conductivity type impurity introduced by the halo counter ion implantation does not exceed the concentration of the second conductivity type impurity.

  FIG. 12 shows an example of the configuration shown in FIG. 11B, in which the first conductivity type impurity introduced by the halo counter ion implantation forms the halo region in the vicinity of the tail in the depth direction of the halo region. This is a case where it exceeds the second conductivity type impurity introduced for the purpose. However, the sum of the second conductivity type impurity concentration introduced by channel ion implantation and the concentration of the second conductivity type impurity introduced by halo ion implantation (ion implantation for forming a halo region) (in some cases) Does not exceed the sum of the concentration of the second conductivity type impurities introduced by well ion implantation, which is higher than the channel ion implantation), so that the concentration of the second conductivity type impurities is the first conductivity type. The concentration of impurities is exceeded, and the semiconductor layer is kept to be of the second conductivity type.

  In the present invention, by setting the impurity concentration of the second conductivity type below the lower end of the extension region so as to always exceed the concentration of the first conductivity type impurity introduced by the halo counter ion implantation, the extension region below the extension region is set. It is most desirable from the viewpoint of preventing leakage current due to punch-through to prevent the first conductivity type region from being formed at a position away from the center. However, if the first conductivity type region is thin in the depth direction so that the entire first conductivity type region located in the pn junction is depleted, there is little influence even if it is formed. In addition, in the case of a transistor that does not easily cause punch-through, such as a transistor with a long gate length, a large first conductivity type region that does not deplete may be formed.

  FIG. 13 shows the vertical distribution of the impurity concentration in the same cross section as FIG. 11 and FIG. 12 as the sum of the first conductivity type impurity concentration (extension region formation, halo counter ion implantation, or other reasons for the distribution of impurities distributed for other reasons). The total concentration) is indicated by a broken line, and the total concentration of second conductivity type impurities (the total concentration of impurities distributed due to halo region formation, channel ion implantation, well ion implantation, or other reasons) is indicated by a solid line. is there. FIG. 13A corresponds to FIG. 11A, and FIG. 13B corresponds to FIG. 11B.

  As shown in FIGS. 13A and 13B, the transistor of the present invention has a minimum value in the vertical distribution of the first conductivity type impurity at the position where the extension region is formed. Above the position where the minimum value is obtained (on the silicon surface side), the first conductivity type impurity introduced to form the extension region is distributed at a high concentration. Below the position where the minimum value is taken (on the lower layer interface side of the silicon layer), the first conductivity type impurity concentration monotonously increases in the depth direction, and reaches a maximum at the interface between the SOI layer and the buried insulating layer or near the interface ( FIG. 13 (a)), or the first conductivity type impurity concentration once increases in the depth direction, takes a maximum value, and then decreases again (FIG. 13 (b)). 13A and 13B, the concentration of the first conductivity type impurity at the position where the first conductivity type impurity concentration is maximum below the position where the minimum value is obtained. Does not exceed the second conductivity type impurity concentration. The minimum value is located near the pn junction at the lower end of the extension region.

  FIG. 14 shows the vertical distribution of the net impurity concentration in the same cross section as FIG. 11 and FIG. FIG. 14 is drawn assuming that the SOI is thin or the energy of the halo counter ion implantation is high as in FIG. 11A. However, the contents described below with reference to FIG. The same applies to the case where the SOI layer is thick or the energy of the halo counter ion implantation is low as assumed in FIG. The semiconductor is the first conductivity type above the pn junction at the lower end of the extension region (silicon surface side), and the semiconductor is the second conductivity type below the pn junction at the lower end of the extension region (on the silicon lower interface side). In the present invention, the net impurity concentration in the second conductivity type region below the pn junction at the lower end of the extension region is suppressed by introducing the first conductivity type halo counter ion implantation. The first conductivity type impurity is introduced below the extension region, but the second conductivity type is maintained below the pn junction. Thereby, in the second conductivity type region below the extension region, the neutral region is reduced, and the element characteristics are improved.

The conditions of simulating the device characteristics for the structure of FIG. 9, that is, the case where the ion species is As ⁺ , the implantation energy is 100 keV, and the dose is 6.0 × 10 ¹² cm ⁻² as the halo counter ion implantation conditions. When the vertical distribution of the net impurity concentration shown in FIG. 14 is examined at the position of the portion (cross section AA ′ in FIG. 9), the maximum value of the net impurity concentration in the second conductivity type region (see FIG. 14) is The net impurity concentration at 5.5% and the maximum halo counter ion implantation concentration position (see also FIG. 14; in this case, the lower interface of the silicon layer) was reduced by 17.6%. Further, when only the dose is changed to 1.8 × 10 ¹³ cm ⁻² with the same structure and process conditions, the maximum value of the net impurity concentration in the second conductivity type region (see FIG. 14) is 29. %, And the net impurity concentration at the position where the halo counter ion implantation concentration was maximum (see also FIG. 14; in this case, the lower interface of the silicon layer) was 66% lower. Further, the reduction of the neutral region and the reduction of the substrate floating effect are performed by device simulation under any of the above conditions (when the dose is 6.0 × 10 ¹² cm ⁻² and 1.8 × 10 ¹³ cm ⁻² ). It was recognized in.

  In the case where there is a pn junction under the source / drain region (for example, in the case of FIG. 35A or FIG. 35B), in the vertical distribution of the first conductivity type impurity formed by halo counter ion implantation, The position where the impurity concentration is maximum is provided, for example, at a position deeper than the pn junction at the lower end of the extension region and shallower than the pn junction at the lower end of the source / drain region.

  The above discussion in [Difference of impurity distribution] is based on the assumption that the first and second conductivity type impurities are activated in a state where the transistor is completed. The same argument holds for the state where the second conductivity type impurity is not activated.

  In the manufacturing method, in the above discussion, “maximum position of halo counter ion implantation concentration” is “maximum value of impurity distribution implanted at the time of halo counter ion implantation”, and “pn junction at the lower end of the extension region” is “extension”. “Maximum value of impurity distribution” such as “position where pn junction at the lower end of the region is formed”, “position where halo region is formed” and “position where halo region is formed” is “maximum value of impurity distribution implanted during the ion implantation” For each “region”, conditions in the ion implantation process such as implantation energy may be set so as to satisfy the condition read as “position where the region is formed”.

(Second embodiment)
The best mode for carrying out the invention will be described by taking as an example a case where a semiconductor region in which a field effect transistor is formed is a bulk semiconductor substrate.

  The structure of the present invention may be adopted not only for a transistor formed on an insulator but also for a transistor formed on a normal bulk substrate. In the transistor on the bulk substrate, since the substrate floating effect does not usually occur, the second problem does not exist. However, the first and third problems also occur in the transistor on the bulk substrate, which is effective in solving the problem.

  In the first embodiment, the case where the transistor is formed on the semiconductor layer on the insulator is described. However, in the second embodiment, the case where the substrate on which the transistor is formed is a normal bulk substrate is described. . The structure and manufacturing method of the second embodiment are the same as those of the first embodiment except that the structure of the substrate is different.

The case where the first embodiment is applied to a transistor on a bulk substrate is shown in FIG. 15, FIG. 16, and FIG. FIG. 15 is a drawing corresponding to FIG. 1 of the first embodiment, and shows a typical structure when applied to a transistor on a bulk substrate. FIG. 16 is a drawing corresponding to FIG. 2 of the first embodiment, and when applied to a transistor on a bulk substrate, a range (symbols 32, 33, and 34) in which impurities in each region are distributed is indicated by a hatch region. Show. FIG. 17 is a drawing corresponding to FIG. 4A of the first embodiment and shows the effect of the invention. The impurity distribution is the same as in FIG. 4 for explaining the first embodiment. Even when the present invention is applied to the transistor on the bulk substrate, the effect of the invention that the parasitic capacitances C ₁ and C ₂ are reduced as compared with the case of the normal structure (FIG. 43) does not change.

  As shown in FIGS. 15, 16, and 17, the second embodiment is an SOI substrate including three layers of a support substrate 1, a buried insulating layer 2, and a semiconductor layer 3 in the manufacturing method of the first embodiment. Is replaced with a semiconductor substrate 22.

  The manufacturing method of the second embodiment is obtained by replacing the SOI substrate including the support substrate 1, the buried insulating layer 2, and the semiconductor layer 3 with the semiconductor substrate 22 in the manufacturing method of the first embodiment. (The figures corresponding to FIGS. 5 and 6 of the first embodiment are shown in FIGS. 18 and 19, respectively). That is, the present invention relates to a structure of a field effect transistor formed on a semiconductor and a method for manufacturing the same when the substrate is an SOI substrate (described in the first embodiment) and a normal semiconductor substrate. It can be implemented for any of (described in the second embodiment). The semiconductor substrate 22 is usually a silicon substrate, but other materials may be used. The semiconductor substrate 22 may be a semiconductor substrate having a multilayer structure made of silicon and another semiconductor material.

  In the field effect transistor on the bulk substrate, since the substrate floating effect does not normally occur, the second problem does not occur. However, the first problem and the action and effect for solving the second problem are described in the first implementation. It is the same as the form. Further, since the substrate impurity concentration is low and, as a result, the substrate resistance is high, the substrate floating effect occurs as in the case of the SOI transistor, and the present invention solves the second problem when the second problem needs to be solved. It is effective for.

  In this embodiment, the SOI substrate in the first embodiment is simply replaced with a bulk substrate. Therefore, the impurity distribution is the same as that in the first embodiment except that the lower interface does not exist in the silicon layer. It is the same. In the form of the impurity distribution in the first embodiment, “the lower silicon interface” may be read as “below the substrate”. However, since there is no buried insulating layer in the second embodiment, there is no structure (FIG. 11A) in which the halo counter ion-implanted first conductivity type impurity monotonously increases in the depth direction in the semiconductor. . Similarly, the structure in which the first conductivity type impurity monotonously increases in the depth direction below the pn junction at the lower end of the extension (FIG. 11A) does not exist in the second embodiment.

  An example of the impurity distribution in the vertical direction below the extension region in the second embodiment is shown in FIG. FIG. 20A corresponds to FIG. 11B of the first embodiment. FIG. 20B shows the case where the second conductivity type impurity concentration is higher than the first conductivity type impurity concentration in a part of the substrate, and in the case where punch-through is unlikely to occur as in the first embodiment. It may be applied.

(Third embodiment)
In the first embodiment and the second embodiment, halo ion implantation, halo counter ion implantation, and extension ion implantation may be performed according to the following embodiment.

  Although an embodiment in which three types of ion implantation, that is, halo ion implantation, halo counter ion implantation, and extension ion implantation are performed after the sidewall insulating film 14 is provided on the side surface of the gate electrode 8 has been described with reference to FIGS. One or more of the three types of ion implantation may be performed before the sidewall insulating film 14 is formed.

  Further, a manufacturing method in which the sidewall insulating film 14 is not provided may be used. A mode in which the sidewall insulating film 14 is not provided is shown in FIGS. FIG. 21A and FIG. 21B respectively correspond to FIG. 6A and FIG. 6B which are drawings for explaining the manufacturing method in the first embodiment.

  Further, after removing a portion of the sidewall insulating film 14 formed on the surface of the semiconductor layer 3 by an etching process such as RIE, a process of performing one or more of the three kinds of ion implantation processes is used. Also good. Since extension ion implantation is performed with low energy, if there is an insulating film on the semiconductor layer 3, there is a problem that many ions do not reach the semiconductor layer but enter the insulating film on the semiconductor. A portion of the insulating film 14 formed on the surface of the semiconductor layer 3 can be solved by an etching process such as RIE. An example is shown in FIGS. 22 (a) and 22 (b). FIG. 22A and FIG. 22B correspond to FIG. 6A and FIG. 6B, respectively, which are drawings for explaining the manufacturing method in the first embodiment.

Alternatively, the sidewall insulating film 14 may be formed on the side surface of the gate electrode 8 by depositing an insulating film such as SiO ₂ or Si ₃ N ₄ by a CVD method or the like. For example, instead of forming the sidewall insulating film 14 by thermal oxidation, an insulating film such as SiO ₂ or Si ₃ N ₄ is deposited thinly (for example, 5 nm to 20 nm) by a deposition process such as a CVD method, and then an etch back process by RIE. After removing the material formed on the surface of the semiconductor layer, one or more of the three types of ion implantation processes may be performed. Its form is shown in FIGS. 23 (a) and 23 (b). FIG. 23A and FIG. 23B respectively correspond to FIG. 6A and FIG. 6B which are drawings for explaining the manufacturing method in the first embodiment. In the method in which the sidewall insulating film 14 is provided by depositing an insulating film such as SiO ₂ or Si ₃ N ₄ by a CVD method or the like, the sidewall insulating film 14 is also formed on the side surface of the gate insulating film 7. The CVD method is easier to form a thicker insulating film than thermal oxidation. This method is effective when a thicker sidewall insulating film is formed.

  Alternatively, halo counter ion implantation may be introduced by oblique ion implantation. In this case, the halo counter ion implantation region expands to the channel side as compared with the case of having the same sidewall insulating film thickness implanted vertically (FIG. 24).

  In general, after the three types of ion implantation of halo ion implantation, halo counter ion implantation, and extension ion implantation are completed, the gate electrode sidewall 23 having a thick film structure with a single layer or a multilayer structure is formed. After that, ion implantation for forming the source / drain region is performed. After the gate electrode sidewall 23 is formed and the ion implantation for forming the source / drain region is performed, and the gate electrode sidewall 23 is removed. Thus, a step of performing one or more of the three types of ion implantations of halo ion implantation, halo counter ion implantation, and extension ion implantation may be used.

(Fourth embodiment)
In the first embodiment, the second embodiment, and the third embodiment, halo counter ion implantation may be performed according to the following mode. In the fourth embodiment, after forming the gate electrode sidewall 23, halo ion implantation and extension ion implantation are performed, and then the second sidewall (symbol 23 in FIG. 25, symbol 23 in FIG. Symbol 24 in FIG. 27 and symbol 24) in FIG. 28 are formed, and halo counter ion implantation is performed on the gate electrode 8 and the second sidewall using the gate electrode sidewall 23 as a mask. According to the method of the first and second embodiments, if the impurity implanted with the halo counter ion is excessively spread to the channel region side according to the conditions such as halo ion implantation and channel ion implantation, the fourth embodiment is limited to the halo counter ion. This has the effect of preventing the implanted impurities from spreading to the channel region side. The fourth embodiment is effective as a method for adjusting the positional relationship between the halo counter ion implantation region and the extension region.

  25A, FIG. 26A, FIG. 27A, and FIG. 28A are drawings for explaining the manufacturing method in the first embodiment, respectively. Corresponds to (a). Drawing explaining embodiment, Drawing 25 (b), Drawing 26 (b), Drawing 27 (b), and Drawing 28 (b) are drawings explaining a manufacturing method in a first embodiment, respectively (b) ).

After the gate electrode side wall 23 is formed, halo ion implantation and extension ion implantation are performed, and then the gate electrode side wall 23 is formed on the side surface of the gate electrode 8, and the gate electrode 8 and the gate electrode side wall 23 are used as masks to extend below the extension region. FIG. 25 shows a case where halo counter ion implantation is performed. In this case, the halo counter ion-implanted region tends to recede from the tip of the extension region. Thus Extension - the effect of reducing neutral region capacitance C ₁ is small, deep source / drain - effect of reducing the neutral region capacitance C ₂ is not different from the first and second embodiments. In this case, it is preferable to use an impurity that is easily diffused in the halo counter ion implantation so that the halo counter ion implantation tip is closer to the channel side than the tip of the source / drain region 4. For example, in the case of an n-channel transistor, it is preferable to use phosphorus. The thickness of the gate sidewall 23 is typically 50 nm to 100 nm. The gate sidewall 23 is an insulating film such as SiO ₂ or Si ₃ N ₄ or a multilayer film made of these insulating films.

  In another embodiment, the halo counter ion implantation is performed by oblique ion implantation in the embodiment shown in FIG. This is shown in FIG. In this embodiment, by adjusting the implantation angle of the halo counter ion implantation, the position of the halo counter ion implantation region is brought closer to the tip of the extension region or the tip of the extension region than in the embodiment shown in FIG. It can extend to the channel region side.

  In the embodiment of FIG. 25 or FIG. 26, when the gate electrode side wall 23 is a multilayer film, halo counter ion implantation may be performed when a part of the sidewall is formed. Examples thereof are shown in FIGS. In the case of removing the insulating film deposited on the semiconductor except for the side surface of the gate electrode by performing etch back after depositing the first gate side wall 24, the side surface of the gate electrode is removed after depositing the first gate side wall 24. FIG. 28 shows the case where the insulating film deposited on the semiconductor is not removed. The first gate sidewall 24 and the second gate sidewall 25 may be made of the same material or different materials.

  In the fourth embodiment, when the side wall (symbol 23 or 24) of the gate electrode at the time of halo counter ion implantation is thickened, the position of the halo counter ion implantation region can be retreated from the tip of the extension region. Implantation is performed by oblique ion implantation, and by adjusting the implantation angle, the position of the halo counter ion implantation region can be brought closer to the tip of the extension region or can be extended to the channel region side than the tip of the extension region. In the fourth embodiment, by adjusting the film thickness of the side wall of the gate electrode and the implantation angle of the halo counter ion implantation, the halo counter ion implantation region can be arranged at an arbitrary position with good controllability. It is.

(Fifth embodiment)
The first to fourth embodiments may be applied to a transistor in which a part or all of the extension region 5 is above the semiconductor surface of the channel formation region. An example is shown in FIG.

  The structure of the fifth embodiment is manufactured by adding a step of digging down the semiconductor in the channel formation region to the manufacturing method of forming the transistor of the first to fourth embodiments. Alternatively, in the structure of the fifth embodiment, in the manufacturing method for forming the transistors of the first to fourth embodiments, a region protruding from the semiconductor surface of the channel formation region in the extension region is formed by epitaxial growth. Manufactured by. In the manufacturing method in which a part or all of the extension region is formed by epitaxial growth, halo counter ion implantation may be performed before epitaxial growth, or halo counter ion implantation may be performed after epitaxial growth.

(Sixth embodiment)
In the first to fifth embodiments, a part of the first conductivity type impurity introduced by the halo counter ion implantation is introduced at a low concentration so that the channel formation region under the gate electrode can maintain the second conductivity type. An embodiment will be described.

  If the transistor has a long gate length, the concentration of the second conductivity type impurity introduced into the channel region is high, or the like, and the leakage current due to punch-through is relatively difficult to flow, or the channel formation region below the gate electrode due to transistor specifications When a low-concentration first conductivity type impurity may be introduced, or when the threshold voltage may change to some extent by the introduction of the first conductivity type impurity due to transistor specifications, the channel formation region below the gate electrode The first conductivity type impurity may be introduced at a low concentration to such an extent that the second conductivity type can be maintained.

  The structure is shown in FIG. 30, FIG. 31 and FIG. 30 and 32, a region surrounded by a broken line is a region 35 into which the first conductivity type impurity is introduced. Note that the region 35 is not limited to the lower portion of the extension, and in some cases, is not limited to the inside of the halo region. Therefore, the region 35 is called a counter ion implantation region with respect to the halo counter ion implantation region 13 of the first embodiment. Further, ion implantation for forming the counter ion implantation region 35 is referred to as counter ion implantation, and impurities implanted to form the counter ion implantation region 35 are referred to as counter impurities. The counter ion implantation region, the counter ion implantation, and the counter impurity are concepts including a halo counter ion implantation region, a halo counter ion implantation, and a halo counter impurity, respectively. When the counter impurity is limited to the inside of the halo region, the counter ion implantation region, the counter ion implantation, and the counter impurity are referred to as a halo counter ion implantation region, a halo counter ion implantation, and a halo counter impurity, respectively.

  The counter ion implantation regions below the extension region may be connected to each other (FIG. 30A) or may not be connected (FIG. 30B). However, in the present invention, the counter ion implantation region refers to a region where the second conductivity type impurity exceeds the first conductivity type impurity. By preventing the second conductivity type impurity from exceeding the first conductivity type impurity, the counter ion implantation region is prevented from becoming the first conductivity type, and as a result, leakage current due to punch-through is prevented. In FIG. 30B, the channel region 9 sandwiched between two counter ion implantation regions 35 is of the second conductivity type, and in the present invention, the first conductivity type region is not formed in the channel formation region. As an example, FIG. 31A and FIG. 31B show the impurity distribution in the D-D ′ cross section of FIG. The maximum value of the counter impurity concentration is below the same position as the depth of the pn junction at the lower end of the extension region. FIG. 31A shows the case where the maximum is in the vicinity of the lower interface of the SOI layer, and FIG. 31B shows the case where the maximum is provided above the lower interface of the SOI layer.

  The sixth embodiment may be applied to a transistor on a bulk semiconductor substrate. FIG. 32A shows an example of a cross-sectional view of the transistor, and FIG. 32B shows the impurity concentration distribution in the vertical direction in the D-D ′ cross section of FIG.

  In the manufacturing method in the sixth embodiment, in the first to fifth embodiments, a modification may be made in which counter ion implantation is performed before the formation of the gate electrode. An example of this will be described with reference to FIGS. A sacrificial oxide film 38 is formed by thermal oxidation on an SOI substrate in which the buried insulating layer 2 and the semiconductor layer 3 are stacked on the support substrate 1, and then a second conductivity type impurity serving as a channel impurity and a counter ion implantation region are formed. First conductivity type impurity ions 36 are implanted for this purpose. The region where the first conductivity type impurity ions for forming the counter ion implantation region are mainly distributed is located away from the semiconductor surface, and the concentration of the first conductivity type impurity ions 36 for forming the counter ion implantation region is the same. The maximum value is set to be lower than the position of the pn junction at the lower end of the extension region to be formed later (FIG. 33A).

  Subsequently, a gate insulating film 7 is provided on the surface of the semiconductor layer 3 by thermal oxidation or heat treatment in nitrogen, and polysilicon is deposited by a CVD method, which is etched by ordinary lithography and RIE (reactive ion etching). The gate electrode 8 is formed by processing according to the process. Subsequently, the side surface of the gate electrode 8 is thermally oxidized thinly to form the sidewall insulating film 14 (at this time, the surface of the semiconductor layer 3 is also oxidized simultaneously). Subsequently, the second conductivity type impurity 15 is introduced by oblique ion implantation using the gate electrode 8 as a mask to form the halo region 6 into which the second conductivity type impurity is introduced at a low concentration, and the configuration shown in FIG. Get.

  Subsequently, the first conductivity type impurity 16 is ion-implanted perpendicularly using the gate electrode as a mask to form the extension region 5 into which the first conductivity type impurity is introduced at a high concentration, thereby obtaining the configuration of FIG. .

  Subsequently, the gate electrode sidewall 23 is formed by a deposition technique such as CVD, and the first conductivity type impurity is ion-implanted using the gate electrode 8 and the gate electrode sidewall 23 as a mask, so that the first conductivity type impurity is introduced at a high concentration. After the formed source / drain regions 4 are formed, a heat treatment is performed to activate the impurities, a metal such as cobalt is deposited by a deposition technique such as sputtering, and then the unreacted metal is etched. By removing, a silicide region 18 is formed on the gate electrode 8 and the source / drain region, an interlayer insulating film 19 is formed, and a contact metal 20 and a wiring 21 are formed by a normal contact forming process and a wiring forming process. As a result, the configuration shown in FIG. Note that the manufacturing method described with reference to FIGS. 33 and 34 may be used for manufacturing a transistor over a bulk substrate. Moreover, you may combine with the other modification except the modification (4th embodiment etc.) regarding the halo counter injection | pouring among the manufacturing methods described in this specification.

(Other Embodiments of the Invention)
In each embodiment of the present invention, the following configuration may be selected.

  The support substrate 1 is usually a silicon substrate, but may be replaced with other materials. Further, a structure in which a semiconductor is provided on a substrate that does not have the support substrate 1 and is entirely an insulator, for example, a structure using an SOS (silicon on sapphire) substrate or a structure in which a silicon layer is provided on a glass substrate is used. May be.

  The semiconductor layer 3 is most preferably a single crystal from the viewpoint of improving on-current and suppressing off-current, but when the required on-current specification is low or the required off-current specification is large. A material other than a single crystal such as amorphous or polycrystalline may be used.

Although the buried insulating layer 2 is usually SiO _{2, Si} 3 _{N 4,} such as a porous SiO _2, it may be an insulator other than SiO _2. A cavity may be provided in the buried insulating layer. The buried insulating layer may be a multilayer film made of a plurality of insulating materials. The thickness of the buried insulating layer is generally 80 nm to 1 micrometer, but the effect of the invention does not change even if it is outside this range.

  Further, the silicon layer 3 may be replaced with a semiconductor layer other than silicon. Further, it may be replaced by a combination of two or more kinds of semiconductors. The thickness of the silicon layer 2 in the partially depleted SOI-MOSFET is typically 50 to 200 nm, but other ranges may be selected as appropriate. In particular, in a transistor with a fine gate length, typically a transistor with a gate length of 100 nm or less, the semiconductor layer may be 50 nm or less. Alternatively, a transistor in which a semiconductor layer with a thickness of 200 nm or more is provided over an insulator may be used.

Typically, 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ of donor impurities or acceptor impurities are introduced into high concentration regions such as source / drain regions and extension regions. More typically, 3 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ of donor impurities or acceptor impurities are introduced. Impurities are introduced by, for example, ion implantation or gas phase diffusion. Typical doses during ion implantation are 1 × 10 ¹⁴ cm ⁻² to 3 × 10 ¹⁵ cm ⁻² , more typically 3 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² .

The net impurity concentration (absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity concentration) in a low concentration region such as a halo region, a halo counter ion implantation region, or a channel formation region is typically 1 ×. 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , more typically 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ . However, even in a transistor having these typical impurity concentrations in the main part of each region, these typical values may be locally exceeded depending on ion implantation conditions.

  For the first conductivity type impurity introduced into the source / drain region and the first conductivity type impurity introduced into the source / drain region, in the case of an n channel transistor, a donor impurity having an n type conductivity type is used as a p channel transistor. In this case, an acceptor impurity having a p-type conductivity may be selected.

  As the second conductivity type impurity introduced into the halo region, an acceptor impurity having a p-type conductivity type may be selected for an n-channel transistor, and a donor impurity having an n-type conductivity type may be selected for a p-channel transistor. .

  The first conductivity type impurity introduced into the halo counter ion implantation region is an n-type donor impurity in the case of an n-channel transistor, and an acceptor impurity having a p-type conductivity in the case of a p-channel transistor. Just choose.

  Typical examples of n-type impurities are arsenic, phosphorus and antimony. Typical examples of p-type impurities are boron and indium.

In the embodiment of the present invention, the gate insulating film formed by thermal oxidation of silicon may be replaced with an SiO ₂ film formed by another method. For example, a SiO ₂ film formed by radical oxidation may be used. Further, the gate insulating film may be replaced with an insulating material other than SiO ₂ . Further, it may be replaced with multi-layer film or a multilayer film between the insulation films other than SiO _2, the SiO ₂ and the other insulating film. The gate insulating film may be replaced with a high dielectric constant material such as HfO ₂ or HfSiO ₄ .

  The ion-implanted impurity is activated by heat treatment such as annealing in an ordinary electric furnace or lamp annealing after ion implantation. In addition, when introducing an impurity into a channel region, in each embodiment, for example, a sacrificial oxide film is formed and then ion implantation is performed. The heat treatment for activating the implanted ions may be performed immediately after the ion implantation, or may be combined with the heat treatment for activating the impurities introduced into the source / drain regions.

  In the case where the gate electrode material is formed of a semiconductor such as polysilicon or polycrystalline silicon-germanium mixed crystal, the introduction of impurities into the gate may be performed simultaneously with the introduction of impurities into the source / drain. Further, it may be performed simultaneously with the deposition of the gate electrode material. Alternatively, it may be performed before the gate electrode material is deposited and processed into the shape of the gate electrode.

Of the channel formation region, the portion where the halo region is not formed is usually of the second conductivity type and has a lower impurity concentration than the source / drain region and the extension region. Typical impurity concentrations range from 1 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ . The impurity concentration of the semiconductor region excluding the extension region, the source / drain region, the halo region (including the halo counter ion implantation region) and the channel formation region is the same as the channel formation region or lower than the channel formation region. Has impurity concentration.

The halo region is of the second conductivity type and has a lower impurity concentration than the source / drain region and the extension region. The halo region has a higher impurity concentration than the second conductivity type portion excluding the halo region. Typical impurity concentrations range from 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The halo region is usually formed from the bottom of the extension region to the inside of the channel formation region.

  Further, the halo region may or may not reach the surface of the semiconductor layer. For a transistor in which the halo region is formed from the lower portion of the extension region to the lower corner portion of the extension region and the halo region does not reach the semiconductor surface, as shown in FIGS. The effect is the same even if each embodiment of the invention is implemented. FIG. 37 (a) corresponds to FIG. 1 (a), and FIG. 37 (b) corresponds to FIG. 15 (a).

  However, in a transistor having a short gate length, the halo regions on both sides are very close to each other and are in contact with each other. In this case, of the channel formation region, the region where the halo region is not formed is small. Further, in a transistor having a short gate length, the halo regions on both sides are in contact with each other and sometimes overlap. In this case, all channel formation regions are formed by halo regions. A typical example of the impurity distribution in that case is shown in FIG. FIG. 36A corresponds to FIG. 3A relating to the first embodiment, and FIG. 36B corresponds to FIG. 1A relating to the first embodiment.

  In each drawing of the first embodiment, the form in which the source / drain regions reach the lower interface of the semiconductor layer is mainly described, but a configuration that does not reach the lower interface may be used. For example, when the semiconductor layer is thick in the first embodiment, typically, for example, 300 nm or more, a pn junction is formed below the source / drain region as in the second embodiment. An example of this is shown in FIG. This is a drawing corresponding to FIG. FIG. 35A shows the case where the field insulating film 31 reaches the buried insulating film 2, and FIG. 35B shows the case where the field insulating film 31 does not reach the buried insulating film 2.

1A and 1B are a cross-sectional view and a plan view showing a first embodiment of a field effect transistor according to the invention. Sectional drawing explaining 1st Embodiment of the field effect transistor of this invention. The impurity distribution of 1st Embodiment of the field effect transistor of this invention is shown. Sectional drawing explaining the effect of this invention. Sectional drawing which shows the manufacturing method of the field effect transistor of 1st Embodiment of the field effect transistor of this invention. Sectional drawing which shows the manufacturing method of the field effect transistor of 1st Embodiment of the field effect transistor of this invention. Sectional drawing which shows the manufacturing method of the field effect transistor of 1st Embodiment of the field effect transistor of this invention. Sectional drawing which shows the manufacturing method of the field effect transistor of 1st Embodiment of the field effect transistor of this invention. Sectional drawing explaining 1st Embodiment of the field effect transistor of this invention. The figure explaining the effect of the 1st Embodiment of this invention. FIG. 3 is an impurity distribution diagram illustrating a first embodiment of a field effect transistor according to the invention. FIG. 3 is an impurity distribution diagram illustrating a first embodiment of a field effect transistor according to the invention. FIG. 3 is an impurity distribution diagram illustrating a first embodiment of a field effect transistor according to the invention. FIG. 3 is an impurity distribution diagram illustrating a first embodiment of a field effect transistor according to the invention. Sectional drawing and top view which show 2nd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 2nd Embodiment of the field effect transistor of this invention. Sectional drawing explaining the effect of 2nd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 2nd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 2nd Embodiment of the field effect transistor of this invention. FIG. 5 is an impurity distribution diagram illustrating a second embodiment of the field effect transistor according to the invention. Sectional drawing explaining 3rd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 3rd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 3rd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 3rd Embodiment of the field effect transistor of this invention. Sectional drawing explaining 4th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 4th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 4th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 4th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 5th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 6th Embodiment of the field effect transistor of this invention. The impurity distribution of 6th Embodiment of the field effect transistor of this invention. Sectional drawing and impurity distribution of 6th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 6th Embodiment of the field effect transistor of this invention. Sectional drawing explaining 6th Embodiment of the field effect transistor of this invention. Sectional drawing explaining other embodiment of the field effect transistor of this invention. Sectional drawing explaining other embodiment of the field effect transistor of this invention. Sectional drawing explaining other embodiment of the field effect transistor of this invention. Sectional drawing and top view explaining the prior art. The impurity distribution in a prior art is shown. Sectional drawing explaining the problem of the prior art. Sectional drawing explaining the prior art. Sectional drawing explaining the prior art. Sectional drawing explaining the problem of the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Buried insulating layer 3 SOI layer 4 Source / drain region 5 Extension region 6 Halo region 7 Gate insulating film
8 Gate electrode
9 Channel formation region
10 Neutral region
11 Electric field due to neutral region charge
12 Deep first conductivity type region
13 Hello counter ion implantation area
14 Side wall insulating film
15 Second conductivity type impurity ions
16 First conductivity type impurity ions
17 First conductivity type impurity ions
18 Silicide region
19 Interlayer insulation film
20 Contact metal
21 Wiring
22 Semiconductor substrate
23 Gate electrode side wall
24 Side wall of first gate electrode
25 Side wall of second gate electrode
26 First conductivity type impurity for forming source / drain regions
27 Region where impurities forming left and right halo regions overlap
31 Field insulating film
32 Range in which the second conductivity type impurity for forming the halo region is introduced
33 Range in which first conductivity type impurity for forming extension region is introduced 34 Range in which first conductivity type impurity for forming halo counter ion implantation region is introduced 35 Counter ion implantation region
36 First conductivity type impurity ions for forming counter ion implantation region
37 Region in which first conductivity type impurity ions are mainly distributed to form counter ion implantation region 38 Sacrificial oxide film
C1 Extension-neutral capacity
C2 Deep source / drain-neutral region capacitance

Claims (16)

A gate electrode is provided on the semiconductor region via a gate insulating film,
A second conductivity type channel forming region in a region including the lower portion of the gate electrode in the semiconductor region;
A first conductivity type impurity having a concentration higher than that of the second conductivity type impurity in the second conductivity type channel formation region is introduced into a region including the surface of the semiconductor region in contact with the gate electrode in the second conductivity type channel formation region. A field effect transistor having a region,
A second conductivity type impurity at a position below the region where the first conductivity type impurity is introduced in a direction perpendicular to the surface of the semiconductor region at a position in contact with the gate electrode in the region where the first conductivity type impurity is introduced. A field effect transistor having a maximum concentration. The region into which the first conductivity type impurity is introduced includes an extension region having a position in contact with the gate electrode, and a first conductivity type to a position deeper than the extension region in a region farther from the gate electrode than the extension region. And a source / drain region into which impurities are introduced,
The second conductivity type channel formation region has a halo counter ion implantation region into which the first conductivity type counter impurity is introduced at a lower concentration than the second conductivity type impurity at the same position in a region below the extension region. The field effect transistor according to claim 1. 3. The counter impurity concentration has a maximum value below a position of a pn junction to be provided at a lower end of the extension region in a direction perpendicular to a surface of the semiconductor region at a position having the extension region. The field effect transistor described in 1. The second conductivity type channel formation region sandwiched between the extension regions on both sides below the gate electrode has a region where the first conductivity type counter impurity is not introduced at any position in the vertical direction. 4. The field effect transistor according to claim 2, wherein the field effect transistor is characterized by the following. The field effect transistor according to any one of claims 1 to 4, wherein the semiconductor region is formed on an insulator. The field effect transistor according to claim 1, wherein the semiconductor region is provided in a bulk semiconductor substrate. A region surrounding the lower portion of the extension region and the side portion on the gate electrode side has a halo region in which the second conductivity type impurity is introduced at a lower concentration than the first conductivity type impurity introduced for the extension region;
7. The field effect transistor according to claim 2, wherein the halo region has a maximum value of the counter impurity concentration in a direction perpendicular to the surface of the semiconductor region at a position having the extension region. A gate insulating film forming step of forming a gate insulating film on the semiconductor region;
Forming a gate electrode on the gate insulating film; and
A second conductivity type channel formation region forming step of forming a second conductivity type channel formation region at a position including the lower side of the gate electrode in the semiconductor region;
An extension region forming step of forming a first conductivity type extension region by introducing a first conductivity type impurity into the surface side of the semiconductor region where the gate electrode is not provided;
A halo region forming step of forming a halo region by introducing a second conductivity type impurity to a lower portion of the extension region and a side portion having the gate electrode in the semiconductor region;
A halo counter ion implantation region forming step of forming a halo counter ion implantation region by introducing a counter impurity of a first conductivity type to a lower portion of the extension region in the semiconductor region,
In the halo counter ion implantation region forming step, the first conductivity type has a maximum value of the counter impurity concentration below the extension region in a direction perpendicular to the surface of the semiconductor region at the position having the extension region. A method of manufacturing a field effect transistor, comprising introducing a counter impurity. The halo counter ion implantation region forming step introduces the first conductivity type counter impurity at a lower concentration than the second conductivity type impurity at a position having the maximum value of the counter impurity concentration in the halo counter ion implantation region. The method of manufacturing a field effect transistor according to claim 8. The method for manufacturing a field effect transistor according to claim 8, wherein the semiconductor region is provided on an insulator. 10. The method of manufacturing a field effect transistor according to claim 8, wherein the semiconductor region is a bulk semiconductor substrate. An insulating film forming step of forming an insulating film on the semiconductor region;
12. The method according to claim 8, further comprising the extension region forming step, the halo region forming step, and the halo counter ion implantation region forming step after the insulating film forming step. A method of manufacturing a field effect transistor. 13. The method of manufacturing a field effect transistor according to claim 12, wherein the extension region forming step is performed without the insulating film formed in the insulating film forming step. 14. The method of manufacturing a field effect transistor according to claim 8, wherein the halo counter ion implantation region forming step is performed after the gate electrode forming step. 15. The method of manufacturing a field effect transistor according to claim 8, wherein the halo counter ion implantation region forming step is performed after sidewalls are formed on both sides of the gate electrode. . 16. The method of manufacturing a field effect transistor according to claim 8, wherein the halo region forming step introduces the second conductivity type impurity by oblique ion implantation.

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