KR100977408B1 - Trench type Silicon Carbide MOSFET - Google Patents

Abstract

The present invention relates to a silicon carbide MOS field effect transistor having a trench structure, comprising: a first conductive silicon carbide substrate having a concentration of impurities in a range of 5E18 to 5E19 cm ^-3 ; A first conductive type silicon carbide epitaxial film layer formed on an upper surface of the silicon carbide substrate in a range of 5E13 to 5E16 cm ^-3 ; A second conductive type base region having a depth of 0.6˜1.0 μm formed through ion implantation of the second conductive type impurity through a mask patterned on the surface of the epitaxial film layer, and having an impurity concentration ranging from 1E17 to 5E17 cm ⁻³ ; A first conductive source region formed to a depth of 0.1 to 0.2 μm formed through ion implantation of a first conductive impurity in the entire upper portion of the epitaxial film layer; Trench formed by etching a relatively deeper than the ion implantation depth of the second conductive base through a trench process by spaced apart from the second conductive base between the region where the second conductive base of the epitaxial layer is formed by a predetermined distance (W1). A gate region; A gate oxide film formed on an outer wall of the trench gate region by a thermal oxidation process; A gate electrode formed by depositing polysilicon in a trench gate region outside the gate oxide film; After the planarization process, the deposited polysilicon is etched to expose the surface of the epitaxial layer through dry etching, and then a screen oxide film and a photoresist are deposited to deposit a first conductive type impurity ion implantation region using a photolithography process. A second conductive source region formed by forming a region into which the second conductive impurity is ion implanted and implanting the second conductive impurity into the region; A source electrode formed on the source region of the epitaxial layer through aluminum metal deposition by depositing BPSG to electrically insulate the gate electrode from the source region, and then forming a source electrode deposition region through a photolithography process; A trench structure silicon carbide MOS field effect transistor, characterized in that it comprises a; a drain electrode formed on the back of the silicon carbide substrate is a technical gist. Accordingly, the present invention has the above-described structure, and according to the gate voltage, a balance between the amount of charges in the p-base region formed by the patterning on the epitaxial layer and the amount of electrons accumulated in the trench gate region and the channel region. has an on-state current density, improves the on-state current density characteristics compared to the non-patterned p-base, lowers the on-state resistance R _{ON , sp} and does not affect the ability to turn off the voltage in the off state. There is this.

Silicon Carbide Trench Structure Field Effect Transistor Trench SiC-MOSFET Patterned p-Base

Description

Trench structure Silicon carbide MOS field effect transistor {Trench type Silicon Carbide MOSFET}

The present invention relates to a silicon carbide MOS field effect transistor having a trench structure, wherein the second conductive base region is spaced apart from the trench gate region wall by W1 to induce a channel region to accumulate charge and to pattern the second conductive base region. the second conductive type base region and the first conductivity type to match the charge balance of the epitaxial thin film layer improves the electron mobility of the channel region to so as to obtain a low R _{oN, sp} trench structure to improve the characteristics of the silicon carbide MOS field It relates to an effect transistor.

In general, the field effect transistor is a type of transistor that controls the drain current through the change of the channel region according to the magnitude of the voltage applied to the gate. In particular, silicon carbide field effect transistors are known to have very useful properties as high voltage and high temperature devices because of their wide bandgap of 3.26 eV and high thermal conductivity of 4.9 W / cm-K. In addition, silicon carbide MOSFETs in the same breakdown voltage region (hereinafter referred to as 'MOSFET') devices have a much lower R _{ON and sp} than silicon MOSFETs, resulting in lower operating losses.

On the other hand, when the voltage is applied to the gate without the MOSFET device operating without a voltage applied to the gate, most of the carbonization is realized to realize a nomally-off MOSFET device in which current flows while electrons move through the channel. Silicon MOSFETs use an inversion channel structure. In this case, the mobility of electrons in the depleted channel region is lowered, and thus the current-voltage characteristic of the MOSFET device is lowered.

In order to solve this problem, the trench structure silicon carbide MOSFET device of the conventional depletion channel structure, as shown in Figure 1, a low concentration of the first conductive epitaxial film layer on the high concentration of the first conductive substrate 10, To form a second conductive type impurity through ion implantation to form the second conductive base region 30 having a high concentration in the first conductive epitaxial film layer 20 having a low concentration, and then a trench. After the gate region is formed by the process, the gate oxide layer 50 and the polysilicon gate electrode 60 are deposited, and a high concentration of the first conductive impurity is formed in the second conductive base region 30 for the source region 70. Let's do it. A screen oxide layer 80 and a p + source region 90 are formed on the gate electrode 60, and a source electrode 100 is formed on the upper layer of the gate electrode 60, and a drain is formed on the rear surface of the first conductive substrate 10. The electrode 110 is formed.

At this time, the channel region is a difference between the base junction depth, which is the ion implantation depth of the second conductive impurity, and the source depth, which is the ion implantation depth of the second conductive impurity, in the trench wall. In this structure, the silicon carbide MOSFET depletes the channel region according to the voltage of the gate, and electrons move from the source to the drain and contribute to the current flow according to the magnitude of the voltage of the drain.

However, in the case of a MOSFET having a depletion type channel structure, there is a problem in that the mobility of electrons in the channel region is low, so that R _{ON and sp} drop and the on-state loss of the device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the second conductive base region is spaced apart from the trench gate region wall by W1 to induce a channel region to accumulate charges and pattern the second conductive base region to pattern the second conductive base region. Due to the charge balance between the region and the first conductive epitaxial layer, the electron mobility of the channel region of the trench structure silicon carbide MOSFET device is improved to obtain a low R _{ON and sp} to obtain a low R _sp , thereby improving the on-state characteristics of the device. The purpose is to maintain the breakdown voltage characteristic.

In order to achieve the above object, the present invention, the impurity concentration of the first conductive silicon carbide substrate of 5E18 ~ 5E19cm ^-3 range; A first conductive type silicon carbide epitaxial film layer formed on an upper surface of the silicon carbide substrate in a range of 5E13 to 5E16 cm ^-3 ; A second conductive type base region having a depth of 0.6˜1.0 μm formed through ion implantation of the second conductive type impurity through a mask patterned on the surface of the epitaxial film layer, and having an impurity concentration ranging from 1E17 to 5E17 cm ⁻³ ; A first conductive source region formed to a depth of 0.1 to 0.2 μm formed through ion implantation of a first conductive impurity in the entire upper portion of the epitaxial film layer; Trench formed by etching a relatively deeper than the ion implantation depth of the second conductive base through a trench process by spaced apart from the second conductive base between the region where the second conductive base of the epitaxial layer is formed by a predetermined distance (W1). A gate region; A gate oxide film formed on an outer wall of the trench gate region by a thermal oxidation process; A gate electrode formed by depositing polysilicon in a trench gate region outside the gate oxide film; After the planarization process, the deposited polysilicon is etched to expose the surface of the epitaxial layer through dry etching, and then a screen oxide film and a photoresist are deposited to deposit a first conductive type impurity ion implantation region using a photolithography process. A second conductive source region formed by forming a region into which the second conductive impurity is ion implanted and implanting the second conductive impurity into the region; A source electrode formed on the source region of the epitaxial layer through aluminum metal deposition by depositing BPSG to electrically insulate the gate electrode from the source region, and then forming a source electrode deposition region through a photolithography process; A trench structure silicon carbide MOS field effect transistor, characterized in that it comprises a; a drain electrode formed on the back of the silicon carbide substrate is a technical gist.

In addition, it is preferable that each of the W1 and the patterned second conductive base has an accumulation channel having a thickness of 0.1 to 0.5 µm.

In addition, the gate electrode may form a first conductive polysilicon gate electrode by depositing polysilicon doped with a first conductivity type in the trench gate region, or after depositing undoped polysilicon, a first conductive impurity It is preferable to form the first conductive polysilicon gate electrode through diffusion of.

In the fabrication of the trench structure silicon carbide MOS field effect transistor (MOSFET), the separation effect in the patterned p-base and the trench gate proposed by the present invention is used, compared with the conventional silicon carbide MOS field effect transistor as follows. There is.

(1) By separating the trench gate and the second conductive base by W1, the channel region of the MOSFET is formed into a storage structure, and the mobility of the carrier is increased, thereby improving drain current characteristics of the MOSFET.

(2) By adopting the patterned structure instead of the cylindrical base structure as the second conductive base structure, the carrier mobility of the accumulated channel region can be effectively induced by inducing the second conductive base and the epitaxial layer (drift region). Further improvement compared to the channel structure allows a large drain current to flow to improve the current density.

(3) These charge balance and mobility improvements result in lower R _{ON and sp} of silicon carbide MOSFETs _, resulting in lower on-state losses.

The invention accumulation (accumulation) relates to a trench structure having a silicon carbide MOSFET type channel structure, the concentration of the high concentration impurity 5E18 ~ The concentration of the impurity in the upper surface of the first conductivity type silicon carbide substrate in the range of 5E13 ~ 5E16cm 5E19cm ^{-3 -} Patterning a desired shape through a photolithography process using a patterned mask and a photoresist to form a low-concentration first conductivity type silicon carbide epitaxial layer in a range of ³ , and to form a second conductive base layer on the surface of the epitaxial layer. Thereafter, the second conductive type impurity is implanted to form a second conductive type base region having a depth of 0.6 to 1.0 µm. The introduction of the patterned second conductive base by the patterned second conductive base region induces charge balance between the second conductive base and the drift region of the epitaxial layer.

The first upper surface of the epitaxial film layer is ion-implanted with a first conductive type impurity to form a first conductive source region having a depth of 0.1 to 0.2 μm, and thereafter, a second gap between the regions where the second conductive base of the epitaxial layer is formed. The two conductive bases are spaced apart by a predetermined distance W1 (0.1 to 0.5 μm) to form a trench gate region through a trench etching process. By providing a predetermined distance W1 from the second conductive base and the trench gate region, the electron mobility of the trench structure silicon carbide MOSFET having the electron accumulation channel structure can be improved, and consequently, R _{ON and sp} can be reduced.

A gate oxide film is deposited on the outer wall of the trench gate region using a thermal oxide process, and a first conductive polysilicon is deposited on the trench gate region outside the gate oxide layer to form a gate electrode, to planarize the surface, and to dry. The epitaxial layer is etched to expose the surface through a photolithography process, and then a screen oxide film and a photoresist are deposited to form a region for the second conductivity type ion implantation of the source region through ion patterning and implanting the second conductivity type impurity. To form a second conductive source region, and then deposit a boro-phospho silicate glass (BPSG) to electrically insulate the gate electrode, and then form a source electrode deposition region through a photolithography process to deposit aluminum metal. A source electrode is formed in the source region of the epitaxial layer, and the silicon carbide Forming a drain electrode formed on the back plate, and is to be mainly of the completion of the trench structure, the silicon carbide MOS field effect transistor according to the present invention.

Here, the first conductive type and the second conductive type preferably have a first conductivity type of n type, a second conductivity type of p type, a first conductivity type of p type, and a second conductivity type of n type. In addition, the first conductive impurity may be a pentavalent ion such as nitrogen or phosphorus, and the second conductive impurity may be a trivalent ion such as boron or vice versa.

Accordingly, according to the present invention, the second conductive base region selectively formed to balance the charge between the second conductive base region and the drift region composed of the first conductive epitaxial layer is formed in the trench gate. Through the channel region in which charges formed by being spaced apart from the wall of the region by W1 (0.1 to 0.5 µm) are to be accumulated, the mobility of the carrier is increased to lower the R _{ON and sp} of the trench structure silicon carbide MOSFET _, thereby reducing the on-state loss. There is an advantage to reduce.

Hereinafter, as a preferred embodiment of the present invention, a case in which the high concentration first conductive silicon carbide substrate is an n + type substrate will be described in detail with reference to the accompanying drawings. 2A to 2H are cross-sectional views illustrating a process of fabricating a trench structure silicon carbide MOSFET according to the present invention.

As shown, the trench structure silicon carbide MOSFET according to the present invention has a high concentration n + type silicon carbide substrate 201, a low concentration n ^- type silicon carbide epitaxial film layer 202 and a low concentration n- type silicon carbide epitaxial film layer formed thereon. A gate oxide layer 209 and a polysilicon gate electrode 210A, n + ion implantation and p + ion implantation formed in the p-base region 205 and the trench gate region 208 that are selectively patterned on top of and a source electrode 215 formed over the n + source region 206A and a p + source region 213 and a drain electrode 216 formed under the n + silicon carbide substrate.

In detail, a low concentration n-type silicon carbide epitaxial layer 202 is formed on an upper surface of the high concentration n + type silicon substrate 201. At this time, the concentration and thickness of the low concentration n-type silicon carbide epitaxial film layer 202 are determined according to the desired breakdown voltage.

In addition, a patterned mask 203 and a patterned photoresist 204 formed of an oxide film are deposited on the low concentration n ⁻ type silicon carbide epitaxial layer 202 and ion implanted into the p-base to be patterned through a photolithography process. After forming the region to be formed, the p-base region 205 is formed through boron ion implantation.

Next, a region 206 in which nitrogen or phosphorus ions are ion-implanted is formed in the entire upper portion of the low concentration n− silicon carbide epitaxial layer 202 to form an n + source region 206A. After etching the trench gate region 208 by the trench etching mask 207 deeper than the p-base ion implantation depth through the trench etching process, the gate oxide layer 209 is deposited through the thermal oxide process, and then the trench gate region ( Polysilicon 210 is deposited on 208 to form a gate electrode 210A.

Here, the gate electrode 210A may form n + polysilicon gate electrode by depositing n + polysilicon in the trench gate region 208 or n + polysilicon through n + diffusion after depositing undoped polysilicon. A gate electrode can be formed.

After the deposited polysilicon is subjected to a surface planarization process, the surface of the epitaxial layer 202 is exposed through dry etching, and then the gate electrode 210A, the source regions 206A, and 213 are etched. After electrically insulating and depositing a screen oxide film 211 for boron ion implantation, after patterning the region where boron ions are to be implanted through a photolithography process using photoresist 212, ion implantation of p + The source region 213 is formed.

Next, a BPSG (boro-phospho silicate glass) 214 is deposited to electrically insulate the gate electrode 210A from the source region, and then the entire p + source region 213 and the n + source using a photolithography process. After defining a region where a source electrode is to be deposited in a portion of the region 206A, aluminum metal is deposited to form a source electrode 215, and a drain electrode 216 is formed below the high concentration n + silicon carbide substrate 201.

3 and 4 show the characteristics of the trench structure silicon carbide MOSFET fabricated by the above process, Figure 3 is a drain voltage vs. drain current characteristics of the trench structure silicon carbide field effect transistor according to the present invention and the conventional trench structure 4 shows a comparison of drain voltage versus drain current characteristics of a silicon carbide field effect transistor, and FIG. 4 shows a comparison of breakdown voltage characteristics of a trench structure silicon carbide field effect transistor according to the present invention and a conventional trench structure silicon carbide field effect transistor. to be.

As shown in FIG. 3, when the trench gate and the p-base are spaced apart by W1, the channel region of the MOSFET is formed in a storage structure, thereby increasing the mobility of the carrier, thereby improving drain current characteristics compared to the conventional MOSFET. I could confirm it.

And, as shown in Figure 4, by adopting a structure patterned p-base, the carrier mobility of the accumulation channel region is reduced by effectively inducing charge balance between the p-base and n-drift region, the conventional accumulation channel structure Compared to the above, a large drain current flows to improve the current density and lower the on-state resistance (R _{ON , sp} ) to improve the on-state characteristic of the device and maintain the breakdown voltage characteristic to maintain the off-state voltage capability. It was confirmed that no effect.

1B-a cross-sectional view showing the structure of a conventional accumulation channel type trench structure silicon carbide field effect transistor.

2A-2H-schematic cross-sectional view showing a method of manufacturing a trench structure silicon carbide field effect transistor according to the present invention;

Figure 3 shows a comparison of the drain voltage versus drain current characteristics of a trench structure silicon carbide field effect transistor according to the present invention and the drain voltage vs. drain current characteristics of a conventional trench structure silicon carbide field effect transistor.

4 is a diagram showing a breakdown voltage characteristic comparison between a trench structure silicon carbide field effect transistor according to the present invention and a conventional trench structure silicon carbide field effect transistor;

<Description of Major Symbols Used in Drawings>

201: silicon carbide substrate 202: silicon carbide epitaxial layer

203 patterned mask 204 patterned photoresist

205: p-base region 206: region in which nitrogen or phosphorus ions are ion-implanted in the entire upper portion of the epitaxial layer to form an n + source

206A: n + source region 207: trench etch mask

209: gate oxide film 210: polysilicon

210A: polysilicon gate electrode 211: screen oxide film

212: photoresist 213: p + source region

214: BPSG 215: source electrode

216: drain electrode

Claims (3)

A first conductivity type silicon carbide substrate 201 having an impurity concentration ranging from 5E18 to 5E19 cm ^-3 ; A first conductive type silicon carbide epitaxial layer 202 formed on the top surface of the silicon carbide substrate 201 in a range of 5E13 to 5E16cm ^-3 ; The second conductive type having a depth of 0.6˜1.0 μm formed through ion implantation of the second conductive type impurity through the mask 203 patterned on the surface of the epitaxial layer 202, and the impurity concentration of 1E17˜5E17cm ^−3. A base region 205; A first conductive source region 206A having a depth of 0.1 to 0.2 μm formed through ion implantation of a first conductive impurity in the entire upper portion of the epitaxial film layer; The second conductive base between the second conductive base region 205 of the epitaxial film layer 202 is separated from the second conductive base by a predetermined distance (W1) and etched relatively deeper than the ion implantation depth of the second conductive base through a trench process. A trench gate region 208 formed thereon; A gate oxide film 209 formed on an outer wall of the trench gate region 208 by a thermal oxidation process; A gate electrode 210A formed by depositing polysilicon 210 in the trench gate region 208 outside the gate oxide film 209; After the planarization process, the deposited polysilicon is etched so that the surface of the epitaxial layer is exposed through dry etching, and then, a screen oxide film 211 and a photoresist 212 are deposited to deposit a first conductive layer using a photolithography process. A second conductive source region 213 formed by forming a region for ion implanting the second conductive impurity in the region into which the impurity is implanted and implanting the second conductive impurity; After depositing the BPSG 214 to electrically insulate the gate electrode 210A from the source regions 206A, 213, a source electrode deposition region is formed through a photolithography process to form the epi via aluminum metal deposition. A source electrode 215 formed in the source regions 206A and 213 of the thin film layer 202; A trench structure silicon carbide MOS field effect transistor, comprising: a drain electrode 216 formed on a rear surface of the silicon carbide substrate 201. The trench structured silicon carbide MOS field effect transistor of claim 1, wherein each of the W1 and the patterned second conductive base has an accumulation channel having a spacing of 0.1 to 0.5 μm. The method of claim 1, wherein the gate electrode 210A, Depositing polysilicon doped with a first conductivity type in the trench gate region 208 to form a first conductive polysilicon gate electrode, or depositing undoped polysilicon and then diffusing the first conductive impurity A trench structure silicon carbide MOS field effect transistor, comprising forming a first conductive polysilicon gate electrode.

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