CN114792629A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114792629A
CN114792629A CN202110106489.0A CN202110106489A CN114792629A CN 114792629 A CN114792629 A CN 114792629A CN 202110106489 A CN202110106489 A CN 202110106489A CN 114792629 A CN114792629 A CN 114792629A
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CN
China
Prior art keywords
forming
source
region
sacrificial layer
drain
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CN202110106489.0A
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Chinese (zh)
Inventor
杨震
张银艳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110106489.0A priority Critical patent/CN114792629A/en
Publication of CN114792629A publication Critical patent/CN114792629A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area, the first area comprises a first peripheral area and a first core area, the first peripheral area is provided with a first pseudo gate structure, and the first core area is provided with a second pseudo gate structure; forming a first sacrificial layer exposing the first region; forming a first source drain opening and a second source drain opening in the first region by taking the first sacrificial layer as a mask; and forming a first lightly doped region on the side wall and the bottom surface of the first source drain opening by using the first sacrificial layer as a mask. The first source drain opening, the second source drain opening and the first lightly doped region can be simultaneously processed through the first sacrificial layer, the number of the sacrificial layers is effectively reduced, the production cost is reduced, and the production efficiency is improved. In addition, the first lightly doped region is formed after the first source drain opening is formed, and the blocking of the first peripheral region is reduced, so that the ion implantation energy, the dosage and the ion implantation time during the formation of the first lightly doped region can be effectively reduced.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
As the channel length of semiconductor devices is reduced, semiconductor substrates and source/drains are typically doped to a greater concentration to generate a high electric field in the depletion region of the source/drain in order to achieve the desired drive current and suppress short channel effects. When the high-voltage input/output device operates in a saturation current state, inversion layer charges are accelerated under the action of a transverse electric field on the surface of a channel and collide and ionize with crystal lattices, and a large number of hot carriers (electron-hole pairs) are generated. Hot electrons and Hot holes can be emitted toward the gate dielectric layer across the interface barrier, creating a Hot-Carrier Injection (HCI) effect. Hot carriers entering the gate dielectric have the following effect: a rise in threshold voltage, a fall in saturation drive current, and a fall in carrier mobility; meanwhile, hot electrons or hot holes can enter the substrate under the action of the junction electric field to form substrate leakage current, and the working characteristics and reliability of the device can be seriously influenced by the result caused by the hot carriers.
Currently, in order to improve the hot carrier injection effect of the NMOS transistor, LDD (Lightly Doped Drain) ion implantation is usually adopted for optimization, and the performance of the semiconductor device is improved by reducing the dose of LDD ion implantation and increasing the LDD implantation energy.
However, the LDD ion implantation process in the prior art still has more problems.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor structure, which can effectively improve the production efficiency and save the production cost.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region, the first region comprises a first peripheral region and a first core region, the first peripheral region is provided with a plurality of first dummy gate structures which are arranged in parallel, a first size is arranged between the adjacent first dummy gate structures, the first core region is provided with a plurality of second dummy gate structures which are arranged in parallel, a second size is arranged between the adjacent second dummy gate structures, and the second size is smaller than the first size; forming a first sacrificial layer on the substrate to expose the first region; forming a plurality of first source-drain openings in the first peripheral region by taking the first sacrificial layer as a mask, wherein the first source-drain openings are positioned between the adjacent first pseudo gate structures, a plurality of second source-drain openings are formed in the first core region, and the second source-drain openings are positioned between the adjacent second pseudo gate structures; after the first source drain opening and the second source drain opening are formed, ion inclined injection treatment is carried out on the first region by taking the first sacrificial layer as a mask, a first lightly doped region is formed on the side wall and the bottom surface of the first source drain opening, and first ions are arranged in the first lightly doped region.
Optionally, after the first lightly doped region is formed, a first source-drain doping layer is formed in the first source-drain opening by using the first sacrificial layer as a mask, a second source-drain doping layer is formed in the second source-drain opening, and second ions are provided in the first source-drain doping layer and the second source-drain doping layer.
Optionally, the substrate includes a second region, the second region includes a second peripheral region and a second core region, the second peripheral region has a plurality of third dummy gate structures arranged in parallel, a third size is provided between adjacent third dummy gate structures, the second core region has a plurality of fourth dummy gate structures arranged in parallel, a fourth size is provided between adjacent fourth dummy gate structures, and the fourth size is smaller than the third size.
Optionally, after the first source-drain doping layer and the second source-drain doping layer are formed, the method further includes: removing the first sacrificial layer; forming a second sacrificial layer on the substrate to expose the second region; forming a plurality of third source-drain openings in the second peripheral region by using the second sacrificial layer as a mask, wherein the third source-drain openings are located between adjacent third dummy gate structures, a plurality of fourth source-drain openings are formed in the second core region, and the fourth source-drain openings are located between adjacent fourth dummy gate structures; after the third source drain opening and the fourth source drain opening are formed, the second sacrificial layer is used as a mask, ion inclined injection treatment is carried out on the second region, a second light doping region is formed on the side wall and the bottom surface of the third source drain opening, third ions are arranged in the second light doping region, and the electrical type of the third ions is opposite to that of the first ions.
Optionally, after the second lightly doped region is formed, the method further includes: and forming a third source drain doping layer in the third source drain opening by taking the second sacrificial layer as a mask, forming a fourth source drain doping layer in the fourth source drain opening, wherein fourth ions are arranged in the third source drain doping layer and the fourth source drain doping layer, and the electrical types of the fourth ions are opposite to that of the second ions.
Optionally, the method for forming the first source-drain opening and the second source-drain opening includes: and etching the first peripheral region and the first core region by using the first sacrificial layer, the first dummy gate structure and the second dummy gate structure as masks to form the first source drain opening and the second source drain opening.
Optionally, the forming method of the third source-drain opening and the fourth source-drain opening includes: and etching the second peripheral region and the second core region by using the second sacrificial layer, the third dummy gate structure and the fourth dummy gate structure as masks to form the third source-drain opening and the fourth source-drain opening.
Optionally, the first ions include: n-type ions or P-type ions; the third ions include: p-type ions or N-type ions.
Optionally, the second ions include: n-type ions or P-type ions; the fourth ions include: p-type ions or N-type ions.
Optionally, the method for forming the first sacrificial layer includes: forming an initial first sacrificial layer on the substrate, the initial first sacrificial layer covering the first and second regions; and removing the initial first sacrificial layer on the first region by adopting a patterning process to form the first sacrificial layer.
Optionally, the method for forming the second sacrificial layer includes: forming an initial second sacrificial layer on the substrate, the initial second sacrificial layer covering the first and second regions; and removing the initial second sacrificial layer on the second region by adopting a patterning process to form the second sacrificial layer.
Optionally, after the third source-drain doping layer and the fourth source-drain doping layer are formed, the method further includes: removing the second sacrificial layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side walls of the first pseudo gate structure, the second pseudo gate structure, the third pseudo gate structure and the fourth pseudo gate structure.
Optionally, after forming the dielectric layer, the method further includes: removing the first pseudo gate structure, and forming a first gate opening in the dielectric layer; removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer; removing the third pseudo gate structure, and forming a third gate opening in the dielectric layer; removing the fourth pseudo gate structure, and forming a fourth gate opening in the dielectric layer; forming a first gate structure in the first gate opening; forming a second gate structure in the second gate opening; forming a third gate structure in the third gate opening; and forming a fourth gate structure in the fourth gate opening.
Optionally, the substrate includes: the first pseudo gate structure and the second pseudo gate structure respectively cross the first fin parts.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme, a first sacrificial layer exposing the first region is formed on the substrate, and the first source-drain opening and the second source-drain opening are formed by taking the first sacrificial layer as a mask; after a first source drain opening and a second source drain opening are formed, ion inclined injection treatment is continuously carried out by taking the first sacrificial layer as a mask, and first lightly doped regions are formed on the side wall and the bottom surface of the first source drain opening. The first sacrificial layer can simultaneously complete the manufacturing procedure of the first source drain opening, the second source drain opening and the ion inclined injection treatment, the number of the sacrificial layers can be effectively reduced, the production cost is reduced, and the production efficiency is improved. In addition, the first lightly doped region is formed after the first source drain opening is formed, and the blocking of the first peripheral region is reduced, so that the ion implantation energy, the dosage and the ion implantation time during the formation of the first lightly doped region can be effectively reduced.
Drawings
Fig. 1 to fig. 4 are schematic structural diagrams illustrating a process of forming a semiconductor structure;
fig. 5 to 15 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the LDD ion implantation process in the prior art still has more problems. The following detailed description will be made with reference to the accompanying drawings.
Fig. 1 to fig. 4 are schematic structural diagrams of a semiconductor structure formation process.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a first region I and a second region II, the first region I has a plurality of first dummy gate structures 101 arranged in parallel, and the second region II has a plurality of second dummy gate structures 102 arranged in parallel; forming a first sacrificial layer 103 on the second region II, wherein the first sacrificial layer 103 covers the second dummy gate structure 102; a plurality of initial first lightly doped regions 104 are formed in the first region I, and the initial first lightly doped regions 104 are located between the adjacent first dummy gate structures 101.
Referring to fig. 2, after the initial first lightly doped region 104 is formed, the first sacrificial layer 103 is removed, a second sacrificial layer 105 is formed on the first region I, and the second sacrificial layer 105 covers the first dummy gate structure 101; a plurality of initial second lightly doped regions 106 are formed in the second region II, and the initial second lightly doped regions 106 are located between the adjacent second dummy gate structures 102.
Referring to fig. 3, after the second lightly doped region 106 is formed, the second sacrificial layer 105 is removed, a third sacrificial layer 107 is formed on the second region II, and the third sacrificial layer 107 covers the second dummy gate structure 102; removing part of the initial first lightly doped region 104 to form the first lightly doped region 108 and a first source-drain opening; and forming a first source-drain doping layer 109 in the first source-drain opening.
Referring to fig. 4, after the first source-drain doping layer 109 is formed, the third sacrificial layer 107 is removed, a fourth sacrificial layer 110 is formed on the first region I, and the fourth sacrificial layer 110 covers the first dummy gate structure 101; removing part of the initial second lightly doped region 106 to form a second lightly doped region 111 and a second source-drain opening; and forming a second source-drain doping layer 112 in the second source-drain opening.
In this embodiment, the first lightly doped region 108 and the second lightly doped region 111 are formed by first forming the initial first lightly doped region 104 and the initial second lightly doped region 106, and then removing a portion of the initial first lightly doped region 104 and a portion of the initial second lightly doped region 106 to form the first lightly doped region 108 and the second lightly doped region 111, in which the first sacrificial layer 103 and the second sacrificial layer 105 are required to be consumed in the process, and the third sacrificial layer 107 and the fourth sacrificial layer 110 are required to be consumed in the subsequent process of forming the first source-drain opening and the second source-drain opening, which not only increases the manufacturing cost, but also reduces the production efficiency.
In addition, when the initial first lightly doped region 104 and the initial second lightly doped region 106 are formed, since the depth and the ion concentration of the finally formed first lightly doped region 108 and the second lightly doped region 111 are ensured, the ion implantation energy, the dose and the ion implantation time required for forming the initial first lightly doped region 104 and the initial second lightly doped region 106 are also increased.
On the basis, the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a first sacrificial layer exposing a first region on a substrate, and forming a first source-drain opening and a second source-drain opening by taking the first sacrificial layer as a mask; after a first source drain opening and a second source drain opening are formed, ion inclined injection treatment is continuously carried out by taking the first sacrificial layer as a mask, and first lightly doped regions are formed on the side wall and the bottom surface of the first source drain opening. The number of the sacrificial layers can be effectively reduced through the process procedure, so that the production cost is reduced and the production efficiency is improved. In addition, the first lightly doped region is formed after the first source drain opening is formed, and the blocking of the first peripheral region is reduced, so that the ion implantation energy, the dosage and the ion implantation time during the formation of the first lightly doped region can be effectively reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to fig. 15 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 5, a substrate 200 is provided, where the substrate 200 includes a first region I, the first region I includes a first peripheral region a1 and a first core region B1, the first peripheral region a1 has a plurality of first dummy gate structures 201 arranged in parallel, a first size d1 is between adjacent first dummy gate structures 201, the first core region B1 has a plurality of second dummy gate structures 202 arranged in parallel, a second size d2 is between adjacent second dummy gate structures 202, and the second size d2 is smaller than the first size d 1.
In this embodiment, the substrate 200 includes a second region II, the second region II includes a second peripheral region a2 and a second core region B2, the second peripheral region a2 has a plurality of third dummy gate structures 203 arranged in parallel, a third dimension d3 is between adjacent third dummy gate structures 203, the second core region B2 has a plurality of fourth dummy gate structures 204 arranged in parallel, a fourth dimension d4 is between adjacent fourth dummy gate structures 204, and the fourth dimension d4 is smaller than the third dimension d 3.
In this embodiment, the substrate 200 includes: the first dummy gate structure 201 and the second dummy gate structure 202 respectively cross over the first fin portion.
In this embodiment, the substrate 200 further includes: a plurality of second fin portions (not labeled) located on the substrate, and the third dummy gate structure 203 and the fourth dummy gate structure 204 respectively cross the second fin portions.
In this embodiment, the first region I and the second region II are used to form different types of transistor structures, and the transistor structures formed on the first peripheral region a1 and the second peripheral region a2 operate in a high-voltage state, so in order to overcome the hot carrier injection effect of the transistors, a Lightly Doped Drain (LDD) needs to be formed in the transistor structures of the first peripheral region a1 and the second peripheral region a 2.
Referring to fig. 6, a first sacrificial layer 217 exposing the first region I is formed on the substrate 200.
In this embodiment, the method for forming the first sacrificial layer 217 includes: forming an initial first sacrificial layer (not shown) on the substrate 200, the initial first sacrificial layer covering the first and second regions I and II; and removing the initial first sacrificial layer on the first region I by using a patterning process to form the first sacrificial layer 217.
In this embodiment, the first sacrificial layer 217 is formed by an atomic layer deposition process.
Referring to fig. 7, with the first sacrificial layer 217 as a mask, a plurality of first source-drain openings 205 are formed in the first peripheral region a1, the first source-drain openings 205 are located between adjacent first dummy gate structures 201, a plurality of second source-drain openings 206 are formed in the first core region B1, and the second source-drain openings 206 are located between adjacent second dummy gate structures 202.
In this embodiment, the method for forming the first source-drain opening 205 and the second source-drain opening 206 includes: and etching the first peripheral region a1 and the first core region B1 by using the first sacrificial layer 217, the first dummy gate structure 201 and the second dummy gate structure 202 as masks to form the first source/drain opening 205 and the second source/drain opening 206.
Referring to fig. 8, after the first source/drain opening 205 and the second source/drain opening 206 are formed, ion tilt implantation is performed on the first region I by using the first sacrificial layer 217 as a mask, a first lightly doped region 207 is formed on a sidewall and a bottom surface of the first source/drain opening 205, and first ions are contained in the first lightly doped region 207.
In this embodiment, a first sacrificial layer 217 exposing the first region I is formed on the substrate 200, and the first source-drain opening 205 and the second source-drain opening 206 are formed by using the first sacrificial layer 217 as a mask; after forming the first source-drain opening 205 and the second source-drain opening 206, continuing to perform ion tilt implantation with the first sacrificial layer 217 as a mask, and forming a first lightly doped region 207 only on the sidewall and the bottom surface of the first source-drain opening 205. The first sacrificial layer 217 can simultaneously complete the first source/drain opening 205, the second source/drain opening 206 and the process of ion tilt implantation, so as to effectively reduce the number of sacrificial layers, thereby reducing the production cost and improving the production efficiency. In addition, the first lightly doped region 207 is formed after the first source-drain opening 205 is formed, and because the blocking of the first peripheral region a1 is reduced, the ion implantation energy, the ion implantation dose and the ion implantation time during the formation of the first lightly doped region 207 can be effectively reduced.
In this embodiment, since the density of the transistor structures in the first peripheral region a1 is less than that in the first core region B1, an ion tilt implantation process may be employed to ensure that the first lightly doped region 207 is formed only on the sidewall and bottom surface of the first source drain opening 205.
In this embodiment, the implantation angle for performing the ion tilt implantation on the first region I is related to the first size d1, the second size d2, the height h1 of the first dummy gate structure 201, the height h2 of the second dummy gate structure 202, the aspect ratio of the first source/drain opening 205, and the aspect ratio of the second source/drain opening 206, and a shadow effect (shadowing effect) of the ion tilt implantation is utilized, so that the first lightly doped region 207 is finally formed only on the sidewall and the bottom surface of the first source/drain opening 205.
Referring to fig. 9, after the first lightly doped region 207 is formed, a first source-drain doping layer 208 is formed in the first source-drain opening 205 by using the first sacrificial layer 217 as a mask, a second source-drain doping layer 209 is formed in the second source-drain opening 206, and second ions are contained in the first source-drain doping layer 208 and the second source-drain doping layer 209.
In this embodiment, the method for forming the first source-drain doping layer 208 and the second source-drain doping layer 209 includes: forming a first epitaxial layer (not shown) in the first source/drain opening 205 and a second epitaxial layer (not shown) in the second source/drain opening 206 by using an epitaxial growth process; in the process of forming the first epitaxial layer, doping the second ions in the first epitaxial layer by adopting an in-situ doping process to form the first source-drain doping layer 208; in the process of forming the second epitaxial layer, the second ions are doped in the second epitaxial layer by using an in-situ doping process to form the second source/drain doping layer 209.
Referring to fig. 10, after the first source-drain doping layer 208 and the second source-drain doping layer 209 are formed, the first sacrificial layer 217 is removed; a second sacrificial layer 210 exposing the second region II is formed on the substrate 200.
In this embodiment, the method for forming the second sacrificial layer 210 includes: forming an initial second sacrificial layer (not shown) on the substrate 200, the initial second sacrificial layer covering the first and second regions I and II; and removing the initial second sacrificial layer on the second region II by using a patterning process to form the second sacrificial layer 210.
In this embodiment, the second sacrificial layer 210 is formed by an atomic layer deposition process.
Referring to fig. 11, with the second sacrificial layer 210 as a mask, a plurality of third source/drain openings 211 are formed in the second peripheral region a2, the third source/drain openings 211 are located between adjacent third dummy gate structures 203, a plurality of fourth source/drain openings 212 are formed in the second core region B2, and the fourth source/drain openings 212 are located between adjacent fourth dummy gate structures 204.
In this embodiment, the forming method of the third source/drain opening 211 and the fourth source/drain opening 212 includes: and etching the second peripheral region a2 and the second core region B2 by using the second sacrificial layer 210, the third dummy gate structure 203 and the fourth dummy gate structure 204 as masks to form the third source-drain opening 211 and the fourth source-drain opening 212.
Referring to fig. 12, after the third source/drain opening 211 and the fourth source/drain opening 212 are formed, ion tilt implantation is performed on the second region II using the second sacrificial layer 210 as a mask, a second lightly doped region 213 is formed on the sidewall and the bottom surface of the third source/drain opening 211, third ions are contained in the second lightly doped region 213, and the electrical type of the third ions is opposite to that of the first ions.
In the present embodiment, since the density of the transistor structures in the second peripheral region a2 is less than the density of the transistor structures in the second core region B2, an ion tilt implantation process may be employed to ensure that the second lightly doped region 213 is formed only on the sidewall and bottom surface of the third source/drain opening 211.
In this embodiment, the implantation angle for performing the ion tilt implantation on the second region II is related to the third dimension d3, the fourth dimension d4, the height h3 of the third dummy gate structure 203, the height h4 of the fourth dummy gate structure 204, the aspect ratio of the third source/drain opening 211, and the aspect ratio of the fourth source/drain opening 212, and a second lightly doped region 213 is finally formed only on the sidewall and the bottom surface of the third source/drain opening 211 by using a shadow effect (shadowing effect) of the ion tilt implantation.
In this embodiment, the first ions are N-type ions, and the third ions are P-type ions; in other embodiments, the first ions may also be P-type ions, and the third ions may be N-type ions.
Referring to fig. 13, after the second lightly doped region 213 is formed, a third source drain doped layer 214 is formed in the third source drain opening 211 and a fourth source drain doped layer 215 is formed in the fourth source drain opening 212 by using the second sacrificial layer 210 as a mask, wherein fourth ions are provided in the third source drain doped layer 214 and the fourth source drain doped layer 215, and the electrical type of the fourth ions is opposite to that of the second ions.
In this embodiment, the method for forming the third source-drain doping layer 214 and the fourth source-drain doping layer 215 includes: forming a third epitaxial layer (not shown) in the third source-drain opening 211 and a fourth epitaxial layer (not shown) in the fourth source-drain opening 212 by using an epitaxial growth process; in the process of forming the third epitaxial layer, doping the fourth ions in the third epitaxial layer by using an in-situ doping process to form the third source-drain doping layer 214; in the process of forming the fourth epitaxial layer, the fourth ions are doped in the fourth epitaxial layer by using an in-situ doping process to form the fourth source-drain doping layer 215.
In this embodiment, the second ions are N-type ions, and the fourth ions are P-type ions; in other embodiments, the second ions may also be P-type ions, and the fourth ions may be N-type ions.
Referring to fig. 14, after the third source/drain doped layer 214 and the fourth source/drain doped layer 215 are formed, the second sacrificial layer 210 is removed; a dielectric layer 216 is formed on the substrate 200, and the dielectric layer 216 covers the sidewalls of the first dummy gate structure 201, the second dummy gate structure 202, the third dummy gate structure 203, and the fourth dummy gate structure 204.
In this embodiment, the dielectric layer 216 is made of silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
Referring to fig. 15, after the dielectric layer 216 is formed, a first gate structure 221, a second gate structure 218, a third gate structure 219, and a fourth gate structure 220 are formed in the dielectric layer 210.
In this embodiment, the forming method of the first gate structure 221, the second gate structure 218, the third gate structure 219 and the fourth gate structure 220 includes: removing the first dummy gate structure 201, and forming a first gate opening (not marked) in the dielectric layer 216; removing the second dummy gate structure 202, and forming a second gate opening (not labeled) in the dielectric layer 216; removing the third dummy gate structure 203, and forming a third gate opening (not labeled) in the dielectric layer 216; removing the fourth dummy gate structure 204, and forming a fourth gate opening (not labeled) in the dielectric layer 216; forming a first gate structure 221 in the first gate opening; forming a second gate structure 218 within the second gate opening; forming a third gate structure 219 within the third gate opening; a fourth gate structure 220 is formed within the fourth gate opening.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region, the first region comprises a first peripheral region and a first core region, a plurality of first dummy gate structures are arranged in parallel on the first peripheral region, a first size is arranged between every two adjacent first dummy gate structures, a plurality of second dummy gate structures are arranged in parallel on the first core region, a second size is arranged between every two adjacent second dummy gate structures, and the second size is smaller than the first size;
forming a first sacrificial layer on the substrate to expose the first region;
forming a plurality of first source-drain openings in the first peripheral region by taking the first sacrificial layer as a mask, wherein the first source-drain openings are positioned between adjacent first dummy gate structures, and a plurality of second source-drain openings are formed in the first core region and positioned between adjacent second dummy gate structures;
after the first source drain opening and the second source drain opening are formed, ion inclined injection treatment is carried out on the first region by taking the first sacrificial layer as a mask, a first light doping region is formed on the side wall and the bottom surface of the first source drain opening, and first ions are arranged in the first light doping region.
2. The method of forming a semiconductor structure of claim 1, further comprising, after forming the first lightly doped region: and forming a first source-drain doping layer in the first source-drain opening by taking the first sacrificial layer as a mask, forming a second source-drain doping layer in the second source-drain opening, wherein the first source-drain doping layer and the second source-drain doping layer are internally provided with second ions.
3. The method of claim 2, wherein the substrate comprises a second region, the second region comprises a second peripheral region and a second core region, the second peripheral region has a plurality of third dummy gate structures arranged in parallel, a third dimension is between adjacent third dummy gate structures, the second core region has a plurality of fourth dummy gate structures arranged in parallel, a fourth dimension is between adjacent fourth dummy gate structures, and the fourth dimension is smaller than the third dimension.
4. The method for forming a semiconductor structure according to claim 3, further comprising, after forming the first source drain doping layer and the second source drain doping layer: removing the first sacrificial layer; forming a second sacrificial layer on the substrate to expose the second region; forming a plurality of third source-drain openings in the second peripheral region by using the second sacrificial layer as a mask, wherein the third source-drain openings are located between adjacent third dummy gate structures, a plurality of fourth source-drain openings are formed in the second core region, and the fourth source-drain openings are located between adjacent fourth dummy gate structures; after the third source drain opening and the fourth source drain opening are formed, the second sacrificial layer is used as a mask, ion inclined injection treatment is carried out on the second region, a second light doping region is formed on the side wall and the bottom surface of the third source drain opening, third ions are arranged in the second light doping region, and the electrical type of the third ions is opposite to that of the first ions.
5. The method of forming a semiconductor structure of claim 4, further comprising, after forming the second lightly doped region: and forming a third source drain doping layer in the third source drain opening by taking the second sacrificial layer as a mask, forming a fourth source drain doping layer in the fourth source drain opening, wherein fourth ions are arranged in the third source drain doping layer and the fourth source drain doping layer, and the electrical type of the fourth ions is opposite to that of the second ions.
6. The method for forming the semiconductor structure according to claim 1, wherein the method for forming the first source-drain opening and the second source-drain opening comprises: and etching the first peripheral region and the first core region by using the first sacrificial layer, the first dummy gate structure and the second dummy gate structure as masks to form the first source drain opening and the second source drain opening.
7. The method for forming the semiconductor structure according to claim 4, wherein the method for forming the third source-drain opening and the fourth source-drain opening comprises: and etching the second peripheral region and the second core region by using the second sacrificial layer, the third dummy gate structure and the fourth dummy gate structure as masks to form the third source-drain opening and the fourth source-drain opening.
8. The method of forming a semiconductor structure of claim 4, wherein the first ions comprise: n-type ions or P-type ions; the third ions include: p-type ions or N-type ions.
9. The method of forming a semiconductor structure of claim 5, wherein the second ions comprise: n-type ions or P-type ions; the fourth ions include: p-type ions or N-type ions.
10. The method of forming a semiconductor structure of claim 3, wherein the method of forming the first sacrificial layer comprises: forming an initial first sacrificial layer on the substrate, the initial first sacrificial layer covering the first and second regions; and removing the initial first sacrificial layer on the first region by adopting a patterning process to form the first sacrificial layer.
11. The method of forming a semiconductor structure according to claim 4, wherein the method of forming the second sacrificial layer comprises: forming an initial second sacrificial layer on the substrate, the initial second sacrificial layer covering the first and second regions; and removing the initial second sacrificial layer on the second region by adopting a patterning process to form the second sacrificial layer.
12. The method for forming a semiconductor structure according to claim 5, further comprising, after forming the third source-drain doping layer and the fourth source-drain doping layer: removing the second sacrificial layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side walls of the first pseudo gate structure, the second pseudo gate structure, the third pseudo gate structure and the fourth pseudo gate structure.
13. The method of forming a semiconductor structure of claim 12, further comprising, after forming the dielectric layer: removing the first dummy gate structure, and forming a first gate opening in the dielectric layer; removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer; removing the third pseudo gate structure, and forming a third gate opening in the dielectric layer; removing the fourth pseudo gate structure, and forming a fourth gate opening in the dielectric layer; forming a first gate structure in the first gate opening; forming a second gate structure in the second gate opening; forming a third gate structure in the third gate opening; and forming a fourth gate structure in the fourth gate opening.
14. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the first dummy gate structure and the second dummy gate structure respectively cross the first fin parts.
CN202110106489.0A 2021-01-26 2021-01-26 Method for forming semiconductor structure Pending CN114792629A (en)

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