JP2009004800A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for obtaining MISFET having desired property by adjusting the isolation width of an element isolation section. <P>SOLUTION: The isolation width La and isolation with La' of an element isolation part 4 are made relatively narrow so that the influence of a stress to be imposed on the channel region of a second MISFETQ<SB>2</SB>can be increased. The change of a threshold voltage is made relatively large, and the isolation width Lb and isolation width Lb' of the element isolation part 4 are made relatively wide so that the influence of a stress to be imposed on the channel region of the fourth MISFETQ<SB>4</SB>can be reduced, and the change of the threshold voltage is made relatively small. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a metal insulator semiconductor field effect transistor (MISFET).

  As one of element isolation techniques for electrically separating adjacent semiconductor elements from each other, a trench having a depth of about 0.3 to 0.4 μm is provided in a substrate serving as an element isolation region, and an insulating film is embedded therein. There is a groove isolation formed by this.

  The following is a groove isolation forming technique studied by the present inventors, and the outline thereof is as follows.

  First, the surface of the substrate is etched to form a groove having a depth of about 0.3 to 0.4 μm in the element isolation region. Subsequently, after the substrate is thermally oxidized at about 900 ° C., a silicon oxide film having a thickness of about 0.6 μm is deposited on the substrate including the inside of the groove by a CVD (chemical vapor deposition) method. This silicon oxide film is deposited by a plasma CVD method using, for example, oxygen (or ozone) and tetraethoxysilane (TEOS) as a source gas. Thereafter, a heat treatment at about 1000 ° C. is performed to densify the film. Next, the surface of the silicon oxide film is polished and planarized by a CMP (chemical mechanical polishing) method to fill the inside of the groove with a silicon oxide film, thereby forming groove isolation on the main surface of the substrate.

For example, “ULSI Process Technology” issued on June 10, 1997, published by Baifukan, edited by Hara, P236 to P238 (Non-patent Document 1) has a description regarding groove element isolation.
Hara edited by "ULSI Process Technology" Baifukan, June 10, 1997, P236-P238

  However, as a result of studies by the present inventors, in a complementary metal oxide semiconductor (CMOS) device manufactured by a process with a minimum processing size of 0.14 μm, variations occur in threshold voltage or driving current. For example, in an n-channel MISFET, It became clear that the threshold voltage fluctuated by about 40 to 70 mV.

  This phenomenon appears when the isolation width of the groove isolation becomes narrower than about 0.35 μm, and becomes more prominent as the isolation width decreases. Therefore, the silicon oxide film embedded in the groove and This was presumed to be due to the effect of stress generated at the corner of the groove due to the difference in thermal expansion coefficient with the substrate.

  Note that fluctuations in the threshold voltage of the MISFET can be prevented, for example, by increasing the impurity concentration of the substrate. However, since ion implantation for adjusting the threshold voltage is required, the number of manufacturing steps increases, and further, the problem arises that the junction electric field is strengthened by increasing the concentration of the substrate.

  An object of the present invention is to provide a technique capable of obtaining a MISFET having desired characteristics by adjusting the isolation width of an element isolation part.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention controls the threshold voltage or drive current of the MISFET by adjusting at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed.

  Further, the present invention forms a MISFET having a desired threshold voltage or drive current by adjusting at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed. It is.

Furthermore, the outline of other inventions of the present application is briefly shown in sections. That is,
1. The semiconductor integrated circuit device of the present invention controls the threshold voltage or driving current of the MISFET by adjusting at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction.
2. The semiconductor integrated circuit device according to the present invention includes at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed, and at least one of the isolation region in the gate length direction from the gate electrode of the MISFET. The threshold voltage or drive current of the MISFET is controlled by adjusting the distance.
3. According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a MISFET having a desired threshold voltage or drive current is formed by adjusting at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction To do.
4). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed, and from the gate electrode of the MISFET to the element isolation portion in the gate length direction. By adjusting at least one of the distances, a MISFET having a desired threshold voltage or drive current is formed.
5). The semiconductor integrated circuit device of the present invention has a first MISFET and a second MISFET having different threshold voltages on the main surface of the substrate, and is surrounded by an element isolation portion having a relatively wide isolation width. A first MISFET is formed in one active region, and a second MISFET is formed in a second active region surrounded by an element isolation portion having a relatively small isolation width at least in the gate length direction.
6). A semiconductor integrated circuit device according to the present invention has a first MISFET and a second MISFET having different threshold voltages on a main surface of a substrate, and a gate electrode of a first active region in which the first MISFET is formed Is relatively large, and the distance between the gate electrode of the second active region where the second MISFET is formed and the element isolation portion in the gate length direction is relatively large. It is a small one.
7). The semiconductor integrated circuit device of the present invention has a first MISFET and a second MISFET having different threshold voltages on the main surface of the substrate, and is surrounded by an element isolation portion having a relatively wide isolation width. A first MISFET is formed in one active region, and a second MISFET is formed in a second active region surrounded by an element isolation portion having a relatively narrow isolation width in at least one of the gate length directions. The distance from the gate electrode in the active region to the element isolation portion in the gate length direction is relatively large and at least one distance from the gate electrode in the second active region to the element isolation portion in the gate length direction is relatively small. is there.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By adjusting the isolation width of the element isolation part that electrically isolates the MISFET, a MISFET having desired characteristics can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  FIG. 1 is a graph showing threshold voltages of a first group of n-channel MISFETs and threshold voltages of a second group of n-channel MISFETs for explaining an embodiment of the present invention. The first group of n-channel MISFETs are formed in an active region surrounded by trench isolation having a relatively wide isolation width, and the second group of n-channel MISFETs are trench isolations having a relatively narrow isolation width. It is formed in the active region surrounded by.

  The threshold voltage of the first group of n-channel MISFETs is about 0.07 to 0.09V, while the threshold voltage of the second group of n-channel MISFETs is about 0.11 to 0.14V. The threshold voltage of the first group of n-channel MISFETs increases by about 0.04 to 0.05V.

  FIG. 2 is a graph showing the relationship between the intrinsic stress of groove isolation and the separation width of groove isolation, for explaining an embodiment of the present invention.

  The intrinsic stress in the groove isolation having a separation width wider than about 2 μm is almost constant, and is about −230 MPa. However, in the groove isolation whose separation width is narrower than about 2 μm, the intrinsic stress increases remarkably as the separation width becomes narrower, and the intrinsic stress when the separation width is about 0.25 μm is about −2000 MPa.

  That is, from FIG. 1 and FIG. 2, the stress applied to the channel region of the active region increases as the isolation width of the trench isolation that electrically isolates the adjacent active regions becomes narrower. The voltage is considered to fluctuate.

  FIG. 3A is a graph showing the relationship between the stress exerted on the channel region of the MISFET and the number of gate electrodes arranged in the active region for explaining an embodiment of the present invention. FIG. 2B is a cross-sectional view of the main part of the substrate showing the arrangement of the gate electrode, in which A indicates the active region, STI indicates the trench isolation, and G indicates the gate electrode of the MISFET.

Groove Isolation separation width L ₁ of the STI surrounding the active region A, regardless of the number of the gate electrode, all of which are about 0.25 [mu] m. Further, the distance _{L 2} is about 0.3μm between the central portion and the groove isolation ends of STI of the gate electrode of the MISFET arranged closest to the groove isolation STI, adjacent MISFET is about 0.5μm intervals (L ₃ ). FIG. 3 (a) shows the stress measured in the channel region under the center of the gate electrode of the MISFET, and shows one trench isolation STI from the center of the active region surrounded by the dotted line in FIG. 3 (b). The stress in the region to the end is shown.

  When two gate electrodes G are disposed in the active region A (denoted as a two-gate structure in the figure), the stress in the channel region of the MISFET located approximately 0.3 μm from the end of the trench isolation STI is − It increases to nearly 800 MPa.

  However, when four gate electrodes G are arranged in the active region A (denoted as a four-gate structure in the figure), the stress in the channel region of the MISFET located about 0.3 μm from the end of the trench isolation STI is The stress in the channel region of the MISFET located about 0.8 μm from the end of the trench isolation STI is reduced to about −350 MPa.

  Further, when 10 gate electrodes G are arranged in the active region A (denoted as 10 gate structure in the drawing) and when 30 gate electrodes G are arranged in the active region A (30 gate structure in the drawing). The stress of the channel region of the MISFET located about 0.3 μm from the end of the trench isolation STI is about −600 MPa, and the channel region of the MISFET located about 0.8 μm from the end of the trench isolation STI However, the stress in the channel region of the MISFET located in the active region separated by about 1.3 μm or more from the end of the trench isolation STI is reduced to about −200 MPa or less.

  That is, it is considered that as the distance from the end of the trench isolation STI increases, the stress exerted on the channel region of the active region A decreases, thereby reducing the amount of change in the threshold voltage of the MISFET.

  Note that the threshold voltage of the MISFET is considered to increase or decrease from the threshold voltage of the MISFET that is hardly affected by the stress due to an increase in stress applied to the channel region. However, in the embodiment of the present invention, the threshold voltage of the MISFET is increased by an increase in stress applied to the channel region, and the mode will be described below.

FIG. 4 is a main part plan view showing a first arrangement example of MISFETs according to one embodiment of the present invention. The description uses the first MISFET to the fifth MISFET arranged based on the results obtained in FIGS. In the figure, _{Q 1} is a MISFET, _{Q 2} is a MISFET, _{Q 3} is a MISFET, _{Q 4} is a MISFETs, _{Q 5} denotes a first 5MISFET.

The first MISFET Q ₁ to the _fifth MISFET Q ₅ are arranged on the main surface of the substrate 1, and the widths (gate lengths) Lg of the gate electrodes 2 of the first MISFET Q ₁ to the _fifth MISFET Q ₅ are substantially the same. The gate length Lg can be set to about 0.14 μm, for example. The element isolation portion 4 that surrounds the active region 3 and isolates the _first MISFET Q ₁ to the _fifth MISFET Q ₅ from each other is configured by, for example, trench isolation. The first MISFET Q ₁ to the _fifth MISFET Q ₅ are arranged in the gate length direction, and the isolation width of the element isolation unit 4 is 0 for the MISFET arranged in the extending direction of the gate electrode 2 (gate width direction). It is assumed that the element isolation portion 4 in the gate width direction does not affect the characteristics of the first MISFET Q ₁ to the _fifth MISFET Q ₅ , for example, the threshold voltage or the drive current.

The 1MISFETQ ₁ and the 2MISFETQ ₂ and the separation width of the element isolation portion 4 separating the La and the 2MISFETQ ₂ and the 3MISFETQ of ₃ and the isolation unit 4 for separating the separation width La 'is provided relatively narrow. Thus the influence of the stress on the first 2MISFETQ ₂ channel region is increased, it can be relatively large change in threshold voltage due to stress. The separation width La can be set to, for example, about 0.25 μm. On the other hand, the isolation width Lb of the element isolation unit 4 that isolates the _third MISFET Q ₃ and the _fourth MISFET Q ₄ and the isolation width Lb ′ of the element isolation unit 4 that isolates the fourth MISFET Q ₄ and the _fifth MISFET Q ₅ are relatively wide. Yes. As a result, the influence of the stress on the channel region of the _fourth MISFET Q4 is reduced, and the change in the threshold voltage due to the stress can be made relatively small.

Here, the distance the end of the isolation portion 4 from the side wall of the 3MISFETQ ₃ side of the gate electrode 2 of the 4MISFETQ ₄ from the side wall of the 1MISFETQ ₁ side of the gate electrode 2 of the 2MISFETQ ₂ to the end portion of the isolation portion 4 The distance to the part is substantially the same distance Lc. The distance Lc can be set to about 0.305 μm, for example. Further, the distance Lc ′ from the side wall of the gate electrode 2 of the second MISFET Q ₂ on the side of the _third MISFET Q _{3 to the} end of the element isolation part 4 and the side wall of the gate electrode 2 of the _fourth MISFET Q ₄ on the side of the _fifth MISFET Q ₅ of the element isolation part 4. The relationship with the distance Lc ″ to the end can be arbitrarily selected.

That is, La ≦ La ′
Lb ≦ Lb ′
Lc ≦ Lc ′, Lc ″
At this time, if La <Lb, the amount of change in the threshold voltage of the _second MISFET Q ₂ (ΔVth (Q ₂ )) and the amount of change in the threshold voltage of the _fourth MISFET Q ₄ (ΔVth (Q ₄ )) The relationship satisfies the following formula.

ΔVth (Q ₂ )> ΔVth (Q ₄ )
FIG. 5 is a main part plan view showing a second arrangement example of the MISFET according to the embodiment of the present invention. As in FIG. 1, the first MISFET Q ₁ to the _fifth MISFET Q ₅ are used for the description.

From the distance Lc and the side wall of the first 3MISFETQ ₃ side gate electrode 2 of the 2MISFETQ ₂ from the side wall of the 1MISFETQ ₁ side of the gate electrode 2 of the 2MISFETQ ₂ to the end portion of the isolation portion 4 to the end portion of the isolation portion 4 The distance Lc ′ is relatively narrow. Thus the influence of the stress on the first 2MISFETQ ₂ channel region is increased, it can be relatively large change in threshold voltage due to stress. On the other hand, the distance Ld from the side wall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _third MISFET Q ₃ side to the end of the element isolation part 4 and the end of the element isolation part 4 from the side wall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _fifth MISFET Q ₅ side. The distance Ld ′ to the portion is relatively wide. As a result, the influence of the stress on the channel region of the _fourth MISFET Q4 is reduced, and the change in the threshold voltage due to the stress can be made relatively small.

Here, the isolation width of the element isolation unit 4 that isolates the first MISFET Q ₁ and the second MISFET Q ₂ and the isolation width of the element isolation unit 4 that isolates the third MISFET Q ₃ and the _fourth MISFET Q ₄ are substantially the same isolation width La. is there. The separation width La can be set to, for example, about 0.25 μm. Further, the separation width of the element isolation portion 4 separating the first 2MISFETQ ₂ and the 3MISFETQ _3, the first 4MISFETQ ₄ and the 5MISFETQ ₅ and the separation width of the element isolation portion 4 which separates the almost the same separation width La ' is there.

That is, La ≦ La ′
Lc ≦ Lc ′
Ld ≦ Ld ′
When, if the Lc <Ld and Lc '<Ld', the change amount of the 2MISFETQ ₂ threshold voltage _{(ΔVth (Q} 2)) and the amount of change in threshold voltage of the 4MISFETQ ₄ (ΔVth ( The relationship with Q ₄ )) satisfies the following formula.

ΔVth (Q ₂ )> ΔVth (Q ₄ )
FIG. 6 is a plan view of an essential part showing a third arrangement example of MISFETs according to one embodiment of the present invention. As in FIG. 1, the first MISFET Q ₁ to the _fifth MISFET Q ₅ are used for the description.

The 1MISFETQ ₁ and the 2MISFETQ ₂ and the separation width of the element isolation portion 4 separating the La and the 2MISFETQ ₂ and the 3MISFETQ of ₃ and the isolation unit 4 for separating the separation width La 'is provided relatively narrow. The separation width La can be set to, for example, about 0.25 μm. Furthermore, the distance Lc and the gate electrode 2 of the 2MISFETQ ₂ second 3MISFETQ ₃ end of the element isolation portion 4 from the side wall of the side wall of the 1MISFETQ ₁ side of the gate electrode 2 to the end portion of the element isolation portion 4 of the 2MISFETQ ₂ The distance Lc ′ to the portion is relatively narrow. Thus the influence of the stress on the first 2MISFETQ ₂ channel region is increased, it can be relatively large change in threshold voltage due to stress.

On the other hand, the isolation width Lb of the element isolation part 4 that isolates the _third MISFET Q ₃ and the _fourth MISFET Q ₄ is relatively wide. Furthermore, the distance Ld from the side wall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _fifth MISFET Q ₅ side to the end of the element isolation groove 4 is relatively wide. As a result, the influence of the stress on the channel region of the _fourth MISFET Q4 is reduced, and the change in the threshold voltage due to the stress can be made relatively small.

That is, La ≦ La ′
Lc ≦ Lc ′
When, La <Lb, Lc '<if the Ld, the change amount of the 2MISFETQ ₂ threshold voltage _{(ΔVth (Q} 2)) and the amount of change in threshold voltage of the 4MISFETQ ₄ (ΔVth (Q ₄ )) satisfies the following formula.

ΔVth (Q ₂ )> ΔVth (Q ₄ )
FIG. 7 is a main part plan view showing a fourth arrangement example of MISFETs according to one embodiment of the present invention. In the description, the first MISFET Q ₁ to the _fourth MISFET Q ₄ arranged based on the results obtained in FIGS. 1 to 3 are used. Dummy active regions DA ₁ and DA ₂ are disposed adjacent to both sides of the active region where the first MISFET Q ₁ is disposed. The dummy active regions DA ₁ and DA ₂ can be used for power supply, for example.

The 1MISFETQ ₁ and one of the separation width of the dummy active regions DA ₁ and the element isolation portion 4 separating the La and the 1MISFETQ ₁ and the other dummy active region DA ₂ and the separation width La of the isolation unit 4 for separating 'the relative Is narrowly provided. Thus the influence of the stress on the first 1MISFETQ ₁ channel region is increased, it can be relatively large change in threshold voltage due to stress. The separation width La can be set to, for example, about 0.25 μm. On the other hand, the isolation width Lb of the element isolation unit 4 that isolates the second MISFET Q ₂ and the _third MISFET Q ₃ and the isolation width Lb ′ of the element isolation unit 4 that isolates the _third MISFET Q ₃ and the _fourth MISFET Q ₄ are relatively wide. Yes. As a result, the influence of the stress on the channel region of the _third MISFET Q3 is reduced, and the change in the threshold voltage due to the stress can be made relatively small.

Here, the distance from the side wall on the dummy active region DA ₁ side of the gate electrode 2 of the _first MISFET Q ₁ to the end of the element isolation part 4 and the side wall on the _second MISFET Q ₂ side of the gate electrode 2 of the _third MISFET Q ₃ are separated. Is approximately the same distance Lc. Further, the distance Lc ′ from the side wall on the dummy active region DA ₂ side of the gate electrode 2 of the _first MISFET Q ₁ to the end of the element isolation unit 4 and the side wall on the _fourth MISFET Q ₄ side of the gate electrode 2 of the _third MISFET Q ₃ are separated. The relationship with the distance Lc ″ to the end of 4 can be arbitrarily selected.

That is, La ≦ La ′
Lb ≦ Lb ′
Lc ≦ Lc ′, Lc ″
When, La <if the Lb, between the change amount of the 1MISFETQ ₂ threshold voltage _{(ΔVth (Q} 1)) and the amount of change in threshold voltage of the _{3MISFETQ 3 (ΔVth (Q 3)} ) The relationship satisfies the following formula.

ΔVth (Q ₁ )> ΔVth (Q ₃ )
FIG. 8 is a plan view of a principal part showing a fifth arrangement example of MISFETs according to one embodiment of the present invention. As in FIG. 7, the first MISFET Q ₁ to the _fourth MISFET Q ₄ and the dummy active regions DA ₁ and DA ₂ are used for the description.

The distance Lc from the side wall on the dummy active region DA ₁ side of the gate electrode 2 of the _first MISFET Q _{1 to} the end portion of the element isolation portion 4 and the side wall on the dummy active region DA ₂ side of the gate electrode 2 of the _first MISFET Q ₁ The distance Lc ′ to the end of is relatively narrow. Thus the influence of the stress on the first 1MISFETQ ₁ channel region is increased, it can be relatively large change in threshold voltage due to stress. On the other hand, the distance Ld and the 4MISFETQ ₄ end from the side wall of the element isolation portion 4 of the gate electrode 2 of the 3MISFETQ ₃ from the side wall of the 2MISFETQ ₂ side of the gate electrode 2 to the end portion of the element isolation portion 4 of the 3MISFETQ ₃ The distance Ld ′ to the portion is relatively wide. As a result, the influence of the stress on the channel region of the _third MISFET Q3 is reduced, and the change in the threshold voltage due to the stress can be made relatively small.

Here, the isolation width of the element isolation part 4 that isolates the _first MISFET Q ₁ and one dummy active region DA ₁ and the isolation width of the element isolation part 4 that isolates the second MISFET Q ₂ and the _third MISFET Q ₃ are substantially the same. The separation width La. Further, the separation width of the 1MISFETQ ₁ and the other dummy active region DA ₂ and the element isolation portion 4 for separating the, the separation width of the 3MISFETQ ₃ and element isolation portion 4 separating the first 4MISFETQ _4, substantially the same separation The width La ′.

That is, La ≦ La ′
Lc ≦ Lc ′
Ld ≦ Ld ′
At this time, if Lc <Ld and Lc ′ <Ld ′, the amount of change in the threshold voltage of the _first MISFET Q1 (ΔVth (Q ₁ )) and the amount of change in the threshold voltage of the _third MISFETQ3 (ΔVth ( The relationship with Q ₃ )) satisfies the following formula.

ΔVth (Q ₁ )> ΔVth (Q ₃ )
FIG. 9 is a main part plan view showing a sixth arrangement example of MISFETs according to one embodiment of the present invention. The description uses the first MISFET Q ₁ to the _fifth MISFET Q ₅ arranged based on the results obtained in FIGS.

Distance Lc from the side wall of the 1MISFETQ ₁ side of the gate electrode 2 to the end portion of the element isolation portion 4 of the 2MISFETQ ₂ is provided relatively narrow. Thus the influence of the stress on the first 2MISFETQ ₂ channel region is increased, it can be relatively large change in threshold voltage due to stress. At this time, the dummy gate electrode DG ₁ can be disposed in the active region 3 having a distance Lc ′ from the side wall on the _third MISFET Q ₃ side of the gate electrode 2 of the second MISFET Q ₂ to the end of the element isolation portion 4. The dummy gate electrode DG ₁ are electrically be used, but they do not affect the properties of the 2MISFETQ _2.

On the other hand, the distance Ld from the sidewall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _third MISFET Q ₃ side to the end of the element isolation portion 4 and the end of the element isolation portion 4 from the sidewall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _fifth MISFET Q ₅ side. The distance Ld ′ to the portion is relatively wide. As a result, the influence of the stress on the channel region of the _fourth MISFET Q4 is reduced, and the change in the threshold voltage due to the stress can be made relatively small. In this case, it is possible to arrange the dummy gate electrode DG ₂ from the sidewall of the 3MISFETQ ₃ side of the gate electrode 2 of the 4MISFETQ ₄ in the active region 3 of the distance Ld to the end of the isolation section 4. Similarly, it is possible to arrange the dummy gate electrode DG ₃ in the active region 3 of the distance the distance Ld 'from the side wall of the 5MISFETQ ₅ side of the gate electrode 2 of the 4MISFETQ ₄ to the end portion of the element isolation portion 4. The dummy gate electrodes DG ₂ and DG ₃ can be used electrically, but do not affect the characteristics of the _fourth MISFET Q ₄ .

Here, the isolation width of the element isolation unit 4 that isolates the first MISFET Q ₁ and the second MISFET Q ₂ and the isolation width of the element isolation unit 4 that isolates the third MISFET Q ₃ and the _fourth MISFET Q ₄ are substantially the same isolation width La. is there. Further, the separation width of the element isolation portion 4 separating the first 2MISFETQ ₂ and the 3MISFETQ _3, the first 4MISFETQ ₄ and the 5MISFETQ ₅ and the separation width of the element isolation portion 4 which separates the almost the same separation width La ' is there.

That is, La ≦ La ′
Lc ≦ Lc ′
Ld ≦ Ld ′
When, if the Lc <Ld and Lc '<Ld', the change amount of the 2MISFETQ ₂ threshold voltage _{(ΔVth (Q} 2)) and the amount of change in threshold voltage of the 4MISFETQ ₄ (ΔVth ( The relationship with Q ₄ )) satisfies the following formula.

ΔVth (Q ₂ )> ΔVth (Q ₄ )
FIG. 10 is a main part plan view showing a seventh arrangement example of MISFETs according to one embodiment of the present invention. As in FIG. 9, the description uses the first MISFET Q ₁ to the _fifth MISFET Q ₅ .

The 1MISFETQ ₁ and the 2MISFETQ ₂ and the separation width of the element isolation portion 4 separating the La and the 2MISFETQ ₂ and the 3MISFETQ of ₃ and the isolation unit 4 for separating the separation width La 'is provided relatively narrow. The distance Lc from the side wall of the 1MISFETQ ₁ side of the gate electrode 2 of the 2MISFETQ ₂ to the end portion of the isolation portion 4 is provided relatively narrow. Thus the influence of the stress on the first 2MISFETQ ₂ channel region is increased, it can be relatively large change in threshold voltage due to stress. At this time, the dummy gate electrode DG ₄ can be disposed in the active region 3 at a distance Lc ′ from the side wall on the _third MISFET Q ₃ side of the gate electrode 2 of the second MISFET Q ₂ to the end of the element isolation portion 4. The dummy gate electrode DG ₄ is electrically use, but they do not affect the properties of the 2MISFETQ _2.

On the other hand, the isolation width Lb of the element isolation part 4 that isolates the _third MISFET Q ₃ and the _fourth MISFET Q ₄ is relatively wide. The distance Ld from the side wall of the gate electrode 2 of the _fourth MISFET Q ₄ on the _fifth MISFET Q ₅ side to the end of the element isolation groove 4 is relatively wide. As a result, the influence of the stress on the channel region of the _fourth MISFET Q4 is reduced, and the change in the threshold voltage due to the stress can be made relatively small. In this case, it is possible to arrange the dummy gate electrode _DG 5, DG ₆ from the side wall of the 5MISFETQ ₅ side of the gate electrode 2 of the 4MISFETQ ₂ in the active region 3 of the distance Ld to the end of the isolation section 4. The dummy gate electrodes DG ₅ and DG ₆ can be used electrically, but do not affect the characteristics of the _fourth MISFET Q ₄ .

That is, La ≦ La ′
Lc ≦ Lc ′
When, La <Lb, Lc '<if the Ld, the change amount of the 2MISFETQ ₂ threshold voltage _{(ΔVth (Q} 2)) and the amount of change in threshold voltage of the 4MISFETQ ₄ (ΔVth (Q ₄ )) satisfies the following formula.

ΔVth (Q ₂ )> ΔVth (Q ₄ )
FIG. 11 is a schematic plan view showing an example of an arrangement region of MISFETs arranged on a semiconductor chip according to an embodiment of the present invention. In the figure, respective regions where three types of MISFETs having different threshold voltages are arranged are shown. The region LA is a MISFET placement region having a relatively low threshold voltage (low Vth), the region HA is a MISFET placement region having a relatively high threshold voltage (high Vth), and the region MA is The arrangement regions of MISFETs having a standard threshold voltage (standard Vth) are shown, and the threshold voltages of MISFETs arranged in the respective regions have a relationship of low Vth <standard Vth <high Vth.

  The region LA can be a circuit region where high speed operation is required, for example. In this region LA, the effect of stress on the MISFET is reduced by relatively widening the isolation width of the element isolation portion, and a MISFET having a relatively low threshold voltage is formed.

  Region HA can be, for example, a memory cell portion. In this region HA, the effect of stress on the MISFET is increased by relatively narrowing the isolation width of the element isolation portion, and a MISFET having a relatively high threshold voltage is formed.

  The area MA can be, for example, a gate array part, a general logic circuit part, or the like. In this region MA, by making the isolation width of the element isolation part narrower than the isolation width of the element isolation part formed in the area LA and wider than the isolation width of the element isolation part formed in the area HA, By setting the influence of stress on the MISFET to be moderate between the region LA and the region HA, a MISFET having a standard threshold voltage is formed.

  FIG. 12 is a schematic plan view showing an example of an arrangement region of a plurality of MISFETs constituting a gate array arranged on a semiconductor chip according to an embodiment of the present invention. In the figure, the region where the MISFET is formed is indicated by a rectangle.

In the region GA ₁ , cell rows are periodically provided according to a relatively wide isolation width of the element isolation portion, and a circuit that requires a relatively low threshold voltage is formed in this region GA _1. . In the region GA ₂ , cell rows are periodically provided according to the relatively narrow isolation width of the element isolation portion, and a circuit that requires a relatively high threshold voltage is formed in this region GA ₂ . Is done.

Next, schematic plan views of an inverter circuit according to an embodiment of the present invention are shown in FIGS. In the figure, a region PMOS is a region where a p-channel MISFET is formed, a region NMOS is a region where an n-channel MISFET is formed, 5 is an element isolation portion, 6 is an active region, 7 is a gate electrode (shaded hatching) 8 is a V _DD power supply wiring, 9 is a _VSS power supply wiring, 10 is an input signal wiring, 11 is an output signal wiring, 12 is a contact hole connecting the active region and the wiring, 13 is a dummy active region, and 14 is A dummy gate electrode is shown.

  FIG. 13 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by relatively narrowing (La) the isolation width of the element isolation unit 5. FIG. It is a top view of the inverter circuit from which a relatively low threshold voltage is obtained by making isolation width relatively wide (Lb).

  FIG. 15 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by providing the dummy active region 13, and FIG. 16 does not provide a dummy active region, and the isolation width of the element isolation portion 5 is increased. It is a top view of the inverter circuit from which a relatively low threshold voltage is obtained by making it comparatively wide (Lb).

  FIG. 17 is a plan view of an inverter circuit in which a relatively high threshold voltage can be obtained by relatively narrowing (Lc) the width of the active region 6, and FIG. FIG. 5 is a plan view of an inverter circuit in which a relatively low threshold voltage can be obtained by widening (Ld). When the width of the active region 6 is relatively wide (Ld), the dummy gate electrode 14 can be provided in the active region 6.

  FIG. 19 shows an inverter in which a relatively high threshold voltage can be obtained by relatively narrowing (La) the isolation width of the element isolation section 5 and relatively narrowing (Lc) the width of the active region 6. FIG. 20 is a plan view of the circuit. FIG. 20 shows that one isolation width of the element isolation portion 5 is relatively wide (Lb) and the width of the active region 6 in contact with the other of the element isolation portion 5 is relatively wide. It is a top view of the inverter circuit from which a relatively low threshold voltage is obtained by this. When the width of the active region 6 is relatively wide (Ld), the dummy gate electrode 14 can be provided in the active region 6.

  Next, schematic plan views of a two-input NAND circuit according to an embodiment of the present invention are shown in FIGS.

  FIG. 21 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation unit 5, and FIG. FIG. 5 is a plan view of a two-input NAND circuit in which a relatively low threshold voltage can be obtained by relatively widening the width.

  FIG. 23 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by providing the dummy active region 13, and FIG. FIG. 5 is a plan view of a two-input NAND circuit in which a relatively low threshold voltage can be obtained by relatively widening the width.

  FIG. 25 is a plan view of a two-input NAND circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the width of the active region 6, and FIG. FIG. 6 is a plan view of a 2-input NAND circuit in which a relatively low threshold voltage can be obtained by widening. If the width of the active region 6 is relatively wide, the dummy gate electrode 14 can be provided in the active region 6.

  FIG. 27 is a plan view of a 2-input NAND circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation portion 5 and relatively narrowing the width of the active region 6. In FIG. 28, the isolation width of one of the element isolation portions 5 is relatively wide, and the width of the active region 6 in contact with the other of the element isolation portions 5 is relatively wide. It is a top view of the 2-input NAND circuit from which a threshold voltage is obtained. If the width of the active region 6 is relatively wide, the dummy gate electrode 14 can be provided in the active region 6.

  Next, schematic plan views of a 2-input NOR circuit according to an embodiment of the present invention are shown in FIGS.

  FIG. 29 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation unit 5, and FIG. It is a top view of a 2-input NOR circuit in which a relatively low threshold voltage is obtained by making the width relatively wide.

  FIG. 31 is a plan view of a two-input NOR circuit in which a relatively high threshold voltage can be obtained by providing the dummy active region 13, and FIG. 32 does not provide a dummy active region and isolation of the element isolation unit 5 is performed. It is a top view of a 2-input NOR circuit in which a relatively low threshold voltage is obtained by making the width relatively wide.

  FIG. 33 is a plan view of a 2-input NOR circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the width of the active region 6, and FIG. FIG. 6 is a plan view of a two-input NOR circuit that can obtain a relatively low threshold voltage by widening. If the width of the active region 6 is relatively wide, the dummy gate electrode 14 can be provided in the active region 6.

  FIG. 35 is a plan view of a 2-input NOR circuit in which a relatively high threshold voltage can be obtained by relatively narrowing the isolation width of the element isolation portion 5 and relatively narrowing the width of the active region 6. FIG. 36 shows that the isolation width of one of the element isolation portions 5 is relatively wide and the width of the active region 6 in contact with the other of the element isolation portions 5 is relatively wide. It is a top view of 2 input NOR circuit from which a threshold voltage is obtained. If the width of the active region 6 is relatively wide, the dummy gate electrode 14 can be provided in the active region 6.

  Next, an example of the manufacturing method of the CMOS device which is embodiment of this invention is demonstrated in order of a process using FIGS. 37-47. In the figure, a region A1 is a region where a CMOS device having a relatively thin gate insulating film and a relatively high threshold voltage is formed, and a region A2 is a relatively thin gate insulating film. A region A3 in which a CMOS device having a relatively thin threshold voltage is formed, and region A3 represents a region in which a CMOS device having a relatively thick gate insulating film is formed.

First, as shown in FIG. 37, a semiconductor substrate 21 made of a silicon single crystal having a specific resistance of about 10 Ωcm is prepared, and a shallow groove 22 is formed in the main surface of the semiconductor substrate 21. Thereafter, a thermal oxidation process is performed on the semiconductor substrate 21 to form a silicon oxide film (not shown). Further, after depositing a silicon oxide film 23, the silicon oxide film 23 is polished by a CMP method, and silicon oxide is only in the shallow groove 22. An element isolation portion is formed by leaving the film 23. At this time, the isolation width (L _H ) of the element isolation portion formed in the region A1 is relatively narrow, and the isolation width (L _L ) of the element isolation portion formed in the region A2 is relatively wide.

  Next, as shown in FIG. 38, using the patterned resist film 24 as a mask, p-type impurities such as boron (B) are ion-implanted into the regions A1 and A2 where the n-channel MISFETs are to be formed. A type well 25 is formed, and then an impurity for adjusting the threshold voltage of the n-channel MISFET is ion-implanted to form a threshold voltage control layer 26.

  Next, as shown in FIG. 39, after removing the resist film 24, the patterned resist film 27 is used as a mask to form n-type impurities such as phosphorous in the regions A1 and A2 where the p-channel MISFETs are to be formed. (P) is ion-implanted to form an n-type well 28, and then an impurity for adjusting the threshold voltage of the p-channel MISFET is ion-implanted to form a threshold voltage control layer 29.

  Next, as shown in FIG. 40, after removing the resist film 27, using the patterned resist film 30 as a mask, a p-type impurity such as boron is ion-implanted into the region A3 where the n-channel MISFET is to be formed. Then, a p-type well 31 is formed, and then an impurity for adjusting the threshold voltage of the n-channel MISFET is ion-implanted to form a threshold voltage control layer 32.

  Next, as shown in FIG. 41, after removing the resist film 30, the patterned resist film 33 is used as a mask, and an n-type impurity, for example, phosphorus is ion-implanted into the region of the region A3 where the p-channel MISFET is to be formed. Then, an n-type well 34 is formed, and then an impurity for adjusting the threshold voltage of the p-channel MISFET is ion-implanted to form a threshold voltage control layer 35.

  Next, after removing the resist film 33, a relatively thin gate insulating film is formed on the surface of the semiconductor substrate 21 in the regions A1 and A2, and a relatively thick gate insulating film is formed on the surface of the semiconductor substrate 1 in the region A3. Form. Examples of the method for forming the gate insulating film include the following methods.

  First, after cleaning the surface of the semiconductor substrate 21 with a hydrofluoric acid (HF) -based aqueous solution, the semiconductor substrate 21 is subjected to thermal oxidation treatment, and a silicon oxide film having a thickness of about 6 to 7 nm is formed on the surface of the semiconductor substrate 21. 36 is formed. Next, by using the patterned resist film as a mask, the silicon oxide film 36 in the regions A1 and A2 is removed, thereby leaving the silicon oxide film 36 in the region A3 as shown in FIG.

  Next, as shown in FIG. 43, by subjecting the semiconductor substrate 21 to thermal oxidation, a silicon oxide film of about 3 to 4 nm constituting the gate insulating film 37a is formed on the surface of the semiconductor substrate 21 in the regions A1 and A2. At the same time, a silicon oxide film of about 8 nm constituting the gate insulating film 37b is formed on the surface of the semiconductor substrate 21 in the region A3.

  Next, as shown in FIG. 44, for example, a polycrystalline silicon film to which an impurity is added is deposited on the semiconductor substrate 21 by the CVD method, and then this polycrystalline silicon film is formed using the patterned resist film as a mask. Etching is performed to form a gate electrode 38 composed of a polycrystalline silicon film.

Next, as shown in FIG. 45, the n-type wells 28 and 34 are covered with a resist film (not shown), and the n-type impurity, for example, is added to the p-type wells 25 and 31 using the gate electrode 38 of the n-channel MISFET as a mask. Arsenic (As) is ion-implanted to form a low-concentration n ⁻ type semiconductor region 39 constituting the source and drain of the n-channel MISFET. Similarly, the p-type wells 25 and 31 are covered with a resist film (not shown), and a p-type impurity such as boron fluoride (BF ₂ ) is added to the n-type wells 28 and 34 using the gate electrode 38 of the p-channel MISFET as a mask. Is implanted to form a low-concentration p ⁻ type semiconductor region 40 constituting the source and drain of the p-channel MISFET.

  Next, as shown in FIG. 46, a silicon oxide film deposited on the semiconductor substrate 21 by anisotropic etching is anisotropically etched by RIE (reactive ion etching) to form sidewall spacers 41 on the side walls of the gate electrode 38. To do.

Subsequently, the n-type wells 28 and 34 are covered with a resist film (not shown), and an n-type impurity such as arsenic is added to the p-type wells 25 and 31 using the gate electrode 38 and the sidewall spacer 41 of the n-channel MISFET as a mask. Ions are implanted to form a low concentration n ⁺ type semiconductor region 42 that constitutes the source and drain of the n-channel MISFET. Similarly, the p-type wells 25 and 31 are covered with a resist film (not shown), and a p-type impurity such as fluoride is added to the n-type wells 28 and 34 using the gate electrode 38 and the side wall spacer 41 of the p-channel MISFET as a mask. Boron is ion-implanted to form a low-concentration p ⁺ -type semiconductor region 43 that constitutes the source and drain of the p-channel MISFET. Thereafter, the semiconductor substrate 21 is heat-treated at 1000 ° C. for about 5 seconds, for example, to activate the n-type impurity and the p-type impurity implanted into the semiconductor substrate 21.

  Next, as shown in FIG. 47, after forming an interlayer insulating film 44 on the semiconductor substrate 21, the interlayer insulating film 44 is etched using the patterned resist film as a mask to reach the source and drain of the n-channel MISFET. Contact holes 45n and contact holes 45p reaching the source and drain of the p-channel MISFET are formed. Although not shown, a contact hole reaching the gate electrode 38 of the n-channel MISFET and the p-channel MISFET is formed at the same time.

  Next, a metal film, for example, tungsten (W) is deposited on the interlayer insulating film 44, and the metal film is buried in the contact holes 45n, 45p by planarizing the surface of the metal film by, for example, CMP. A plug 46 is formed. Thereafter, the metal film deposited on the upper layer of the interlayer insulating film 44 is etched to form the wiring layer 47, whereby the CMOS device is substantially completed.

In this manner, the isolation width (L _H ) of the element isolation portion formed in the region A1 is relatively narrow, and the isolation width (L _L ) of the element isolation portion formed in the region A2 is relatively wide. Thus, in the regions A1 and A2, the p-type well 25 of the n-channel MISFET, the threshold voltage control layer 26 of the n-channel MISFET, the n-type well 28 of the p-channel MISFET, and the threshold voltage control layer 29 of the p-channel MISFET Even in the same process, for example, the threshold voltage of the n-channel MISFET in the region A1 can be relatively high, and the threshold voltage of the n-channel MISFET in the region A2 can be relatively low. Therefore, compared with a manufacturing method in which the isolation width of the element isolation portion formed in the region A1 and the isolation width of the element isolation portion formed in the region A2 are the same, the number of steps including the lithography process can be reduced by six steps. In addition, two lithography masks can be reduced.

  Thus, according to the present embodiment, the MISFET is configured by adjusting the isolation width of the element isolation part for electrically isolating the MISFET, the distance from the gate electrode of the MISFET to the element isolation part, or both. To obtain desired characteristics, for example, threshold voltage or drive current, in each of a plurality of MISFETs even if the elements to be operated, for example, the gate length, the film thickness of the gate insulating film or the concentration of impurities introduced into the substrate are the same Can do. Furthermore, since manufacturing processes such as a lithography process and an ion implantation process can be reduced, manufacturing costs can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the threshold voltage of the MISFET increases due to an increase in the stress applied to the channel region has been described. The threshold voltage of the MISFET can be adjusted higher or lower than the voltage.

  Further, in the above-described embodiment, the element isolation portion is configured by trench isolation, but is not limited thereto, and may be configured by, for example, LOCOS (local oxidation of silicon), and the same effect can be obtained. .

  In the above embodiment, the threshold voltage is mainly exemplified as the characteristic of the MISFET that varies depending on the stress. However, other characteristics such as the drive current can also be varied depending on the stress.

  The method for manufacturing a semiconductor integrated circuit device of the present invention can be applied to a manufacturing process of a semiconductor integrated circuit device having a MISFET.

It is a graph which shows the threshold voltage of 1st group n-channel MISFET and the threshold voltage of 2nd group n-channel MISFET for demonstrating one embodiment of this invention. It is a graph which shows the relationship between the intrinsic stress of groove | channel isolation for demonstrating one embodiment of this invention, and the isolation | separation width | variety of groove | channel isolation. (A) is a graph showing the relationship between the stress exerted on the channel region of the MISFET and the number of gate electrodes arranged in the active region for explaining one embodiment of the present invention, and (b) is a gate electrode It is principal part sectional drawing of the board | substrate which shows arrangement | positioning. It is a principal part top view which shows the 1st example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 2nd example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 3rd example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 4th example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 5th example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 6th example of arrangement | positioning of MISFET which is one embodiment of this invention. It is a principal part top view which shows the 7th example of arrangement | positioning of MISFET which is one embodiment of this invention. 1 is a schematic plan view showing an arrangement region of MISFETs arranged on a semiconductor chip according to an embodiment of the present invention. 1 is a schematic plan view showing an example of an arrangement region of MISFETs arranged in a gate array portion on a semiconductor chip according to an embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. It is a plane schematic diagram of the inverter circuit which is one embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NAND circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. 1 is a schematic plan view of a 2-input NOR circuit according to an embodiment of the present invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the CMOS device which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Active region 4 Element isolation part 5 Element isolation part 6 Active region 7 Gate electrode 8 V _DD power supply wiring 9 V _SS power supply wiring 10 Input signal wiring 11 Output signal wiring 12 Contact hole 13 Dummy active region 14 Dummy gate Electrode 21 Semiconductor substrate 22 Shallow groove 23 Silicon oxide film 24 Resist film 25 P-type well 26 Threshold voltage control layer 27 Resist film 28 N-type well 29 Threshold voltage control layer 30 Resist film 31 p-type well 32 Threshold Voltage control layer 33 Resist film 34 N-type well 35 Threshold voltage control layer 36 Silicon oxide film 37a Gate insulating film 37b Gate insulating film 38 Gate electrode 39 n ⁻ type semiconductor region 40 p ⁻ type semiconductor region 41 Side wall spacer 42 n ⁺ -type semiconductor region 43 ^{p +} -type semiconductor region 44 interlayer insulating film 45n Contact hole 45p contact hole 46 plug 47 interconnect layer A active region STI trench isolation G gate electrode L ₁ separating the width L ₂ distance L ₃ interval Q ₁ first 1MISFET
Q ₂ 2nd MISFET
Q _{3 3rd} MISFET
Q _{4 4th} MISFET
Q _{5 5th} MISFET
Lg Gate length La Separation width La ′ Separation width Lb Separation width Lb ′ Separation width Lc Distance Lc ′ Distance Lc ″ Distance Ld Distance Ld ′ Distance DA ₁ dummy active region DA ₂ dummy active region DG ₁ dummy gate electrode DG ₂ dummy gate electrode DG ₃ dummy gate electrode DG ₄ dummy gate electrode DG ₅ dummy gate electrode DG ₆ dummy gate electrode HA region MA region LA region GA ₁ region GA ₂ region PMOS region NMOS region A1 region A2 region A3 region

Claims (8)

An element isolation portion in which an insulating film is embedded in a groove formed in a semiconductor substrate;
First, second, third, fourth, fifth and sixth active regions defined by the device isolation part;
An n-channel first MISFET formed in the second active region;
An n-channel second MISFET formed in the fifth active region,
In the gate length direction of the first MISFET, the second active region is disposed adjacent to the first and third active regions,
In the gate length direction of the second MISFET, the fifth active region is disposed adjacent to the fourth and sixth active regions,
An interval between the first active region and the second active region, an interval between the second active region and the third active region, an interval between the fourth active region and the fifth active region, and the fifth active region The distance between the region and the sixth active region is 2 μm or less,
The width from one end of the gate electrode of the first MISFET in the gate length direction of the first MISFET to the end of the second active region on the first active region side, and the first MISFET in the gate length direction of the first MISFET The width from the other end of the gate electrode of the second MISFET to the end of the second active region on the side of the third active region is determined from the one end of the gate electrode of the second MISFET in the gate length direction of the second MISFET, respectively. The width of the fourth active region to the end of the fifth active region, and the fifth active region on the sixth active region side from the other end of the gate electrode of the second MISFET in the gate length direction of the second MISFET By making the width smaller than the width to the end, the stress generated in the channel region of the first MISFET is reduced to the second M The semiconductor integrated circuit device being characterized in that larger than the stress generated in the channel region of the SFET. The semiconductor integrated circuit device according to claim 1.
The amount of change in the threshold voltage of the first MISFET that changes due to the stress generated in the channel region of the first MISFET is the amount of change in the threshold voltage of the second MISFET that changes due to the stress generated in the channel region of the second MISFET. A semiconductor integrated circuit device characterized by being larger than The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device according to claim 1, wherein a threshold voltage of the first MISFET is larger than a threshold voltage of the second MISFET. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device according to claim 1, wherein a driving current of the first MISFET is different from a driving current of the second MISFET. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The interval between the first active region and the second active region and the interval between the second active region and the third active region are respectively the interval between the fourth active region and the fifth active region, and A semiconductor integrated circuit device, wherein the distance between the fifth active region and the sixth active region is the same. In the semiconductor integrated circuit device according to claim 1,
The length of the gate electrode of the first MISFET in the gate length direction of the first MISFET is the same as the length of the gate electrode of the second MISFET in the gate length direction of the second MISFET. The semiconductor integrated circuit device according to any one of claims 1 to 6,
2. The semiconductor integrated circuit device according to claim 1, wherein a thickness of the gate insulating film of the first MISFET is the same as a thickness of the gate insulating film of the second MISFET. The semiconductor integrated circuit device according to any one of claims 1 to 7,
The semiconductor integrated circuit device according to claim 1, wherein the first or third active region is a dummy region in which a MISFET is not formed.

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