JP2023087695A - Miniaturized transistor structure with controlled dimensions of source/drain and contact opening and associated fabrication method - Google Patents

Abstract

To provide a transistor structure and a related manufacturing method that can have precisely controlled lengths of source/drain and contact openings to effectively reduce the size of the transistor structure.SOLUTION: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. A contact hole is positioned above the first conductive region. The perimeter of the contact hole is surrounded by the perimeter of the first conductive region.SELECTED DRAWING: Figure 1

Description

The present invention relates to a transistor structure and an associated manufacturing method according to claims 1 and 11.

Design guidelines for shrinking all dimensions of metal oxide semiconductor field effect transistors (MOSFETs) are disclosed in a 1974 paper by R. Dennard, et al. is a major technological requirement that has changed the minimum physical feature size of linear dimensions of silicon wafers from a few micrometers to a few nanometers. The minimum feature size or length, commonly referred to as Lambda(λ), is measured by the minimized printed line-width resolution, also referred to as λ for ease of illustration and comparison. Determined by microminiaturization capability using photolithographic masking techniques with device scaling techniques. However, another difficult-to-control factor limiting device shrinkage is the so-called misalignment tolerance, or delta-alignment tolerance, due to both the inadequacy and inaccuracy of photolithographic equipment. Lambda(Δλ). Furthermore, due to misalignment tolerances, it is difficult to make the distance between the transistor gate edge and the transistor source (or drain) edge smaller than the sum of λ and Δλ. After that, it is necessary to make square contact holes in the drain (or source) for connection between future metal interconnects to the drain (or source) again by using photolithographic masking techniques. , it is difficult to make the minimum size of the square contact hole smaller than λ on both sides of the square contact hole. Furthermore, by including the misalignment tolerance of ensuring square contact holes in the drain, it is difficult to make the length of each edge of the drain (having a rectangular shape) less than the sum of λ and Δλ. be. However, reducing the size of transistors is essential in order to integrate more transistors within the planar area of a silicon wafer, and a necessary and effective method to achieve the above goals is to reduce the size of transistors. Reducing the area occupied by the source and drain respectively, which can also help reduce leakage current and power consumption.

Therefore, how to effectively reduce transistor size in order to integrate more transistors within a planar area of a silicon wafer has become an important issue for transistor designers.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a transistor structure and related fabrication method that can have precisely controlled lengths of source/drain and contact openings to effectively reduce the size of the transistor structure. do.

This is achieved by a transistor structure and an associated manufacturing method according to claims 1 and 11. Dependent claims relate to corresponding further developments and improvements.

As will become more clearly apparent from the detailed description that follows, a transistor structure is claimed. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region and a first isolation region. A semiconductor substrate has a semiconductor surface. The gate structure has a length. A first conductive region is electrically coupled to the channel region. The first isolation region is adjacent to the first conductive region. The length of the first conductive region between the gate structure and the first isolation region is controlled by a single photolithographic process originally configured to define the length of the gate structure.

According to another aspect of the invention, a manufacturing method is for a transistor including a gate structure and a first conductive region. The manufacturing method comprises forming an active region based on a substrate, forming a gate structure and a dummy shield gate structure over the active region, and forming a first isolation region to replace the dummy shield gate structure. forming self-aligned pillars above the active area; removing the self-aligned pillars; and forming a first conductive region between the gate structure and the first isolation region. .

According to another aspect of the invention, prior to removing the self-aligned pillars, the method further includes forming a second isolation region above the first isolation region, the self-aligned pillars comprising: , between the gate structure and the second isolation region.

According to another aspect of the invention, after removing the self-aligned pillars, the method further includes forming a spacer between the gate structure and the first isolation region to define a contact hole; The hole is above the first conductive region.

According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

According to another aspect of the invention, the substrate is a silicon substrate and the self-aligned pillars are intrinsic silicon pillars formed by selective epitaxy growth.

According to another aspect of the invention, a manufacturing method is for a transistor including a gate structure and a first conductive region. A manufacturing method includes forming an active region based on a substrate, forming a gate structure based on the active region, and self-aligned pillars configured to allocate contact holes over the first conductive region. and forming a.

According to another aspect of the invention, the fabrication method further includes forming an isolation region based on the active region prior to forming the self-aligned pillars.

In accordance with another aspect of the invention, a method of manufacturing includes removing self-aligned pillars formed between a gate structure and an isolation region, and forming a spacer between the gate structure and the isolation region to form a contact. defining a hole, the contact hole overlying the first conductive region.

According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

According to another aspect of the invention, a manufacturing method is for a transistor including a gate structure and a first conductive region. A manufacturing method comprises forming an active region based on a substrate, forming a gate structure over the active region, forming a first conductive region next to the gate structure, and forming a first conductive region. defining a contact hole over the active region, wherein defining the contact hole is independent of the photolithography process.

According to another aspect of the invention, a first conductive region is formed between the gate structure and an isolation region extending above the active region.

According to another aspect of the invention, the contact holes are defined by forming spacers covering the sidewalls of the gate structure and the sidewalls of the isolation regions.

According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

According to another aspect of the invention, a manufacturing method is for a transistor including a gate structure and a first conductive region. The manufacturing method comprises performing a first photolithographic process configured to define the width of the gate structure and the length of the active region; and defining the length of the gate structure within the active region. and performing a second photolithography process, the second photolithography process further configured to define the length of the first conductive region.

According to another aspect of the invention, the length of the first conductive region defined by the second photolithographic process is equal to or substantially equal to the minimum feature length.

According to another aspect of the invention, the length of the gate structure defined by the second photolithographic process is equal to or substantially equal to the minimum feature length.

According to another aspect of the invention, the length of the active region defined by the first photolithography process is approximately equal to four times the minimum feature length.

According to another aspect of the invention, a manufacturing method is for a transistor including a gate structure and a first conductive region. A manufacturing method comprises forming an active region based on a substrate, forming a gate structure based on the active region, forming a first conductive region next to the gate structure, and forming a contact hole. forming a contact hole above the first conductive region without using a photolithography process to define the .

According to another aspect of the invention, a first conductive region is formed between the gate structure and the isolation region.

According to another aspect of the invention, the contact holes are defined by forming spacers covering the sidewalls of the gate structure and the sidewalls of the isolation regions.

According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

According to another aspect of the invention, a transistor structure includes a semiconductor substrate, a gate structure, a first conductive region, and a contact hole. A semiconductor substrate has a semiconductor surface. The gate structure has a length. A first conductive region is electrically coupled to the channel region. A contact hole is positioned over the first conductive region. The periphery of the contact hole is surrounded by the periphery of the first conductive region.

According to another aspect of the invention, the perimeter of the first conductive region is shaped like a rectangle.

According to another aspect of the invention, the length of the contact hole is less than the minimum feature length.

According to another aspect of the invention, a transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a contact hole. A semiconductor substrate has a semiconductor surface. A channel region underlies the gate structure. A first conductive region is electrically coupled to the channel region. A contact hole is positioned over the first conductive region. The contact hole length is shorter than the minimum feature length.

According to another aspect of the invention, the horizontal distance between sidewalls of the gate structure and sidewalls of the contact hole remote from the gate structure is less than the minimum feature length.

According to another aspect of the invention, the horizontal distance between sidewalls of the gate structure and sidewalls of the first conductive region remote from the gate structure is approximately equal to the minimum feature length.

In accordance with another aspect of the invention, a transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first isolation region, a first spacer, a second spacer, and a first conductivity. and a first contact hole. A semiconductor substrate has a semiconductor surface. The gate structure has a length. The channel region underlies the semiconductor surface. A first isolation region extends upwardly and downwardly from the semiconductor surface. A first spacer covers the first sidewall of the gate structure and a second spacer covers the sidewall of the first isolation region. A first conductive region is electrically coupled to the channel region and positioned between the gate structure and the first isolation region. A first contact hole is formed between the first spacer and the second spacer.

According to another aspect of the invention, the transistor structure further includes a cap layer and a first metal region. A cap layer covers the gate structure. A first metal region fills the first contact hole and contacts the first conductive region, the first metal region extending from the first conductive region to a predetermined position above the top of the cap layer. Extend upwards.

According to another aspect of the invention, the width of the first metal region is substantially equal to the length of the first contact hole plus the minimum feature length.

According to another aspect of the invention, the transistor structure further includes a second isolation region and a second conductive region. A second isolation region extends upwardly and downwardly from the semiconductor surface. A second conductive region is electrically coupled to the channel region and positioned between the gate structure and the second isolation region.

According to another aspect of the invention, the horizontal distance between the second sidewall of the gate structure and the sidewall of the second isolation region remote from the gate structure is substantially equal to the minimum feature length.

According to another aspect of the invention, the transistor structure further includes a second contact hole, the second contact hole positioned above the second conductive region and having a length of the second contact hole. is shorter than the minimum feature length.

According to another aspect of the invention, the transistor structure further includes a third spacer and a fourth spacer. A third spacer covers the second sidewall of the gate structure. A fourth spacer covers the sidewall of the second isolation region, and a second contact hole is formed between the third spacer and the fourth spacer.

According to another aspect of the invention, a transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. A semiconductor substrate has a semiconductor surface. The gate structure has a length. A first conductive region is electrically coupled to the channel region. The first isolation region is adjacent to the first conductive region. The length of the first conductive region is originally controlled by a single photolithographic process configured to define the length of the gate structure.

According to another aspect of the invention, the length of the first conductive region is equal to or substantially equal to the minimum feature length.

According to another aspect of the invention, a transistor structure includes a semiconductor substrate, a gate structure, a first conductive region, and a first contact hole. A semiconductor substrate has a semiconductor surface. The gate structure has a length. A first conductive region is electrically coupled to the channel region. The periphery of the first contact hole is independent of the photolithography process.

According to another aspect of the invention, the length of the first contact hole is shorter than the minimum feature length.

According to another aspect of the invention, the length of the first conductive region is equal to or substantially equal to the minimum feature length.

According to another aspect of the invention, the first contact hole is positioned over the first conductive region.

The invention is further illustrated by way of example with reference to the accompanying drawings.
FIG. 2 shows a top view of a miniaturized metal oxide semiconductor field effect transistor (mMOSFET) according to an embodiment of the present invention; 4 is a flowchart illustrating a method of manufacturing an mMOSFET according to another embodiment of the invention; FIG. 2B is a diagram showing FIG. 2A; FIG. 2B is a diagram showing FIG. 2A; FIG. 2B is a diagram showing FIG. 2A; FIG. 2B is a diagram showing FIG. 2A; FIG. 2B is a diagram showing FIG. 2A; FIG. 3 shows a top view of the pad nitride layer and STI-oxide 1; It is a figure which shows sectional drawing along the X direction shown in FIG. FIG. 10 shows the photolithographic misalignment tolerance (PMT) for aligning the edge of the gate structure to the edge of the interface between the source of the mMOSFET and the STI-oxide 1; Fig. 3 shows a new structure that can overcome the above-mentioned negative effects of PMT; FIG. 3 shows a spin-on dielectric (SOD) being deposited; FIG. 10 shows a well-designed gate mask layer being deposited and etched; Fig. 2 shows a dummy shield gate (DSG), a nitride layer, a dielectric insulator, and a p-type substrate corresponding to the DSG being removed by an anisotropic etching technique; FIG. 3 shows the gate mask layer being removed, the SOD layer being etched, and the oxide 2 layer being deposited to form STI-Oxide 2; FIG. 4 is a diagram showing the relationship between the positions of real gates (TG) and the positions of dummy shield gates; FIG. 4 is a diagram showing the relationship between the positions of real gates (TG) and the positions of dummy shield gates; FIG. 4 is a diagram showing the relationship between the positions of real gates (TG) and the positions of dummy shield gates; FIG. 4 is a diagram showing the relationship between the positions of real gates (TG) and the positions of dummy shield gates; Oxide 3 layer deposited and etched to form oxide 3 spacers, lightly doped drain (LDD) formed in p-type substrate, deposited and etched to form nitride spacers. FIG. 4 shows the nitride layer being backed and the dielectric insulator being removed; Fig. 2 shows an intrinsic silicon electrode being grown by selective epitaxy (SEG) technique; Fig. 3 shows the CVD-STI-oxide tri-layer being deposited and etched back, the intrinsic silicon electrode being removed, and the source (n+source) and drain (n+drain) of the mMOSFET being formed. FIG. 12 shows oxide spacers being deposited and etched to form contact hole openings; FIG. 1 shows a Metal 1 layer being deposited and etched to form a Metal 1 interconnect; FIG. 3 shows a metal 1 interconnect being formed and a source and drain being formed by using a merged semiconductor junction and metal conductor (MSMC) structure according to another embodiment of the present invention; be. The gate mask layer is removed, then an oxide 2 layer is deposited to fill trenches and other vacancies on the horizontal silicon surface (HSS) to form STI-Oxide 2, followed by chemical-mechanical FIG. 4 shows that the STI-oxide 2 has been planarized by polishing (CMP). 3 layers of oxide deposited and etched to form oxide 3 spacers, a lightly doped drain (LDD) formed in a p-type substrate, a nitride layer to form nitride spacers. is deposited and etched back, and the dielectric insulator being removed. Fig. 2 shows an intrinsic silicon electrode being grown by selective epitaxy (SEG) technique; FIG. 12 shows oxide spacers being deposited and etched to form contact hole openings; FIG. 1 shows a Metal 1 layer being deposited and etched to form a Metal 1 interconnect;

The present invention is the smallest feature size ( We disclose a new method for precisely controlling the linear dimensions of the source (or drain) of a transistor, which can be as small as the minimum feature size, Lambda(λ). Moreover, contact holes with linear dimensions smaller than λ can be achieved in the drain (or source). Thus, the present invention has a minimum feature size from the edge of the gate of the transistor to the edge of the source (or drain) adjacent to the edge of the transistor isolation, and is suitable for sources and drains with linear dimensions less than λ. A new structure of source and drain with contact holes is provided. Thus, the present invention avoids misalignment tolerances caused by photolithographic masking techniques in forming both the source and drain, respectively.

See FIG. FIG. 1 is a diagram illustrating a top view of a miniaturized metal oxide semiconductor field effect transistor (mMOSFET) 100 according to one embodiment of the present invention. As shown in FIG. 1, mMOSFET 100 has (1) gate structure 101 having length G(L) and width G(W), and (2) to the left of gate structure 101, source 103 having (3) to the right of gate structure 101, drain 107 has a length S(L), which is the linear dimension from the edge of gate structure 101 to the edge of isolation region 105, and a width S(W); It has a length D(L), which is the linear dimension from the edge of the structure 101 to the edge of the isolation region 105, and a width D(W); (5) Similarly, a contact hole 109 (contact hole) formed by a At the center of 107, a contact hole 111 formed by a self-aligned technique has opening lengths and widths marked CD(L) and CD(W), respectively.

To form mMOSFET 100, a first photolithography process can be used to define the width G(W) and pseudo length of the active region, and a second photolithography process can be used to define , a length G(L) in the active region can be defined, and a second photolithographic process is further utilized to control the length S(L) between the gate structure 101 and the isolation region 105; In one example, the pseudo-length of the active region defined by the first photolithographic process is approximately four times the minimum feature length λ. In one embodiment, the length G(L) can be equal or substantially equal to the minimum feature length λ. Of course, in another example, the length G(L) can be greater than the minimum feature length λ.

A first feature of the present invention is that both length S(L) and length D(L) can be aligned with the wafer without being subject to unavoidable photolithographic misalignment tolerances (PMT). It can be precisely designed and defined according to the target dimensions that can be produced on the surface.

A second feature of the present invention is that both length S(L) and length D(L) can be made as small as the minimum feature length λ, which is the processing limit defined at the processing node. (eg, minimum length S(L) or minimum length D(L) is 7 nm at the designated 7 nm node, 28 nm at the designated 28 nm node, or 180 nm at the designated 180 nm node, respectively).

A third feature of the present invention is the minimum dimension along the length of mMOSFET 100 (i.e., from the left edge of source 103 to the right edge of drain 107) if length G(L) is designed to be λ. ) can be as small as 3λ (i.e., 1λ for length S(L), 1λ for length D(L), and 1λ for length G(L)). . Second, when not including isolation region 105, mMOSFET 100 can be scaled to only 3λ to achieve linear dimensions along the length of mMOSFET 100. FIG.

A fourth feature of the present invention is that the well-defined lengths S(L) and D(L) of the contact hole 109 are not limited by photolithographic misalignment tolerances. A narrower length CS(L) and a narrower length CD(L) of the contact hole 111 can be produced, respectively. This is because the most critical masking steps that produce contact holes 109, 111 have been eliminated. Moreover, a metal 1 deposited interconnect layer that can be sufficiently filled in the contact holes 109, 111 to form native metal contacts connecting metal 1 to both the source 103 and drain 107, respectively. It can be effectively defined by photolithographic masking techniques to achieve a narrow width of 1 (ie, the sum of the contact hole opening and twice the PMT).

With the above invention, MOSFET structures can be scaled down to minimum device length dimensions (including metal 1 isolation and interconnects) without being magnified by unavoidable photolithographic misalignment tolerances.

See FIGS. 2A-2F, 3, 4, 6-19. FIG. 2A is a flowchart illustrating a method of fabricating an mMOSFET according to one embodiment of the present invention, wherein the method of fabricating an mMOSFET in FIG. can be made. The detailed steps are as follows.
Step 10: Start.
Step 20: Form active regions and trench structures on the substrate 102 .
Step 30: Form mMOSFET true gates and dummy shield gates above the horizontal silicon surface (HSS) of substrate 102 .
Step 40: Replace the dummy shield gates with isolation regions to define the boundaries of the source/drain regions.
Step 50: Form the source and drain regions of the mMOSFET.
Step 60: Form smaller contact holes in the boundaries of the source and drain regions and form metal 1 interconnects that contact the source or drain regions through the contact holes.
Step 70: End.

See FIG. 2B and FIGS. 3 and 4. FIG. Step 20 can include:
Step 202 : A pad oxide layer 302 is formed and a pad nitride layer 304 is deposited over the substrate 102 .
Step 204: An mMOSFET active area is defined and a portion of the silicon material outside the active area is removed to create a trench structure.
Step 206: An oxide 1 layer is deposited in the trench structure and etched back to form shallow trench isolation (STI-oxide 1) 306 below the HSS.
Step 207: Pad oxide layer 302 and pad nitride layer 304 are removed and dielectric insulator 402 is formed over HSS.

See FIG. 2C and FIG. Step 30 may include the following.
Step 208: A gate layer 602 and a nitride layer 604 are deposited over the HSS.
Step 210: Gate layer 602 and nitride layer 604 are etched to form the true gate of the mMOSFET and a dummy shield gate with a desired linear distance to the true gate.

See Figure 2D and Figures 7-10. Step 40 can include:
Step 212: deposit spin-on dielectrics (SOD) 702, then etch back SOD 702;
Step 214: Form well-designed gate mask layer 802 by photolithographic masking techniques.
Step 216: Using an anisotropic etching technique, remove the nitride layer 604 above the dummy shield gate (DSG), the DSG, the portion of the dielectric insulator 402 corresponding to the DSG, and the p-layer corresponding to the DSG. The mold substrate 102 is removed.
Step 218: Remove gate mask layer 802, etch SOD 702, deposit STI-Oxide 2 1002, then etch back.

See Figure 2E and Figures 15-17. Step 50 can include:
Step 220: Deposit and etch back an oxide 3 layer to form oxide 3 spacers 1502, form lightly doped drains (LDDs) 1504 in p-type substrate 102, and a nitride layer. is deposited and etched back to form nitride spacers 1506 and remove dielectric insulator 402 .
Step 222: Growing the intrinsic silicon electrode 1602 using selective epitaxy growth (SEG) technique.
Step 224: Deposit and etch back a CVD-STI-Oxide 3 layer 1702, remove the intrinsic silicon 1602, and form the source region (n+source) 1704 and drain region (n+drain) 1706 of the mMOSFET.

See FIG. 2F and FIGS. 18-19. Step 60 can include:
Step 226: Deposit and etch oxide spacers 1802 to form contact hole openings above the source and drain regions.
Step 228: Deposit and etch Metal 1 layer 1902 to form Metal 1 interconnects.

Part I. Sharp on wafer as well as on drain (GEBEDI) by avoiding photolithographic misalignment tolerance (PMT) by utilizing dummy shield gate (DSG) added on gate level mask from gate edge It achieves to make the designed distance to the boundary edge between the source and the isolation region (GEBESI).

Taking an n-type MOSFET as an example, the substrate 102 is a p-type substrate 102, and a detailed description of the aforementioned fabrication method follows. Beginning at step 20, see FIG. 2B and FIGS. At step 202 , a pad oxide layer 302 is formed over the HSS of p-type substrate 102 and then a pad nitride layer 304 is deposited over pad oxide layer 302 .

At step 204, the active area of the mMOSFET can be defined by photolithographic masking techniques, and the HSS outside the active area is correspondingly exposed. Since the HSS outside the active area pattern is exposed, portions of the silicon material outside the active area can be removed by an anisotropic etching technique to form the trench structure.

In step 206, an Oxide 1 layer is deposited to completely fill the trench structure and then an Oxide 1 layer to form STI-Oxide 1 306 below the HSS, as shown in FIG. The layer is etched back. 4 is a cross-sectional view along the X direction shown in FIG. 3. FIG. Additionally, since FIG. 3 is a top view, FIG. 3 only shows pad nitride layer 304 and STI-oxide 1 306. FIG. Next, in step 207, the pad oxide layer 302 and pad nitride layer 304 over the active area are removed and a dielectric insulator 402 (with high K) is formed over the HSS.

FIG. 5 illustrates typical state-of-the-art design and processing methods for achieving geometric relationships between gate regions and transistor isolation regions (STIs) at smaller dimensions. After a dielectric insulator 402 (with high K) is formed over the HSS, a gate layer 404 (metal gate) is deposited over the dielectric insulator 402 and then nitrided with a well-designed thickness. A nitride layer 406 (nitride cap) is deposited over the gate layer 404 . Next, as shown in FIG. 5, photolithographic masking techniques are utilized to define regions for the gate structure 1, the gate structure 1 is formed in such a way as to achieve a suitable threshold voltage of the mMOSFET. A gate layer 404 and a nitride layer 406 are included to have a suitable metal gate material that delivers the required work function of the MIS (metal insulator to substrate). In addition, STI-Oxide 1 306 is made underneath the HSS, thus forming a tri-gate or fin field effect transistor (FinFET) structure (shown in FIG. 5).

After a first photolithographic process used to define the pseudolength of the active area and a second photolithographic process used to define the length G(L) in the active area, the gate structure The distance from the edge to the edge of the boundary between the mMOSFET source (or mMOSFET drain) and the shallow trench isolation called GEBESI (or GEBEDI) can be defined as shown in FIG.

However, as shown in FIG. 5, align the edge of gate structure 1 with the edge of the boundary between the source of the mMOSFET and the STI-Oxide 1 306 (also on the other side of the drain of the mMOSFET). There is an unavoidable non-ideal factor called photolithographic misalignment tolerance (PMT) during photolithographic masking techniques for photolithography. If the PMT measured in the linear dimension along the X direction is Δλ, then Δλ is the minimum feature size as determined by the photolithographic resolution of the equipment available for the specified processing node. (minimal feature size). For example, a 7 nm process node should have λ equal to 7 nm, and Δλ for PMT should be on the order of 3.5 nm. Therefore, if the desired actual physical length of the mMOSFET source (or mMOSFET drain) is targeted at λ (eg, 7 nm), then the length of the mMOSFET source (or mMOSFET drain) under prior art process methods is The design length must be greater than the sum of λ and Δλ (eg >10.5 nm).

Accordingly, the present invention utilizes a new structure that can eliminate the above-mentioned negative effects of PMT. That is, any dimension of the distance from the edge of the gate structure to the edge of the boundary between the source of the mMOSFET (or the drain of the mMOSFET) and the shallow trench isolation called GEBESI (or GEBEDI) should be achieved; No extra dimension needs to be left for the PMT along the length direction (ie the X direction shown in FIGS. 4 and 5).

In step 208, a gate layer 602 and a nitride layer 604 are deposited after a dielectric insulator 402 (with high K) is formed over the HSS, as shown in FIG. Next, at step 210, the gate layer 602 and nitride layer 604 are etched to form the gate structure (the gate layer 602 may be the gate structure of an mMOSFET). The main difference between the new structure shown in FIG. 6 and the structure shown in FIG. 5 is that when the mMOSFET true gate (TG) is defined by photolithographic masking techniques, the dummy shield gate (DSG) is also defined by the desired TG. , so that the target linear distance (e.g., λ as 7 nm at the 7 nm process node) is between DSG and TG without leaving an extra dimension (i.e., Δλ) for the PMT. It is to exist between Both the DSG and TG designed on the same mask can be formed simultaneously on top of the dielectric insulator 402 covering the active area. In addition, TG2 and TG3 correspond to other mMOSFETs, as shown in FIG.

The following steps describe how to replace the dummy shield gate with an isolation region raised above the HSS. In step 212, deposit SOD 702 and etch back SOD 702 using a chemical mechanical polishing (CMP) technique to make the top of SOD 702 even with the top of nitride layer 604, as shown in FIG. height.

In step 214, as shown in FIG. 8, gate mask layer 802 is deposited and then etched by photolithographic masking techniques to cover TG, TG2, TG3, but not that of GEBESI and GEBEDI. A target is achieved that exposes the DSG with a safe PMT margin Δλ in between such lengths (FIG. 8).

For clarity, the distance between the TG under the gate mask layer 802 and its left DSG (right DSG) in FIG. 8 can also be marked as GEBESI (or GEBEDI). Because after replacing the DSG by the isolation region described in FIGS. 9-10 below, the distance between TG and DSG in FIG. This is because it is the distance from the edge of the TG to the edge of the boundary between the source of the mMOSFET (or the drain of the mMOSFET) and the isolation region.

In step 216, an anisotropic etching technique is used to etch the DSG and the nitride layer 604 corresponding to the DSG, as shown in FIG. etching a portion of the dielectric insulator 402 and then using an anisotropic etching technique to remove the silicon material of the p-type substrate 102 under the HSS to form a trench 902 under the HSS; The depth of trench 902 can be equal to the depth of the bottom of STI-Oxide 1 306 . Therefore, as shown in FIG. 9(a), PMT is avoided in the generation of precisely controlled lengths of GEBESI and GEBEDI, respectively. Since the lengths of GEBESI and GEBEDI are well defined by TG and DSG on the same mask, both the length S(L) of the source region and the length D(L) of the drain region shown in FIG. It is thus clearly defined and created. That is, this single photolithographic masking technique is used not only to define TG and DSG, but also to control the length of GEBESI and GEBEDI. Therefore, the dimensions of length S(L) and length D(L) can be precisely controlled, even to achieve optimally minimized dimensions as small as the minimum feature size λ. can. Since length S(L) and length D(L) can be equal to λ, length S(L) and length D(L) are substantially the length of TG (i.e. gate structure) be equivalent to. In addition, FIG. 9(b) is a top view corresponding to FIG. 9(a).

In step 218, gate mask layer 802 and SOD 702 are removed, as shown in FIG. 10(a). Next, a STI-Oxide 2 layer 1002 is deposited to fill trenches 902 and other vacancies on the HSS, leaving the STI-Oxide 2 layer 1002 equal to the HSS as shown in FIG. 10(a). It can be etched back down to surface level. FIG. 10(b) is a top view corresponding to FIG. 10(a).

The temporarily formed DSG is therefore replaced by the STI-oxide bilayer 1002 to define the boundaries of the source/drain regions. Any existing method of forming a lightly doped drain (LDD), spacers surrounding the TG, source and drain regions can then be used to complete the mMOSFET, where the source and drain regions are , are formed according to precisely controlled GEBESI and GEBEDI, respectively.

Part II. A dummy shield gate (DSG) design principle for variable shape of the active area (on the active area (AA) mask) by adaptive dummy shield gate (DSG) design is used to achieve the target lengths of GEBESI and GEBEDI, respectively.

Since the shape of the isolation region of a transistor and the location of the isolation region from a transistor to an adjacent transistor can be quite different (even from the above embodiments), how to implement an adaptive DSG by extending the principles of the above embodiments. Another structural invention for designing is described below.

FIG. 11 shows a different geometry in which the active areas of adjacent transistors are arranged differently than in FIG. For example, as shown in FIG. 6, the adjacent active areas of adjacent transistors may be separated before true gate (TG), true gate 2 (TG2), true gate 3 (TG3) and dummy shield gate (DSG) are deposited. The DSG is then used to divide the connected active regions into individual precisely targeted distances by the length of the DSG. However, as shown in FIG. 11, the active area on the source (or drain) of the transistor is completely isolated (by isolation region 1102) from any other active area before and after the TG of the transistor is defined. is assumed to be So what is proposed here is how to design both the active region on the source side and (similarly for the drain) an adaptive DSG as described below. For example, if the final length of GEBESI is targeted at λ (or any other target length L(S)), then the length of the active area mask (“AA mask”) corresponding to the GEBESI side is , λ plus Δλ (or length L(S) plus Δλ). Then, on the gate mask, the DSG can have a shape as shown in FIG. That is, the rectangular shape of the DSG has a length equal to λ and a width equal to the width of the active region plus 2Δλ (each side shares 0.5Δλ). The designed distance between TG and DSG on the source side is still only the length of GEBESI, eg, λ.

Results derived from the active area and gate mask levels of FIG. 11 on wafer level are shown in FIG. As shown in FIG. 12, when the TG is defined by photolithographic masking techniques, the DSG is parallel to the TG at a target distance between the DSG and the TG (eg, λ such as 7 nm at a 7 nm process node). made in With nominal processing results (i.e. no significant misalignment induced by photolithographic processing), the DSG partially covers the active area (corresponding to the source) by a distance Δλ, and both the TG and the DSG cover the active area. It is printed on top of the overlying dielectric insulator 402 . Both the TG and DSG have a nitride cap layer on top.

If the PMT causes a shift (e.g., Δλ) of both TG and DSG toward the right side of the active region (Fig. 13), then this previously existing DSG location as described by the previous processing steps in Part I Subsequent processing to remove the DSG to achieve isolation regions (i.e., STI-Oxide 2) precisely in place should result in an STI-Oxide 2 layer with length λ. The two layers result in the physical geometry of the source region with a GEBESI length equal to λ (because the distance between TG and DSG is designed to equal λ). On the other hand, if the PMT causes a shift (eg, Δλ) of both TG and DSG toward the left side of the active region (FIG. 14), then subsequent processing steps to remove the DSG and form the STI-oxide bilayer yields an STI-oxide bilayer with length λ, the source region still has its GEBESI length equal to λ.

Such an adaptive dummy shield gate design with a width that is the sum of the width of the active region and 2Δλ reduces the width of the active region when the PMT causes an undesirable shift along the width of the active region (i.e., up or down). Do not affect geometric dimensions. New designs using adaptive dummy shield gates can always yield STI-oxide 2 with lengths λ and GEBESI that match the designed target (eg narrow as λ). The present invention can certainly be applied to all different shapes of source and drain isolation regions each having their respective individual target lengths.

Part III. Accurately defined source (or drain) regions allow precisely controlled contact hole openings with self-aligned spacers to eliminate contact mask and hole opening process steps.

After disclosing how both GEBESI and GEBEDI can be optimally designed and manufactured to precisely controlled small dimensions (which can be as small as λ), another new invention is GEBESI and GEBEDI (referred to as length CS(L) and length CD(L) as defined respectively in FIG. 1). Two designs and process formulations are described below.

A. Design and process (I)
Continuing with FIG. 10(a), using TG, in step 220 three layers of oxide are deposited, etched back and oxidized as shown in FIG. 15(a). A material 3 spacer 1502 is formed and an oxide 3 spacer 1502 covers the TG. Next, a lightly doped zone is formed in the p-type substrate 102 and a rapid thermal annealing (RTA) is performed on the lightly doped zone to form a lightly doped zone adjacent to the TG. A drain (LDD) 1504 is formed. A nitride layer is then deposited and etched back to form nitride spacers 1506 , which cover oxide 3 spacers 1502 . Dielectric insulator 402 not covered by nitride spacers 1506 and oxide 3 spacers 1502 is removed. In addition, FIG. 15(b) is a top view corresponding to FIG. 15(a).

In step 222, the selective epitaxy (SEG) technique is used to perform nitridation (on top of the TG) by utilizing the exposed HSS as a silicon growth seed, as shown in FIG. 16(a). Intrinsic silicon 1602 is grown only above the exposed HSS to a height as high as the top of the material cap 604 . In addition, FIG. 16(b) is a top view corresponding to FIG. 16(a).

In step 224, a CVD-STI-Oxide 3 layer 1702 is deposited to fill all the holes and planarize by CMP technique to overlie the top of the TG, as shown in FIG. 17(a). A horizontal flat surface is achieved to the top of the nitride cap 604 . The intrinsic silicon 1602 is then removed to expose the HSS corresponding to the source and drain regions surrounded by the CVD-STI-oxide tri layer 1702 and nitride spacers 1506 .

Intrinsic silicon 1602 is only like a self-alignment pillar (SPR) to surround or block areas where contact holes will later be allocated. Such self-aligned pillars are not necessarily limited to silicon materials. Depending on the seed material exposed for selective epitaxy growth, the self-aligned pillars can be of metallic material or other semiconductor material (such as SiC, SiGe, GaN, etc.). Furthermore, the substrate can be a silicon substrate, a SiC substrate, a SiGe substrate, or a GaN substrate.

Any existing method of forming the source region (n+ source) 1704 and the drain region (n+ drain) 1706 of the mMOSFET can be performed to achieve a flat surface for the source region 1704 and the drain region 1706 with HSS; A source region (n+source) 1704 can be a first conductive region and a drain region (n+drain) 1706 can be a second conductive region. In addition, a channel region exists between the lightly doped drain (LDD) 1504 and under the HSS, as shown in FIG. It is electrically coupled to region (n+ drain) 1706 . In addition, as shown in FIG. 17(a), the source region (n+ source) 1704 is formed between the gate structure (ie, TG (gate layer 602)) and the STI-Oxide 2 1002 and CVD Both the STI-Oxide 2 1002 and the CVD-STI-Oxide 3 layer 1702 located between the STI-Oxide 3 layer 1702 and on the left side of the gate structure can be referred to as first isolation regions. The first isolation region can be adjacent to the first conductive region (ie, source region (n+ source) 1704). In addition, as shown in FIG. 17(a), a drain region (n+ drain) 1706 is formed between the gate structure and the STI-Oxide 2 1002 and CVD-STI-Oxide 3 layers 1702 located to the right of the gate structure. Both the STI-Oxide 2 1002 and the CVD-STI-Oxide 3 layer 1702 located in between and on the right side of the gate structure can be referred to as second isolation regions, the second isolation region being the second isolation region. 2 conductive regions (ie, the drain region (n+ drain) 1706). In addition, it is apparent that the first isolation region and the second isolation region extend upward and downward from the HSS, as shown in FIG. 17(a). In addition, FIG. 17(b) is a top view corresponding to FIG. 17(a).

In the contact hole forming step 226, as shown in FIG. 18(a), the CVD-STI-oxide tri-layer 1702 overlying the isolation region and the nitride spacer 1506 surrounding the TG have HSS as the four sidewalls. , creating well-designed oxide spacers 1802 (referred to as oxide spacers for contact holes (Oxide--SCH)) outside the four sidewalls to form the first conductive region (i.e., the source A first contact hole 1804 is formed overlying the region (n+ source) 1704 and also within the boundaries of the source region 1704 . Similarly, a second contact hole 1806 is located above and within the boundary of the second conductive region (ie, drain region (n+ drain) 1706). Therefore, as shown in FIG. 18(a), contact holes 1804 and 1806 are naturally formed in such a self-aligned method that does not use any etching technique to perform contact hole opening, and have a thickness of tOSCH. With proper design of the oxide-SCH having such contact hole opening, such contact hole opening has a length dimension shorter than the length of each of GEBESI and GEBEDI. What is new here is that the contact hole opening is located approximately in the center of the boundary of the source region (or drain region) and the length of the contact hole opening can be designed shorter than λ (because the contact hole This is because the length = length of GEBESI - twice the thickness tOSCH, so for example if the thickness tOSCH = 0.2λ and the length of GEBESI = λ, then the length of the contact hole height = 0.6λ). Therefore, the perimeter of the first contact hole 1804 (and the second contact hole 1806) is independent of the photolithographic masking process because the length of the contact hole is primarily governed by the thickness tOSCH of the oxide-SCH 1802. 18(b), the periphery of the first contact hole 1804 is within the periphery of the first conductive region, and the periphery of the second contact hole 1806 is the second conductive region. is clearly within the perimeter of .

In addition, as shown in FIG. 18(a), since the length of the contact hole opening is shorter than λ, the length of the first contact hole 1804 (also the length of the second contact hole 1806) is less than that of the gate. shorter than the length of the structure (because the length of the gate structure is equal to λ, as shown in FIG. 6). In addition, as shown in FIG. 18(a), the oxide spacer 1802 has a thickness tOSCH and the length of the GEBESI is equal to the length of the gate structure so that it is located on the left side of the gate structure. ) It is clear that the horizontal distance between the first sidewall and the sidewall of the first contact hole 1804 away from the gate structure is less than the length of the gate structure (ie, λ). Additionally, as shown in FIG. 18(a), the horizontal distance between the first sidewall of the gate structure and the sidewall of the first conductive region (ie, source region 1704) remote from the gate structure is the gate structure. It is also clear that it is approximately equal to the length of . Similarly, as shown in FIG. 18(a), the horizontal distance between the second sidewall of the gate structure (located to the right of the gate structure) and the sidewall of the second isolation region away from the gate structure is substantially equal to the length of the gate structure.

In addition, as shown in FIG. 18(a), an oxide spacer 1802 (i.e., first spacer) located to the left of the gate structure and located near the gate structure limits the first sidewall of the gate structure. Overlying oxide spacers 1802 (i.e., second spacers) positioned to the left of and away from the gate structure cover sidewalls of first isolation regions 1702, and first contact holes 1804 are It is formed between the first spacer and the second spacer.

In addition, as shown in FIG. 18(a), oxide spacers 1802 (i.e., third spacers) located on the right side of the gate structure and located near the gate structure an oxide spacer 1802 (i.e., a fourth spacer) covering the second sidewalls of the gate structure and positioned to the right of the gate structure and away from the gate structure covering the sidewalls of the second insulating region; A second contact hole 1806 is formed between the third spacer and the fourth spacer.

In addition, as shown in FIG. 18(b), the first contact hole 1804 is surrounded by the first conductive region (or source region), and the first contact hole 1804 is surrounded by the first conductive region (or source region). is similar to the shape of the perimeter of the first conductive region, and that the perimeter of the first conductive region has a rectangular-like shape. A similar situation applies to the second contact hole 1806 and the second conductive region (or drain region).

According to the present invention, this self-aligned contact hole is achieved by using photolithographic masking processes at such dimensions smaller than λ, as well as by using complex etching process techniques as well as the prior art techniques for creating contact hole openings. It should appear as a contact length shorter than the contact length of the design and process. In addition, the present invention eliminates the most difficult to control and most expensive masks for defining and making metal 1 contacts (such as contact holes for source and drain regions) and drilling contact hole openings. eliminate the subsequent task of In addition, FIG. 18(b) is a top view corresponding to FIG. 18(a).

See FIG. 19 in step 228 of forming metal 1 connections. After depositing the metal 1 layer 1902 to fill the contact holes, the metal 1 layer 1902 can be defined using photolithographic masking techniques. As shown in FIG. 19, the metal 1 layer 1902 must have a width that completely covers the contact hole opening and leaves any unavoidable PMT in precisely controlled dimensions. That is, the width of metal 1 layer 1902 is the length CS(L) of the contact hole opening (above the source region) plus 2Δλ, and equally over the contact hole opening above the drain region: 2Δλ is added to the contact hole length CD(L). If the length of the contact hole opening (which should be under control since the dimensions of the oxide spacers 1802 in the contact hole can be well controlled as described above in the calculations) can be controlled to 0.6λ, then The width of metal 1 layer 1902 can be as small as the sum of the length of the contact hole opening and 2Δλ (Δλ=0.5λ (ie half the length of the gate structure) in one embodiment of the present invention. and the length of the contact hole opening=0.6λ, then the width of the metal 1 layer 1902 should be as narrow as 1.6λ to completely cover the contact hole opening under the unavoidable PMT. That is, the width of the metal 1 layer 1902 is equal to the length of the first contact hole 1804 plus the length of the gate structure to completely cover the contact hole opening under the unavoidable PMT. can be done). According to the present invention, a width of metal 1 layer 1902 as narrow as 1.6λ can be one of the minimum widths of a metal 1 interconnect. Additionally, the minimum space 1904 between the two closest Metal 1 interconnects should be no less than λ. Additionally, as shown in FIG. 19, Metal 1 layer 1902 (ie, first metal region) is filled into first contact hole 1804 and contacts first conductive region (ie, source 1704). However, the first metal region extends upward from the first conductive region to a predetermined position above the top of the nitride layer 604 (ie, the cap layer).

In addition, e.g. By using a merged semiconductor junction and metal conductor (MSMC) structure, as shown in FIG. 20, if there is no adjacent metal 1 interconnect, dummy The width of the CVD-STI-Oxide-3 layer 1702 defined by the shield gate can be made as small as the minimum feature size λ without being limited by the space between adjacent Metal-1 interconnects. Additionally, as shown in FIG. 20, the source region includes a first semiconductor region (N+ heavily doped semiconductor region) 1906 and a first metal-containing region 1908, and the drain region includes a second It includes a semiconductor region (N+ heavily doped semiconductor region) 1910 and a second metal-containing region 1912 , a first oxide guard layer (OGL) 1914 overlying the first metal-containing region 1908 . The second oxide guard layer 1916 (in the recess shown in FIG. 20) covers only the sidewalls of the first metal-containing region 1908 and does not cover the bottom of the first metal-containing region 1908 , covering the sidewalls and bottom of the second metal-containing region 1912 . cover. Thus, first metal-containing region 1908 is coupled to p-type substrate 102 through the bottom of first metal-containing region 1908 .

An important advantage of the present invention is that almost all critical dimensions such as GEBESI, GEBEDI and contact hole opening lengths, as well as metal 1 interconnect widths, can be accurately measured without being affected by PMT uncertainties. controllable, thus ensuring their reproducibility, quality and reliability due to the uniformity of critical dimensions.

B. Design and process (II)
The principles as described above are adopted in the following embodiments, the only difference being how the spacers and contact hole openings are formed. Continuing with FIG. 9(a), as shown in FIG. 21(a), the gate mask layer 802 is removed and then an oxide bilayer is deposited to provide trenches 902 and other voids above the HSS. Fill the holes to form STI-Oxide 2 2102, then planarize STI-Oxide 2 2102 by CMP to nitride the top of STI-Oxide 2 2102 on top of SOD 702 and TG. It should be about as high as the top of the layer 604 . In addition, FIG. 21(b) is a top view corresponding to FIG. 21(a).

Next, as shown in FIG. 22(a), the SOD 702 is removed. An oxide 3 layer is deposited and etched back by an anisotropic etching technique to form an oxide 3 spacer 2202, which covers the TG. Next, a lightly doped zone is formed in the p-type substrate 102 and a rapid thermal annealing is performed on the lightly doped zone to form a lightly doped drain (LDD) 2204 next to the TG. do. A nitride layer is then deposited and etched back to form nitride spacers 2206 , which cover oxide 3 spacers 2202 . And then the dielectric insulator 402 underlying the previously existing SOD 702 is removed. In addition, FIG. 22(b) is a top view corresponding to FIG. 22(a).

Next, as shown in FIG. 23(a), the selective epitaxy growth (SEG) technique is utilized to grow the nitride over the top of the TG by using the exposed HSS regions as silicon growth seeds. Grow intrinsic silicon 2302 only above the exposed HSS to a height as high as the top of cap 604 . A difference from the previous Section A of Part III is that the shape of the SEG intrinsic silicon 2302 can be better controlled. Because two sides of SEG intrinsic silicon 2302 are sandwiched between STI-Oxide 2 2102 and TG, the other two sides of SEG intrinsic silicon 2302 are above the active area cliff edge. , the active area is still covered by the dielectric insulator 402 and above the adjacent STI-oxide 1 . Next, a CVD-STI-Oxide layer 3 layer 2304 (shown in FIG. 23(b)) is deposited to fill all the vacancies and planarized by a CMP technique (on top of the TG). A flat surface leveled to the top of the nitride cap 604 is achieved. In addition, FIG. 23(b) is a top view corresponding to FIG. 23(a).

Further, as shown in FIG. 24(a), two walls of the CVD-STI-Oxide 3 layer 2304, a wall of the nitride spacer 2206 on the STI-Oxide 2 2102, and a wall of the nitride spacer 2206 surrounding the TG. The intrinsic silicon 2302 is removed to expose the HSS in the areas for the source (n+source) 2402 and drain (n+drain) 2404, surrounded by walls. Any existing method of forming the source and drain regions 2402 and 2404 of the mMOSFET can be performed to achieve a planar surface for the source and drain regions 2402 and 2404 in HSS.

As shown in FIG. 24(a), the two walls of the CVD-STI-Oxide 3 layer 2304, the nitride spacers 2206 on the STI-Oxide 2 2102, and the nitride spacers 2206 surrounding the TG are all 4 As one sidewall is taller than HSS, another well-designed four new oxide spacers 2406 (referred to as oxide spacers for contact holes, oxide-SCH) are made to cover the four sidewalls. can be done. Therefore, contact hole openings are naturally formed in such a self-aligned method that does not use any etching techniques to create contact holes, and by proper design of oxide-SCH with a thickness of tOSCH, such contacts The hole opening has a length dimension that is less than the respective lengths of GEBESI and GEBEDI. What is new here is that the contact hole opening is located at the center of both the boundaries of the source and drain regions, respectively, and the length of the contact hole opening can be designed shorter than λ (because the contact hole This is because the length is the length of GEBESI minus twice tOSCH, so if, for example, tOSCH=0.2λ and GEBESI=λ, then the length of the contact hole=0.2λ. 6λ). According to the present invention, this self-aligned contact hole is achieved by using photolithographic masking process steps and creating contact hole openings at such dimensions shorter than λ by using complex etching process techniques. It should appear as a shorter contact length than that of any prior art design and process. In addition, the present invention eliminates the most difficult to control and most expensive mask for defining and making metal 1 contacts and the subsequent task of drilling contact hole openings. In addition, FIG. 24(b) is a top view corresponding to FIG. 24(a).

FIG. 25 shows the result after a Metal 1 layer 2502 is deposited to fill the contact hole openings and then Photolithographic masking techniques can be used to define the Metal 1 layer 2502 . As shown in FIG. 25, Metal 1 layer 2502 must have a width that completely covers the contact hole opening, leaving unavoidable PMTs in precisely controlled dimensions. That is, the width of the metal 1 layer 2502 is the contact hole opening length C−S(L) plus 2Δλ, and equally above the drain is the contact hole opening length CD(L) plus 2Δλ. is added. If the contact hole opening can be controlled to 0.6λ (which can be under control since the dimensions of the oxide spacers 2406 in the contact hole can be well controlled as described above in the calculations), the width of the metal 1 layer 2502 is can be as small as the sum of the length of the contact hole opening and 2Δλ (if Δλ=0.5λ and the length of the contact hole opening=0.6λ, then the width of metal 1 layer 2502 is unavoidably (can be as narrow as 1.6λ to completely cover the contact hole opening under the PMT). According to the present invention, a width of metal 1 layer 1902 as narrow as 1.6λ can be one of the minimum widths of a metal 1 interconnect. The minimum space 2504 between the two closest Metal 1 interconnects should not be less than λ. An important advantage of the present invention is that almost all critical dimensions such as GEBESI, GEBEDI and contact hole opening lengths, as well as metal 1 interconnect widths, can be accurately measured without being affected by PMT uncertainties. control, thus ensuring their reproducibility, quality and reliability due to the uniformity of these critical dimensions.

In summary, by avoiding photolithographic misalignment tolerances, particularly with respect to geometric relationships between contact hole openings between gate and source, gate and drain, metal 1 and source/drain, and metal 1 Some for future integrated circuit designs that derive from the above embodiments of the invention for MOSFET structures by having fundamental improvements in design and processing regarding interconnect widths and self-aligned methods of filling contact holes. There are major improvements in

(1) Accurately define the lengths S(L) and D(L) from the two edges of the gate by removing uncertainties due to photolithographic misalignment tolerances.

(2) Both length S(L) and length D(L) can be designed and fabricated to the minimum feature size λ allowed by photolithographic masking and processing resolution, which allows the size of the source and drain to be Significantly minimized, thus reducing both the area of the MOSFET and the standby and active currents and power, with a corresponding increase in the operating speed of the MOSFET.

(3) Since both the length S(L) and the length D(L) are precisely controlled, the self-aligning technique of the present invention by making each spacer out of four sidewalls surrounding both the source and drain is , self-aligned contact holes (SACH) with controllable shapes and sizes near the center of both the source and drain, respectively, can be precisely made.

(4) The length of the SACH can be designed to a dimension smaller than the minimum feature size λ, eg, as small as 0.6λ or even narrower.

(5) Other width dimensions of such a SACH can be successfully engineered with self-aligned spacers and a well-defined active area width. Because SACH is a state-of-the-art method of defining contact holes by photolithographic masking techniques that utilize chemical film deposition with controllable thickness and with misalignment tolerances and geometries that are difficult to control. The contact hole openings of the present invention can be well designed and defined because they are formed by spacer technology that relies on well-developed techniques that use anisotropic etching techniques instead of Although they may not have a uniform square contact shape, the contact hole has a well-defined rectangular shape and the filling result actually depends on the narrow length dimension of the contact hole). .

(6) eliminates the most challenging and expensive contact fabrication steps and masks;

(7) Change the contact hole design from one square hole or multiple square holes with complete isolation between multiple contact holes to rectangular shape with single contact hole or single contact trench. do. As a result, a dog-bone layout is used to accommodate the dimensional difference between the width of the gate width and the width of the source (or drain), which may have multiple square contact holes. , the width (or length) of the source (or drain) can be approximately the same as the width (or length) of the gate.

(8) Metal 1 interconnects with well-designed thickness can reliably fill all existing contact holes. Because the success of this fill depends on the minimum dimension of the contact hole, which is usually the length of the SACH, a planarization process is added to the tungsten fill (known as the tungsten stud process and the metal 1 damascene process). The state-of-the-art two steps for forming contact studs) can be simplified into one Metal 1 deposition process.

(9) In such an integrated SACH and metal 1 formation process, the gate is buried under the nitride cap and protected by spacers, both of which are flattened to the rest of the area outside the SACH. Creating a plateau, the metal-1 interconnects can be designed with multiple layout methods to create an optimally distributed interconnect network of metal-1.

(10) By combining the above advantages, the new mMOSFET structure has a minimum length dimension of 4λ (i.e. length S(L)=λ, length D(L)=λ, gate length=λ, 1/2λ to account for left separation, 1/2λ to account for right separation) can be made to have very small sizes, with a minimum width dimension of 2λ, i.e. source and drain. The world's smallest single transistor with both contact holes and metal 1 interconnects can be achieved with an area of ^8λ2 .

Of course, depending on design requirements, length G(L), length S(L) or length D(L) can be larger than the minimum feature length λ.

(11) All advantages are limited by being applied to a single MOSFET, but also CMOS (Complementary Metal Oxide Semiconductor) like many optimized functional cells for their area It is also limited by the circuit applied. For example, SRAMs (static random access memories), NAND gates, NOR gates, and random logic gates have been developed by removing uncertainty from photolithographic misalignment tolerances and employing novel self-aligned design and process techniques. Using the design and fabrication principles invented herein to reduce chip area, current, power and speed with the accuracy, reproducibility, uniformity, and robust limits resulting from the invention. can be achieved by

U.S. Patent Application No. 16/991,044

Claims (15)

A method of manufacturing a transistor including a gate structure and a first conductive region, comprising:
forming an active region based on the substrate;
forming the gate structure and a dummy shield gate structure over the active area;
forming a first isolation region that replaces the dummy shield gate structure;
forming self-aligned pillars above the active area;
characterized by removing the self-aligned pillars and forming the first conductive region between the gate structure and the first isolation region;
Production method. Prior to removing the self-aligned pillars, the method includes:
forming a second isolation region above the first isolation region, further characterized in that the self-aligned pillars are between the gate structure and the second isolation region;
The manufacturing method according to claim 1. After removing the self-aligned pillars, the manufacturing method includes:
forming a spacer between the gate structure and the first isolation region to define a contact hole;
further characterized in that the contact hole is above the first conductive region;
The manufacturing method according to claim 1. 4. The manufacturing method of claim 3, further characterized in that the length of the contact hole is shorter than the minimum feature length. 4. The method of claim 3, further characterized in that defining said contact hole is independent of a photolithography process. 2. The fabrication method of claim 1, further characterized in that said substrate is a silicon substrate and said self-aligned pillars are intrinsic silicon pillars formed by selective epitaxy growth. 2. The method of claim 1, further characterized in that the self-aligned pillars are configured to allocate contact holes over the first conductive regions. 2. The method of claim 1, further characterized in that said first isolation region extends upwardly above said active region. performing a first photolithographic process configured to define the width of the gate structure and the length of the active area;
performing a second photolithographic process configured to define a length of the gate structure within the active area;
The second photolithography process is further characterized in that it is further configured to define a length of the first conductive region.
The manufacturing method according to claim 1. 10. The method of manufacturing of claim 9, further characterized in that the length of the active region defined by the first photolithography process is equal to approximately four times the minimum feature length. a semiconductor substrate comprising a semiconductor surface;
a gate structure having a length;
a channel region;
a first conductive region electrically coupled to the channel region;
a contact hole positioned over the first conductive region;
characterized by the perimeter of the contact hole being surrounded by the perimeter of the first conductive region;
transistor structure. 12. The transistor structure of claim 11, further characterized in that a horizontal distance between sidewalls of said gate structure and sidewalls of said contact hole remote from said gate structure is less than said minimum feature length. isolation regions extending upwardly and downwardly from the semiconductor surface;
a first spacer overlying a first sidewall of the gate structure and a second spacer overlying a sidewall of the isolation region;
further characterized in that the contact hole is between the first spacer and the second spacer;
12. The transistor structure of claim 11. a cap layer covering the gate structure;
a first metal region filling the contact hole and in contact with the first conductive region;
further characterized in that the first metal region extends upwardly from the first conductive region to a predetermined position above the top of the cap layer;
12. The transistor structure of claim 11. 12. The transistor structure of claim 11, further characterized in that the contact hole perimeter is photolithographic process independent.

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