JPH0955479A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen connection holes used for bit lines and word lines in alignment allowance in a DRAM having COB structure. SOLUTION: In the manufacture of a DRAM having COB structure, word lines WL and bit lines BL are covered with cap insulating films 7a and 11a and side walls 7b and 11b, and connection holes 9a, 9b1 , and 9b2 are bored in a self-aligned manner as prescribed by them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a DRAM (Dynamic Random Acce
The present invention relates to a technique effectively applied to a method for manufacturing a semiconductor integrated circuit device having an ss memory).

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory that represents a large-capacity memory. The memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell must be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the storage capacitance of an information storage capacitor (capacitor) in a memory cell of a DRAM is DR
It is known that a certain amount is required regardless of the generation from the viewpoint of consideration of the operation margin of the AM, the soft error, and the like, and it is generally not possible to reduce proportionally.

Therefore, the development of a capacitor structure that can secure a necessary storage capacity within a limited small occupied area is underway. As such a capacitor structure, electrodes made of polysilicon laminated in two layers are being developed. A three-dimensional capacitor structure such as a so-called stacked capacitor having a capacitance insulating film interposed therebetween is adopted.

In a stacked capacitor, a capacitor electrode is formed of a selection MOS.FET (Metal Oxide Semi) of a memory cell.
In general, a structure that is placed in the upper layer of the conductor field effect transistor) can secure a large storage capacity with a small occupied area, and since the diffusion layer is not required in the capacitor configuration part, the occurrence rate of soft error is also large. It has the characteristics that it can be reduced and the required storage capacity is small.

There are various types of such stacked capacitor structures. Among them, a so-called Capacitor Over Bitline (hereinafter referred to as CO) in which the capacitor is arranged above the bit line.
The structure (abbreviated as B) is characterized in that the underlying step of the storage electrode (storage node) is flattened by the bit line, so that the process load at the time of forming the capacitor is reduced. Further, since the bit line is shielded by the capacitor, a high signal-to-noise (S / N) ratio can be obtained. A DRAM having a memory cell having a COB structure is described in Japanese Patent Application Laid-Open No. 7-122654.

[0007]

However, the present inventor has found that the DRAM having such a COB structure has the following problems.

That is, the bit line connection hole and the capacitor connection hole require alignment margins for the word line and the bit line, respectively, in consideration of the positional deviation when forming them. The problem is that the cell size of the memory cell cannot be made sufficiently small.

The problem of such alignment margin has been dependent on the progress of alignment precision technology of photolithography.
In order to achieve high integration, it is necessary to have sophisticated alignment technology and process control, and it is necessary to introduce sophisticated and expensive photolithography technology such as phase shift technology to increase the resolution of the transfer pattern. Moreover, there is a problem that it takes time and labor to newly introduce these techniques into the manufacturing process of the semiconductor integrated circuit device, and the development period of the semiconductor integrated circuit device becomes long.

Further, as a phase shift technique for drilling a connection hole, there are, for example, an edge emphasis type and a halftone type. In the edge-enhanced type, an auxiliary light transmission area (hereinafter, referred to as an auxiliary pattern) that is not actually transferred is arranged around a light transmission area (hereinafter, referred to as a main pattern) for a transfer pattern, so This is a technique of enhancing the edge in the image of the light transmitted through the mask by producing a phase difference in each light transmitted through the mask. The halftone type is a technique in which an opaque portion on the mask is made slightly transmissive to cause a phase difference in the light passing through the mask and enhance the edge of the image of the light.

In the case of the edge-emphasized type, however, it becomes difficult to design and appropriately arrange the auxiliary pattern for obtaining a sufficient exposure intensity ratio as the diameter of the connection hole and the adjacent space are reduced. In particular, in the memory cell area of the DRAM, the connection holes are arranged at a high density, and the adjoining spaces between them tend to be reduced more and more. Therefore, it is difficult to arrange the above auxiliary patterns, and there is a limit to miniaturization. is there. Further, in the case of the halftone type, it is necessary to form a pattern on the mask that is larger than the opening diameter of the connection hole that is actually opened, so that the arrangement of adjacent connection holes is limited and there is a limit to miniaturization. .

An object of the present invention is to have a DR having a COB structure.
It is an object of the present invention to provide a technique capable of reducing the alignment margin of the bit line connecting hole and the capacitor connecting hole in the AM.

Another object of the present invention is to provide a technique capable of reducing the memory cell size in a DRAM having a COB structure.

Another object of the present invention is to provide a COB without introducing advanced lithography technology or advanced alignment technology.
It is an object of the present invention to provide a technique capable of reducing the memory cell size in a DRAM having a structure.

Another object of the present invention is to provide a technique capable of shortening the development period of a semiconductor integrated circuit device including a DRAM having a COB structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention is a memory cell selection MISFE formed on a semiconductor substrate.
A word line forming a gate electrode of T and a bit line extending in a layer above the word line so as to extend orthogonal to the extending direction of the word line are provided, and information is stored in the layer above the bit line. With a capacitor-over-bitline structure memory cell provided with a capacitor for
A method of manufacturing a semiconductor integrated circuit device having M, comprising the following steps.

(A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride.

(B) A first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride is formed on the semiconductor substrate, and the first cap insulating film and the first sidewall insulating film are formed. Step of coating.

(C) On the upper surface of the first insulating film, the first
A step of depositing a first mask film made of a material having an etching rate slower than that of the insulating film, and then opening a first capacitor connection hole formation region located between word lines adjacent to each other in the first mask film.

(D) A first capacitor connection hole such that one semiconductor region of the memory cell selection MISFET is exposed by etching away the first insulating film portion exposed from the opening region of the first mask film. Is perforated in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner.

(E) The first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back to form the first conductor film.
A step of embedding the first conductor film in the capacitor connection hole.

(F) After the step of embedding the first conductor film,
Depositing a second insulating film on the first insulating film.

(G) After depositing a second mask film made of a material having a slower etching rate than the first insulating film and the second insulating film on the second insulating film, the second mask film A step of forming a bit line connection hole forming region located between word lines adjacent to each other.

(H) A bit line such that the other semiconductor region of the memory cell selection MISFET is exposed by etching away the second insulating film and the first insulating film exposed from the opening region of the second mask film. A step of forming a connection hole in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner.

(I) After depositing a second conductor film on the semiconductor substrate after the formation of the bit line connection hole, the second
Forming the bit line by patterning a conductor film.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the first cap insulating film and the first sidewall insulating film are formed on the upper surface and the side surface of the gate electrode of the MISFET for the peripheral circuit. It is formed simultaneously with the film and the sidewall insulating film.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selection MIS formed on a semiconductor substrate is used.
A word line forming a gate electrode of an FET, and a bit line extending above the word line so as to extend perpendicularly to the extending direction of the word line are provided, and information is stored above the bit line. D having a capacitor-over-bitline structure memory cell having a capacitor for
A method of manufacturing a semiconductor integrated circuit device having a RAM, including the following steps.

(A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride.

(B) A first insulating film having a flat upper surface made of a material having an etching rate faster than that of silicon nitride is formed on the semiconductor substrate, and the first cap insulating film and the first sidewall insulating film are formed. Step of coating.

(C) On the upper surface of the first insulating film, the first
A step of depositing a first mask film made of a material having an etching rate slower than that of the insulating film, and then opening a first capacitor connection hole formation region located between word lines adjacent to each other in the first mask film.

(D) A first capacitor connection hole such that one semiconductor region of the memory cell selection MISFET is exposed by etching away the first insulating film portion exposed from the opening region of the first mask film. Is perforated in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner.

(E) The first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back to form the first conductor film.
A step of embedding the first conductor film in the capacitor connection hole.

(F) After the step of embedding the first conductor film,
Depositing a second insulating film on the first insulating film.

(G) After depositing a second mask film made of a material having a slower etching rate than the first insulating film and the second insulating film on the second insulating film, then A step of forming a bit line connection hole forming region located between word lines adjacent to each other.

(H) A bit line such that the other semiconductor region of the memory cell selection MISFET is exposed by etching away the second insulating film and the first insulating film exposed from the opening region of the second mask film. A step of forming a connection hole in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner.

(I) After the second conductor film is deposited on the semiconductor substrate after the formation of the bit line connection hole, the second
Forming the bit line by patterning a conductor film.

(J) A step of covering the upper surface and the side surface of the bit line with a second cap insulating film and a second side wall insulating film made of silicon nitride.

(K) A third insulating film having a flat upper surface made of a material having an etching rate faster than that of silicon nitride is deposited on the second insulating film to deposit the second cap insulating film and the second sidewall insulating film. The step of coating.

(L) On the upper surface of the third insulating film, the third
A step of depositing a third mask film made of a material having an etching rate slower than that of the insulating film and then opening a first capacitor connection hole forming region in the third mask film.

(M) The first conductive film embedded in the first capacitor connection hole by etching away the third insulating film and the second insulating film portion exposed from the opening region of the third mask film. A step of forming a second capacitor connection hole that exposes the second capacitor in a state of being defined in a self-aligned manner by the second cap insulating film and the second sidewall insulating film.

(N) A third conductor film is deposited on the semiconductor substrate after the formation of the second capacitor connection hole, and then the third conductor film is patterned to form the information storage capacitor. Step of forming a part of the first electrode.

[0044]

According to the present invention described above, the capacitor connection hole and the bit line connection hole can be formed in a self-aligned manner. Further, since the underlying insulating film is flattened when forming the connection holes, it is possible to sufficiently secure the focus margin in the photolithography technique when transferring the connection hole pattern.

As a result, it is possible to reduce the alignment margin of the connection holes, so that it is possible to reduce the memory cell size without introducing advanced lithography technology or advanced alignment technology.

Further, since the memory cell size can be reduced by the conventional technology without introducing the advanced lithography technology or the advanced alignment technology, the new technology introduction work becomes unnecessary and the semiconductor integrated circuit device having the DRAM can be manufactured. It is possible to shorten the development period.

Further, since the alignment accuracy of the capacitor connecting hole and the bit line connecting hole can be improved, the connection failure in these connecting holes can be reduced, and the semiconductor integrated circuit device having the DRAM can be manufactured. It is possible to improve yield and reliability.

Further, according to the present invention, the first cap insulating film and the first sidewall insulating film are formed simultaneously with the step of forming the cap insulating film and the sidewall insulating film for covering the gate electrode of the MISFET which constitutes the peripheral circuit of the DRAM. By doing so, the manufacturing process is not significantly increased.

[0049]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view of a main part of a memory cell region of a semiconductor integrated circuit device according to an embodiment of the present invention.
2 is a sectional view of a main part of a peripheral circuit region of the semiconductor integrated circuit device of FIG. 1, FIG. 3 is a plan view of a main part of a memory cell region of the semiconductor integrated circuit device of FIG. 1, and FIG. 4 is a semiconductor integrated circuit device of FIG. Plan views of a main part of the memory cell region of FIGS.
3 to 32 are cross-sectional views of the main part of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process, and FIG. 22 is a plan view of the main part of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process of FIG.

The semiconductor integrated circuit device of the first embodiment is, for example, a 64 Mbit DRAM. However, the present invention provides 6
The present invention is not limited to the application to the 4M bit DRAM and various applications are possible.

This DRAM will be described with reference to FIGS. Note that FIG. 1 shows a cross-sectional view taken along the line II of FIG.

The semiconductor substrate 1s constituting the DRAM is made of, for example, p ⁻ -type silicon (Si) single crystal, and the field insulating film 2 for element isolation made of, for example, silicon dioxide (SiO ₂ ) is formed on the semiconductor substrate 1s. Has been done.

Semiconductor substrate 1s in memory cell region M
A p-well 3p is formed on the upper part of the. Boron, which is a p-type impurity, is introduced into the p-well 3p. The memory cell M is formed on the p-well 3p.
C is formed. The memory cell MC is composed of one memory cell selection MOS.FET (hereinafter referred to as selection MOS) 4 and one capacitor 5. The size of this one memory cell MC is, for example, 1.15 μm
It is about ² .

The selection MOS 4 has a pair of semiconductor regions 4a and 4b formed on the semiconductor substrate 1s so as to be spaced apart from each other.
And a gate insulating film 4c formed on the semiconductor substrate 1s.
And a gate electrode 4d formed on the gate insulating film 4c.

The semiconductor regions 4a and 4b are regions for forming the source region and the drain region of the selection MOS 4, and the semiconductor regions 4a and 4b are doped with, for example, n-type impurity phosphorus or arsenic (As). ing. In addition,
A channel region of the selection MOS 4 is formed between the semiconductor regions 4a and 4b.

One active region composed of the semiconductor regions 4a and 4b and two channel regions is defined by the field insulating film 2 in plan view.
The semiconductor region 4a is formed in a symmetrical shape with respect to the center (see FIG. 3).

The channel region below the gate electrode 4d of the selection MOS 4 has an upper side and a lower side that are refracted when viewed in a plane, but since the refraction angle is designed to be 135 ° or more, The same extension of the bird's beak and the shape of the end portion of the field insulating film 2 are obtained on the upper side and the lower side of the channel region.

Thus, according to the first embodiment, the selection M
Since it becomes difficult for a step to be formed on the surface of the channel region of OS4, it is possible to introduce impurities to the entire surface of the channel region by ion implantation to approximately the same depth. Therefore, it is possible to obtain a channel region having a uniform impurity concentration distribution, and thus it is possible to prevent the threshold voltage of the selection MOS 4 from varying.

The gate insulating film 4c is made of SiO ₂ , for example. The gate electrode 4d are, for example on the conductor film 4d1 made of low-resistance poly-silicon film, is formed by depositing a conductor film 4d2 made of, for example, tungsten silicide (WSi _2). The conductor film 4d2 is intended to reduce the resistance of the gate electrode 4d. However, the gate electrode 4d
May be formed of a single film of low resistance polysilicon, or may be a predetermined metal such as tungsten.

The gate electrode 4d is also a part of the word line WL. The word line WL extends in a direction orthogonal to the direction in which the active region extends, and the selection M
A certain width (L) necessary to obtain the threshold voltage of OS4
g) (see FIG. 3). The interval between the adjacent word lines WL is, for example, about 0.67 μm.

A word line WL having a size of Lg
The region of (1) is wider than the width of the active region by at least the amount corresponding to the mask alignment margin in the manufacturing process.

The upper surface and the side surface of the gate electrode 4d (word line WL) are covered with a cap insulating film (first cap insulating film) 7a and a sidewall (first sidewall insulating film) 7b via insulating films 6a and 6b. Has been done. These cap insulating film 7a and sidewall 7b are
It is covered with the interlayer insulating films 8a to 8c. Then, a connection hole 9a1 is formed in the interlayer insulating films 8a to 8c so that the semiconductor region 4a in the upper layer portion of the semiconductor substrate 1s is exposed, and in the interlayer insulating films 8a and 8b, a semiconductor in the upper layer portion of the semiconductor substrate 1s is formed. Connection hole 9b1 so that the region 4b is exposed
Are formed. The diameter of these connection holes 9a1 and 9b1 is, for example, about 0.36 μm.

The insulating films 6a and 6b are made of, for example, SiO ₂ . In the first embodiment, the cap insulating film 7
The a and the sidewall 7b are made of, for example, silicon nitride.

The insulating films 6a and 6b have the following two functions, for example. That is, the first is the cap insulating film 7
It has a function of preventing the inside of the film forming processing apparatus from being contaminated with the constituent metal element of the conductor film 4d2 when the a and the side wall 7b are formed. The second function is to reduce stress applied to the cap insulating film 7a and the sidewalls 7b due to the difference in thermal expansion during heat treatment or the like in the manufacturing process of the semiconductor integrated circuit device.

The cap insulating film 7a and the sidewalls 7b function as etching stoppers when forming the connection holes 9a1 and 9b1 in the interlayer insulating films 8a and 8b, and form the connection holes 9a1 and 9b1 between the word lines WL adjacent to each other. It functions as a film for self-aligned formation. That is, the cap insulating film 7a and the sidewall 7b are
The dimensions of the connection holes 9a1 and 9b1 in the width direction of the word line WL are defined.

Therefore, for example, even if the connection holes 9a1 and 9b1 are slightly displaced in the width direction of the word line WL (left and right direction in FIG. 3), the cap insulating film 7a and the sidewalls 7b are formed.
Function as an etching stopper, so that the word line WL is not partially exposed from the connection holes 9a1 and 9b1. Therefore, the alignment margin of the connection holes 9a1 and 9b1 can be reduced.

The connection holes 9a1 and 9b1 are connected to the word line WL.
Even if it is deviated in the longitudinal direction (vertical direction in FIG. 3), since the interlayer insulating films 8a and 8b have a certain thickness here, the upper surface of the semiconductor substrate 1s should be exposed from the connection holes 9a1 and 9b1. Nor.

The interlayer insulating film 8a is made of, for example, SiO ₂ , and the interlayer insulating film 8b is made of, for example, BPSG (Boro Phospho).
Silicate Glass). The interlayer insulating film 8a has a function of preventing boron or phosphorus in the upper interlayer insulating film 8b from diffusing into the lower semiconductor substrate 1s.

Further, the interlayer insulating film 8b has a function of flattening the base of the wiring layer. As a result, a margin for photolithography can be secured and the connection hole 9a can be secured.
It is possible to improve the pattern transfer accuracy of 1,9b1 and wiring.

An interlayer insulating film 8c made of, for example, SiO ₂ is formed on the interlayer insulating film 8b. In the interlayer insulating film 8c, when a part of the cap insulating film 7a is exposed from the interlayer insulating film 8b in a bit line forming step described later or the like, the exposed portion is etched and the word line WL is formed.
It is a film to prevent it because it may be exposed. Therefore, when such a problem does not occur, it may not be provided.

A bit line BL is formed on the interlayer insulating film 8c. The bit line BL is, for example, a conductor film (second conductor film) BL made of, for example, WSi ₂ on a conductor film (second conductor film) BL1 made of low resistance polysilicon.
2 is deposited and is electrically connected to the semiconductor region 4a through the connection hole 9a1. The interval between the adjacent bit lines BL is, for example, about 0.86 μm.

Between the conductor film BL1 and the interlayer insulating film 8c, there is left a mask film (second mask film) 10b which serves as an etching mask when forming the connection hole 9a1.
The mask film 10b is a film for increasing the etching selection ratio when the connection hole 9a1 is formed, is made of, for example, low resistance polysilicon, and is also a part of the bit line BL.

The bit line BL is the word line W described above.
It is arranged so as to be orthogonal to L (see FIG. 4). The center line of the bit line BL does not necessarily have to coincide with the center of the connection hole 9a1 for the bit line, but in this case, the bit line BL has a protrusion for completely enclosing the connection hole 9b1, 9b2 for the capacitor. I need.

When the protrusion is formed on the bit line BL, a short circuit failure may occur between the adjacent bit line BL and the protrusion. Therefore, the bit line BL portion adjacent to the protrusion is separated from the protrusion. It's a little bent away.

The upper surface and the side surface of the bit line BL are cap insulating film (second cap insulating film) 11a and sidewalls (second sidewall insulating film) 1 with insulating films 6c and 6d interposed therebetween.
1b. This cap insulating film 11
The a and the sidewall 11b function as an etching stopper when forming the connection hole 9b2 in the interlayer insulating film 8c and the like, and the connection hole 9b2 is formed between the bit lines BL adjacent to each other.
Functioning as a film for forming in a self-aligned manner.
That is, the cap insulating film 11a and the sidewalls 11b are formed of the connection holes 9b1 in the width direction of the bit line BL.
The size of 9b2 is specified.

Therefore, for example, even if the connection holes 9b1 and 9b2 are slightly deviated in the width direction of the bit line BL (vertical direction in FIG. 4), the cap insulating film 11a and the sidewall 11b function as an etching stopper. The holes 9b1 and 9b2 do not excessively enter the element isolation region. Therefore, the alignment margin of the connection holes 9b1 and 9b2 can be reduced.

Further, the cap insulating film 11a and the sidewalls 11b are covered with the insulating film 12. The insulating film 12 is a film that functions as an etching stopper when removing the underlying insulating film after forming the capacitor 5, and is made of, for example, silicon nitride.

The insulating film 12 has a thickness of, for example, 100 to
It is set at 500 °, preferably about 250 °.
If the thickness is larger than this, hydrogen is trapped by the silicon nitride film during the final hydrogen annealing treatment for terminating dangling bonds, and a sufficient termination effect cannot be obtained.

A cylindrical capacitor 5, for example, is formed on the upper layer of the bit line BL. That is, the DRAM of the first embodiment has a COB structure. The capacitor 5 is configured such that the surface of the first electrode (third conductor film) 5a is covered with the second electrode 5c via the capacitor insulating film 5b. That is, in the first embodiment, the capacitance portion is formed on the lower surface side of the first electrode 5a and the side surface of the shaft portion of the capacitor 5, so that a large capacitance can be secured.

The first electrode 5a is made of, for example, low resistance polysilicon, and is electrically connected to one semiconductor region 4b of the selection MOS 4 through a conductor film (first conductor film) 13 embedded in the connection hole 9b1. There is. The conductor film 13 is made of, for example, low resistance polysilicon.

The capacitor insulating film 5b is formed, for example, by depositing a SiO ₂ film on a silicon nitride film. The second electrode 5c is made of, for example, low resistance polysilicon and is electrically connected to a predetermined wiring.

The mask film (third mask film) 10c below the first electrode 5a of the capacitor 5 is a film used as a mask when the connection hole 9b2 is formed. The mask film 10c is made of, for example, low resistance polysilicon and is a part of the first electrode 5a of the capacitor 5.

On the other hand, a p well 3p and an n well 3n are formed above the semiconductor substrate 1s in the peripheral circuit region P. Boron, which is a p-type impurity, is introduced into the p-well 3p. In addition, for example, phosphorus or As, which is an n-type impurity, is introduced into the n-well 3n. Then, for example, an nMOS 14 and a pMOS 15 are formed on the p well 3p and the n well 3n.

These nMOS 14 and pMOS 15
Thereby, peripheral circuits such as a DRAM sense amplifier circuit, a column decoder circuit, a column driver circuit, a row decoder circuit, a row driver circuit, an I / O selector circuit, a data input buffer circuit, a data output buffer circuit, and a power supply circuit are formed. Have been.

The nMOS 14 is a pair of semiconductor regions 14a, 14a formed on the p well 3p and spaced apart from each other.
b and the gate insulating film 14 formed on the semiconductor substrate 1s
c and the gate electrode 1 formed on the gate insulating film 14c
4d and.

The semiconductor regions 14a and 14b are the nMOS1
4 is a region for forming a source region and a drain region, and n-type impurities such as phosphorus or As are introduced into the semiconductor regions 14a and 14b. In addition,
A channel region of the nMOS 14 is formed between the semiconductor regions 14a and 14b.

The gate insulating film 14c is made of SiO ₂ , for example. The gate electrode 14d, the conductor film 14d2 made of WSi ₂ is formed by depositing for example on the conductor film 14d1 made of low-resistance poly-silicon. However, the gate electrode 14d may be formed of, for example, a single film of low resistance polysilicon or may be formed of metal.

On the upper surface and the side surface of the gate electrode 14d,
A cap insulating film 7a and a sidewall 7b are formed via the insulating films 6a and 6b. Insulating film 6a, 6b
Has the same function as the insulating films 6a and 6b in the memory cell region M described above, and is made of, for example, SiO ₂ .

The cap insulating film 7a and the sidewalls 7b are made of, for example, silicon nitride. However,
The side wall 7b in this case is mainly LDD (Li
ghtly Doped Drain) It is a film for constructing the structure.

The pMOS 15 is a pair of semiconductor regions 15a, 15 formed on the n-well 3n so as to be separated from each other.
b and the gate insulating film 15 formed on the semiconductor substrate 1s
c and the gate electrode 1 formed on the gate insulating film 15c
5d.

The semiconductor regions 15a and 15b are pMOS1
5 is a region for forming a source region and a drain region of No. 5, and p-type impurity boron, for example, is introduced into the semiconductor regions 15a and 15b. A channel region of the pMOS 15 is formed between the semiconductor regions 15a and 15b.

The gate insulating film 15c is made of SiO ₂ , for example. The gate electrode 15d is formed by depositing a conductor film 15d2 made of WSi ₂ on a conductor film 15d1 made of, for example, low resistance polysilicon. However, the gate electrode 15d may be formed of, for example, a single film of low resistance polysilicon, or may be formed of metal.

On the upper surface and the side surface of the gate electrode 15d,
A cap insulating film 7a and a sidewall 7b are formed via the insulating films 6a and 6b. Insulating film 6a, 6b
Has the same function as the insulating films 6a and 6b in the memory cell region M described above, and is made of, for example, SiO ₂ .

The cap insulating film 7a and the sidewall 7b are made of, for example, silicon nitride. However,
The sidewall 7b in this case is a film mainly for forming an LDD structure.

The nMOS 14 and pMOS 15 are
It is covered with the above-mentioned interlayer insulating films 8a to 8c, and the above-mentioned insulating film 12 is deposited on the interlayer insulating film 8c. Further, such a memory cell region M
Further, in the peripheral circuit region P, the interlayer insulating film 8d is formed on the insulating film 12, and the second electrode 5b of the capacitor 5 is covered thereby.

The interlayer insulating film 8d is formed on the insulating film 8d1 made of, for example, SiO _{2 on the} insulating film 8d made of, for example, BPSG.
It is formed by depositing d2. The insulating film 8d1 has a function of preventing boron or phosphorus in the insulating film 8d2, which is an upper layer thereof, from diffusing to the second electrode 5c side of the capacitor 5 or the like.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 5, after the surface of the semiconductor substrate 1s made of p ^{− type} Si single crystal is subjected to thermal oxidation treatment, an insulating film 16 made of SiO ₂ having a thickness of, for example, 135 Å is formed. , On its upper surface, for example, thickness 1400Å
An insulating film 17 made of silicon nitride is deposited by the CVD method or the like.

Subsequently, of the insulating film 17, the portion located in the element isolation region is removed by the photolithography technique and the dry etching technique, and then the selective insulating process is performed by using the patterned insulating film 17 as a mask. As shown in FIG. 6, a field insulating film 2 for element isolation is formed on the main surface of the semiconductor substrate 1s. The field insulating film 2 is made of, for example, SiO ₂ and has a film thickness of about 4000Å.

After removing the insulating film 17 with a hot phosphoric acid solution or the like, the photoresist is used as a mask to ion-implant boron of p-type impurity, for example, the semiconductor substrate 1s.
After removing the photoresist, the semiconductor substrate 1s is subjected to thermal diffusion treatment to form the p well 3p.

Further, using the photoresist as a mask, for example, phosphorus of an n-type impurity is ion-implanted to form the semiconductor substrate 1.
n is introduced into the semiconductor substrate 1s at a predetermined position, the photoresist is removed, and then the semiconductor substrate 1s is subjected to thermal diffusion treatment.
Well 3n is formed.

Next, the insulating film 1 on the surface of the semiconductor substrate 1s
After removing 6 by etching with a hydrofluoric acid solution, an insulating film (not shown) made of, for example, SiO ₂ and having a thickness of about 100 Å is formed on the surface of the semiconductor substrate 1s.

After that, by optimizing the impurity concentration in the channel region, predetermined impurities are ion-implanted into the main surface of the active region in order to obtain the threshold voltage of each MOS.

Next, as shown in FIG. 7, the semiconductor substrate 1
After the insulating film on the surface of s is removed by etching with a hydrofluoric acid solution, the gate insulating film 4c of the selective MOS and the gate insulating film 1 of the MOS forming the peripheral circuit are formed on the surface of the semiconductor substrate 1s.
4c and 15c are formed. The gate insulating film 4c is formed by, for example, a thermal oxidation method and has a film thickness of about 90Å.

Then, as shown in FIG.
To the top surface, sequentially depositing a conductor film 18d2 made of a conductor film 18d1 and WSi ₂ made of, for example, low-resistance poly-silicon to which phosphorus is introduced. The conductor films 18d1 and 18d2
Are formed by, for example, a CVD method, and their film thicknesses are, for example, 700Å and 1500Å, respectively.

After that, an insulating film 6a made of, for example, SiO ₂ and a cap insulating film 7a made of silicon nitride are sequentially deposited on the upper conductive film 18d ₂ . This insulating film 6
The a and the cap insulating film 7a are formed by, for example, the CVD method.

The insulating film 6a is for preventing the inside of the film forming apparatus from being contaminated with the constituent metal of the conductor film 18d2 when forming the cap insulating film 7a, and for relaxing the stress applied to the cap insulating film 7a during heat treatment or the like. The film has a thickness of, for example, about 100 to 500Å.

The cap insulating film 7a is a film that functions as an etching stopper in the connection hole forming step described later, and its thickness is, for example, about 2000 Å.

Then, as shown in FIG. 9, using the photoresist as a mask, the cap insulating film 7a, the insulating film 6a and the conductor films 18d2,1 exposed from the photoresist are masked.
The gate electrodes 4d (word lines WL), 14d and 15d are formed in the memory cell region M and the peripheral circuit region P by sequentially removing 8d1 by etching.

Then, after removing the above-mentioned photoresist, the semiconductor substrate 1s is subjected to thermal oxidation treatment,
On the side surfaces of the gate electrodes 4d, 14d, 15d, for example, Si
A thin insulating film 6b made of O ₂ is formed.

After that, as shown in FIG. 10, ion implantation of phosphorus of an n-type impurity and boron of a p-type impurity into the nMOS formation region and the pMOS formation region of the peripheral circuit region P using the gate electrodes 14d and 15d as masks is performed. The low impurity concentration semiconductor regions 14a1, 14b1,
15a1 and 15b1 are formed.

Next, phosphorus of an n-type impurity is ion-implanted into the selection MOS formation region of the memory cell region M by using the gate electrode 4d as a mask, and the n-type impurity is expanded and diffused to thereby form a source region and a drain region of the selection MOS 4. The semiconductor regions 4a and 4b forming the above are formed. Bit lines and capacitors are connected to the semiconductor regions 4a and 4b, respectively.

Subsequently, after depositing an insulating film made of, for example, silicon nitride on the semiconductor substrate 1s by the CVD method,
The insulating film is etched back by an anisotropic dry etching method such as RIE (Reactive Ion Etching) to form a sidewall 7b on the side surface of the gate electrode 4d of the selection MOS 4.

After forming such sidewalls 7b, arsenic (As) is ion-implanted into the main surface of the p-well 3p at a concentration higher than that of phosphorus, which is the n-type impurity described above. The source region and the drain region may have an LDD (Lightly Doped Drain) structure.

Thereafter, the nMOS forming region and the pMOS forming region of the peripheral circuit region P are ion-implanted with phosphorus of an n-type impurity and boron of a p-type impurity using the sidewalls 7b as a mask, respectively, so that the semiconductor region 14a2 of high impurity concentration is formed. , 14b2, 15a2, 15b2 are formed. As a result, the semiconductor regions 14a, 14b, 15a, 1 of the nMOS 14 and pMOS 15 in the peripheral circuit region P are
5b is formed.

Then, as shown in FIG. 11, an interlayer insulating film 8a made of, for example, SiO _{2 is} formed on the semiconductor substrate 1s by C.
After being deposited by the VD method or the like, an interlayer insulating film 8b made of BPSG or the like is deposited on the interlayer insulating film 8a by the CVD method or the like.

Subsequently, the upper surface of the interlayer insulating film 8b is subjected to chemical mechanical polishing (CM).
After planarization by the P) method, a mask film (first mask film) 10a made of, for example, low resistance polysilicon having phosphorus introduced therein is deposited on the interlayer insulating film 8b by the CVD method or the like.

Then, using the photoresist as a mask,
By patterning the mask film 10a by a dry etching method or the like, a pattern of the mask film 10a is formed such that an opening is formed above one semiconductor region 4b of the selection MOS 4.

At this time, in the first embodiment, since the upper surface of the interlayer insulating film 8b underlying the mask film 10a is made flat, a sufficient photolithography margin can be secured and good pattern transfer is possible. Is. In the peripheral circuit region P, the entire upper surface of the interlayer insulating film 8b is covered with the mask film 10a.

Here, the reason why the low resistance polysilicon is used as the mask film 10a is as follows. First
In addition, the etching selection ratio with respect to the silicon nitride film can be increased in the step of forming a connection hole for the capacitor 5 described later. Secondly, after the conductor film is embedded in the connection hole, the lower mask film 10a can be removed at the same time when the conductor film is etched back.

However, the constituent material of the mask film 10a is not limited to polysilicon and can be variously changed, and may be silicon nitride, for example.

Then, using the mask film 10a as an etching mask, the interlayer insulating films 8a and 8b exposed from the mask film 10a are removed by, for example, a dry etching method, and as shown in FIG. A connection hole (first capacitor connection hole) 9b1 is formed so that 4b is exposed. The diameter of the connection hole 9b1 is, for example, about 0.36 μm.

At this time, in the first embodiment, since the cap insulating film 7a and the sidewalls 7b are made of silicon nitride, the cap insulating film is set to have a high selection ratio with respect to silicon nitride in the dry etching process. 7a and the side wall 7b serve as an etching stopper, and the fine connection hole 9b1 can be formed in a self-aligning manner with high alignment accuracy.

For example, even if the position of the opening of the mask film 10a is slightly displaced in the width direction of the word line WL (left and right direction in FIG. 12), the cap insulating film 7a and the sidewall 7 are formed.
Since b is made of silicon nitride and functions as an etching stopper, part of the word line WL is not exposed from the connection hole formed by using the mask film as an etching mask.

Even if the position of the opening of the mask film 10a is deviated in the extending direction of the word line WL, in that case, the thickness of the lower field insulating film 2 is sufficiently large.
The connection hole formed using the mask film as an etching mask does not reach the upper portion of the semiconductor substrate 1s.

Therefore, in the first embodiment, a large number of connection holes 9b1 are secured in consideration of misalignment.
Since the alignment margin can be reduced, the area of the memory cell region M can be reduced.

The dry etching conditions at this time are as follows, for example. The selection ratio is, for example, about 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / A
r gas, for example, 3/5/200/550 sccm
It is a degree. The pressure is, for example, about 100 mTorr, and the high frequency power (RF Power) is, for example, about 1000 watts. The treatment temperature of the upper electrode / wall surface / lower electrode is, for example, about 20/60 / -10 ° C.

Subsequently, as shown in FIG. 13, after depositing a conductor film 13 made of low-resistance polysilicon into which phosphorus is introduced, for example, by a CVD method or the like on the semiconductor substrate 1s,
By etching back the conductor film 13 by a dry etching method or the like, as shown in FIG.
The conductor film 13 is embedded only in b1. At the time of this etch back process, the lower mask film 10a (see FIG. 13) is also removed.

After that, as shown in FIG. 15, an interlayer insulating film 8c made of, for example, SiO _{2 is} formed on the semiconductor substrate 1s by C.
It is deposited by the VD method or the like. The thickness of the interlayer insulating film 8c is, for example, about 500 to 1000Å.

Then, a mask film 10b made of, for example, low resistance polysilicon is deposited on the interlayer insulating film 8c by the CVD method or the like. The thickness of the mask film 10b is, for example, about 3000 to 6000Å.

Then, using the photoresist as a mask,
By patterning the mask film 10b by a dry etching process, an opening above the semiconductor region 4a in the mask film 10b is opened, and then the interlayer insulating films 8a to 8c in regions exposed from the opening are removed by a dry etching process. .

As a result, as shown in FIG. 16, the selection M
Connection hole 9a1 for exposing semiconductor region 4a of OS4
Perforate. The diameter of the connection hole 9a1 is 0.36, for example.
It is about μm.

At this time, in the first embodiment, since the cap insulating film 7a and the sidewalls 7b are made of silicon nitride, the cap insulating film is set to have a high selection ratio with respect to silicon nitride in the dry etching process. 7a and the side wall 7b serve as an etching stopper, and the fine connection hole 9a1 can be formed in a self-aligning manner with high alignment accuracy.

For example, even if the position of the opening of the mask film 10b is slightly shifted in the width direction of the word line WL (left and right direction in FIG. 16), the cap insulating film 7a and the sidewall 7 are formed.
Since b is made of silicon nitride and functions as an etching stopper, part of the word line WL is not exposed from the connection hole formed by using the mask film as an etching mask.

Even if the position of the opening of the mask film 10b is deviated in the direction in which the word line WL extends, in that case, the thickness of the lower field insulating film 2 is sufficiently large.
The connection hole formed using the mask film as an etching mask does not reach the upper portion of the semiconductor substrate 1s.

Therefore, in the first embodiment, a large number of connection holes 9a1 are secured in consideration of misalignment.
Since the alignment margin can be reduced, the area of the memory cell region M can be reduced.

The dry etching conditions at this time are as follows, for example. The selection ratio is, for example, about 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / A
r gas, for example, 3/5/200/550 sccm
It is a degree. The pressure is, for example, about 100 mTorr, and the high frequency power (RF Power) is, for example, about 1000 watts. The treatment temperature of the upper electrode / wall surface / lower electrode is, for example, about 20/60 / -10 ° C.

For example: The selection ratio is, for example, 10 to 15.

[0140] Thereafter, as shown in FIG. 17, on the resulting semiconductor substrate 1s, for example, conductive film phosphorus made of a conductor film BL1 and Wsi ₂ made of low-resistance poly-silicon introduced B
L2 is sequentially deposited by the CVD method or the like, and then the insulating film 6c made of SiO ₂ and the cap insulating film 11a made of silicon nitride are sequentially deposited on the conductor film BL2 by the CVD method or the like. The thickness of the cap insulating film 11a is, for example, about 2000Å.

Next, a photoresist 19a is formed on the cap insulating film 11a so as to cover the bit line formation region, and then the photoresist 19a is used as an etching mask to expose the cap insulating film 1 from the mask.
1a, insulating film 6c, conductor films BL2, BL1 and mask film 10b are sequentially removed by etching.

As a result, as shown in FIG. 18, the bit line BL composed of the conductor films BL1 and BL2 and the mask film 10b is formed. The bit line BL is electrically connected to one semiconductor region 4a of the selection MOS 4 through the connection hole 9a1.

Then, after removing the photoresist 19a (see FIG. 17), the semiconductor substrate 1 is subjected to a thermal oxidation treatment, so that the conductor film forming the bit line BL is formed as shown in FIG. A thin insulating film 6d made of, for example, SiO ₂ is formed on the side surfaces of BL1 and BL2 and the mask film 10b.

After that, an insulating film made of, for example, silicon nitride is deposited on the semiconductor substrate 1s by the CVD method, and then the insulating film is removed by anisotropic dry etching such as RIE to remove the bit line BL. Sidewalls 11b are formed on the side surfaces.

Next, an insulating film 12 made of silicon nitride or the like having a thickness of about 100 to 500 Å, preferably about 250 Å is deposited on the semiconductor substrate 1s by the CVD method.
This insulating film 12 has a function as an etching stopper in the wet etching removal step of the underlying insulating film after the capacitor forming process described later.

Then, as shown in FIG. 20, an insulating film 20 made of, for example, SiO _{2 is} formed on the semiconductor substrate 1s by CVD.
Method, the upper surface of the insulating film 20 is covered with, for example, CM.
It is flattened by the P method.

After that, on the semiconductor substrate 1s, for example, the mask film 10 made of low resistance polysilicon into which phosphorus is introduced.
c is deposited by the CVD method. In this case, the thickness of the mask film 10c is, for example, about 500 to 2000Å.

Next, in the mask film 10c, the capacitor connection portion forming region is opened by the photolithography technique and the dry etching technique, and then the mask film 10c is used as an etching mask.
2C by removing the insulating film 20, the insulating film 12 and the interlayer insulating film 8b in the region exposed from 0c by etching.
1, the connection hole 9b reaching the conductor film 13 is formed.
Form 2. The diameter of this connection hole 9a2 is, for example, 0.3.
It is about 6 μm.

At this time, in the first embodiment, since the cap insulating film 11a and the side wall 11b that cover the bit line BL are formed of silicon nitride, the selection ratio to silicon nitride in the dry etching process is set to be high. Thus, the cap insulating film 11a and the sidewall 11b serve as an etching stopper, and the fine connection hole (second capacitor connection hole) 9b2 can be formed in a self-aligning manner with high alignment accuracy.

Here, FIG. 22 shows a plan view of the main part of the memory cell region M at this stage, and FIGS. 23 and 24 are sectional views taken along lines XXIII-XXIII and XXIV-XXIV thereof.

In the case of the first embodiment, for example, the mask film 10c
Even if the position of the opening (see FIG. 21) is slightly displaced in the width direction of the bit line BL (vertical direction in FIG. 22), as can be seen from FIG. 24, the cap insulating film 11 a and the sidewall 11 b are made of silicon nitride. Since it also functions as an etching stopper, a part of the bit line BL is not exposed from the connection hole formed by using the mask film as an etching mask.

Even if the position of the opening of the mask film 10c (see FIG. 21) is displaced in the direction in which the bit line BL extends (left-right direction in FIG. 22), in that case, as can be seen from FIG. Since the cap insulating film 7a and the sidewall 7b covering the lower word line WL are made of silicon nitride and function as an etching stopper, the word line WL is exposed from the connection hole formed by using the mask film as an etching mask. Nor.

That is, in the first embodiment, as shown in FIG.
As shown in, the connection holes 9b1 and 9b2 for capacitors are
It is positioned and formed within a region A surrounded by the word line WL and the bit line BL. In addition,
Region B in FIG. 22 shows the formation range of the connection holes 9b1 and 9b2 in consideration of other alignment margins such as the alignment margin range in consideration of alignment with the element isolation region.

Dry etching conditions at this time are as follows, for example. The selection ratio is, for example, about 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / A
r gas, for example, 3/5/200/550 sccm
It is a degree. The pressure is, for example, about 100 mTorr, and the high frequency power (RF Power) is, for example, about 1000 watts. The treatment temperature of the upper electrode / wall surface / lower electrode is, for example, about 20/60 / -10 ° C.

Next, on the mask film 10c, for example, a thin film made of low-resistivity polysilicon having phosphorus introduced has a thickness of 500 to
After depositing a conductor film of about 1000 Å, an insulating film of SiO _{2 having} a thickness of about 3000 to 6000 Å is deposited on the upper surface by a plasma CVD method or the like.

The conductor film is also deposited in the connection holes 9b1 and 9b2 and electrically connected to the other semiconductor region 4b of the selection MOS 4 through the conductor film 13.

Further, the insulating film on the conductor film is the lower B layer.
It is formed of an insulating film having a higher etching rate in the wet etching process than the insulating film 20 made of PSG. This is because the etching rate of this insulation film is insulation film 2
When it is lower than 0, when the insulating film and the insulating film 20 are simultaneously removed in a later step, the insulating film is also buried in the narrow recess at the center of the first electrode 5a, This is because the insulating film 20 may be removed before the insulating film is sufficiently removed, which may adversely affect the underlying device.

Subsequently, in the insulating film, the conductor film and the mask film 10c, a portion exposed from the photoresist is removed by etching by a dry etching method or the like, so that the first electrode 5 of the capacitor is formed as shown in FIG.
The lower part 5a1 of a and the insulating film 21 are formed.

After that, a conductor film made of low-resistance polysilicon is deposited on the semiconductor substrate 1s by the CVD method, and the conductor film is etched back by the anisotropic dry etching method such as RIE, as shown in FIG. As shown
The side portion 5 of the first electrode 5a of the capacitor is formed on the side surface of the insulating film 21.
a2 is formed.

Then, the insulating films 20 and 21 are removed by wet etching using, for example, a hydrofluoric acid solution to form the first electrode 5a of the cylindrical capacitor, as shown in FIG. At this time, since the insulating film 12 formed on the interlayer insulating film 8c functions as a wet etching stopper, the underlying interlayer insulating film 8c is not removed.

Then, as shown in FIG. 28, after depositing a silicon nitride film (not shown) on the semiconductor substrate 1s by the CVD method, the silicon nitride film is subjected to an oxidation treatment to obtain silicon nitride. A SiO ₂ film is formed on the surface of the film to form a capacitor insulating film 5b made of a silicon nitride film and a SiO ₂ film.

After that, a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1s by the CVD method, and this conductor film is etched using a photoresist as a mask to form the second electrode 5c of the capacitor 5. Formed,
The capacitor 5 is formed.

Then, for example, Si is formed on the semiconductor substrate 1s.
After depositing an insulating film 8d1 made of O ₂ by a CVD method or the like, an insulating film 8d2 made of, for example, BPSG is deposited on the insulating film 8d1, and the upper surface of this insulating film 8d2 is
For example, flattening is performed by the CMP method.

Subsequently, the wiring forming process is performed. This wiring forming process will be described with reference to FIGS. In addition,
29 to 32 are shown in FIG. 5 in order to explain the wiring forming process.
28 shows a cross section of a portion different from FIG. 28, but the same D
FIG. 3 is a cross-sectional view of a main part of RAM.

First, as shown in FIG. 29, the semiconductor substrate 1
An interlayer insulating film 8e made of, for example, SiO _{2 is provided} on
It is deposited by the D method or the like. Thereby, the capacitor 5 is covered.

Subsequently, a connection hole 22a is formed in the interlayer insulating film 8e using the photoresist as a mask so that the pad portion of the second electrode 5c of the capacitor 5 is exposed, and the MOS.FET 23 in the peripheral circuit region P is formed. A connection hole 22b is formed by dry etching so that one semiconductor region 23a is exposed.

After that, a conductor film made of, for example, titanium (Ti) is deposited on the semiconductor substrate 1s by the sputtering method or the like, and then a conductor film made of, for example, tungsten is deposited on the upper surface thereof by the CVD method or the like. A conductor film made of, for example, titanium nitride (TiN) is deposited on the upper surface by a sputtering method or the like.

Next, the laminated conductor film is patterned by a dry etching method or the like using a photoresist as a mask to form a first layer wiring 24a as shown in FIG.

Then, on the semiconductor substrate 1s, for example, Si
After the interlayer insulating film 8f made of O ₂ is deposited by the CVD method or the like to cover the first layer wiring 24a, the interlayer insulating film 8f is deposited.
By performing a dry etching process on f using a photoresist as a mask, a connection hole 22c is formed so that a part of the first layer wiring 24a is exposed.

Thereafter, as shown in FIG. 31, second layer wiring 24b is formed on interlayer insulating film 8f. The second layer wiring 24b is formed, for example, as follows.

First, after depositing a conductor film made of, for example, tungsten by the CVD method or the like, a conductor film made of, for example, aluminum (Al) or the like is deposited on the upper surface thereof by the sputtering method, and further, on the upper surface thereof, for example, T
A conductor film made of iN or the like is deposited by the sputtering method. Then, the laminated conductor film is formed by patterning similarly to the first layer wiring 24a.

Then, for example, Si is formed on the interlayer insulating film 8f.
After the interlayer insulating film 8g made of O ₂ is deposited by the CVD method or the like to cover the second layer wiring 24b, the interlayer insulating film 8g is formed.
By performing a dry etching process on g using a photoresist as a mask, a connection hole 22d is formed so that the second layer wiring 24b is exposed.

Subsequently, as shown in FIG. 32, a third layer wiring 24c is formed on the interlayer insulating film 8g. Third layer wiring 24
c is made of the same material as the second layer wiring 24b and is formed by the same method.

Finally, on the semiconductor substrate 1s, for example, Si
By depositing the surface protection film 25 made of O ₂ by the CVD method or the like and covering the third layer wiring 24c, the wafer process of the DRAM of the first embodiment is completed.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Since the connection holes 9a1 for connecting the bit lines and the connection holes 9b1, 9b2 for connecting the capacitors can be formed in a self-aligning manner, the connection holes 9a1, 9b.
It is possible to eliminate the need for photolithography alignment between 1,9b2 and each layer.

(2). Since the upper surface of the base insulating film at the time of forming the connection holes 9a1 for connecting the bit lines and the connection holes 9b1, 9b2 for connecting the capacitors can be made flat, the connection holes 9a1, 9a1, The margin in the photolithography for forming 9b1 and 9b2 can be improved, and the pattern transfer accuracy can be improved.

(3) By the above (1) and (2), the connection hole 9a1 for connecting the bit line and the connection hole 9b1, for connecting the capacitor are formed.
Since the alignment margin of 9b2 can be reduced, the size of the memory cell MC can be reduced.
Therefore, the size of the semiconductor chip can be reduced.

(4). By the above (1) and (2), the connection hole 9a1 for connecting the bit line and the connection hole 9b1, for connecting the capacitor are formed.
Since connection failure at 9b2 can be reduced, DR
It is possible to improve the yield and reliability of AM.

(5). By the above (1) and (2), the connection hole 9a1 for connecting the bit line and the connection hole 9b1, for connecting the capacitor are formed.
9b2 does not require sophisticated alignment technology or process control. Further, it is not necessary to introduce a sophisticated and expensive photolithography technique such as a phase shift technique in order to increase the resolution of the transfer pattern.

(6). Cap insulating film 7 in memory cell region M
a and the sidewall 7b are the MO of the peripheral circuit region P.
Since it can be formed at the same time as the cap insulating film 7a and the sidewall 7b for forming the LDD structure of the S.FET, the manufacturing process is not significantly increased.

(7). Due to the above (5) and (6), it is possible to shorten the development period of a semiconductor integrated circuit device having a DRAM.

(Embodiment 2) FIG. 33 is a cross-sectional view of essential parts of a memory cell region of a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device of the second embodiment shown in FIG. 33 shows the case where the conductor film for embedding shown in the first embodiment is not provided in the connection hole 9b1 for the capacitor 5.

The connection hole 9b1 in this case is formed, for example, as follows. First, similarly to the first embodiment, the bit line BL and the insulating films 6c and 6d that cover the bit line BL, the cap insulating film 11a, the sidewalls 11b and the insulating film 12 are formed.
To form

Subsequently, after covering the insulating film 12 with the insulating film, the upper surface of the insulating film is flattened. After that, a mask film 10b made of, for example, low-resistance polysilicon is formed on the insulating film, and using the mask film 10b as a mask, the insulating film, the insulating film 12, and the interlayer insulating films 8a to 8c are formed on the semiconductor region on the semiconductor substrate 1s. Connection hole 9 so that 4b is exposed
b1 is perforated by a dry etching method.

At this time, also in the second embodiment, the cap insulating film 7a and the sidewalls 7b which cover the word lines WL, and the cap insulating film 11 which covers the bit lines BL.
By forming a and the side wall 11b of silicon nitride, the connection hole 9b1 can be formed in a self-aligned manner.

Therefore, also in the second embodiment, the first embodiment is used.
It is possible to obtain the same effect as.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments 1 and 2 and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first and second embodiments, the case where the capacitor of the memory cell has a cylindrical shape has been described, but the present invention is not limited to this, and various modifications are possible. For example, a fin shape may be used.

In the first and second embodiments, the case where the bit line is formed by providing the silicide layer on the low resistance polysilicon has been described. However, the present invention is not limited to this, and only the silicide layer is used. You may form.
In this case, the bit line BL can be thinned.

In the first and second embodiments, the case where both the word line and the bit line are covered with the cap insulating film made of silicon nitride and the side wall has been described, but the present invention is not limited to this. This can be changed, and for example, only the word line may be covered with the cap insulating film and the sidewall made of silicon nitride, or only the bit line may be covered with the cap insulating film and the sidewall made of silicon nitride.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the case of application to M has been described, the present invention is not limited to this, and various applications are possible, such as SRAM,
The present invention can be applied to other semiconductor integrated circuit devices in which a ROM, a logic circuit or a semiconductor memory circuit and a logic circuit are provided on the same semiconductor substrate.

[0194]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1). The capacitor connection hole and the bit line connection hole can be formed in a self-aligned manner.

(2). Since the underlying insulating film is flattened when forming the capacitor connection hole and the bit line connection hole, it is possible to secure a sufficient focus margin in the photolithography technique when transferring the connection hole pattern. it can.

(3). Because of the above (1) and (2), it is possible to reduce the alignment margin of the capacitor connection hole and the bit line connection hole. Even without it, the memory cell size can be reduced.

(4). Because of the above (1) and (2), it is possible to reduce the memory cell size by the existing technology without introducing the advanced lithography technology and the advanced alignment technology. Is unnecessary, and the development period of a semiconductor integrated circuit device having a DRAM can be shortened.

(5) By the above (1) and (2), it is possible to improve the alignment accuracy of the capacitor connecting hole and the bit line connecting hole, so that the connection failure in these connecting holes is reduced. Therefore, the yield and reliability of the semiconductor integrated circuit device having the DRAM can be improved.

(6). By forming the first cap insulating film and the first side wall insulating film at the same time as the step of forming the cap insulating film and the side wall insulating film for covering the gate electrode of the MISFET forming the peripheral circuit of the DRAM, It is possible to obtain the effects (1) to (4) described above without significantly increasing the number of manufacturing steps.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a memory cell region of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a peripheral circuit region of the semiconductor integrated circuit device of FIG.

3 is a plan view of relevant parts of a memory cell region of the semiconductor integrated circuit device of FIG.

FIG. 4 is a plan view of relevant parts of a memory cell region of the semiconductor integrated circuit device of FIG.

5 is a main-portion cross-sectional view of the semiconductor integrated circuit device in FIG. 1 during the manufacturing process thereof;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 5;

7 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 6;

8 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 9;

11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 10;

12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 11;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 16;

18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 17;

19 is a cross-sectional view of essential parts in the manufacturing process continued from FIG. 18 of the semiconductor integrated circuit device of FIG. 1;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 19;

21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 20; FIG.

22 is a main-portion plan view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing step of FIG. 21;

23 is a cross-sectional view taken along the line XXIII-XXIII of FIG.

24 is a sectional view taken along line XXIV-XXIV in FIG.

25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 21;

26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 25;

27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 26;

28 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 27;

29 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 28; FIG.

30 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 29; FIG.

31 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 30; FIG.

32 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 31; FIG.

FIG. 33 is a fragmentary cross-sectional view of a memory cell region of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1s semiconductor substrate 2 field insulating film 3p p well 3n n well 4 memory cell selection MOS / FET 4a, 4b semiconductor region 4c gate insulating film 4d gate electrode 4d1, 4d2 conductive film 5 capacitor 5a first electrode (third conductive film) 5b Capacitor insulating film 5c Second electrode 6a to 6d Insulating film 7a Cap insulating film (First cap insulating film) 7b Side wall (First sidewall insulating film) 8a to 8g Interlayer insulating film 8d1, 8d2 Insulating film 9a1 Connection hole 9b1 Connection hole (First capacitor connection hole) 9b2 Connection hole (second capacitor connection hole) 10a Mask film (first mask film) 10b Mask film (second mask film) 10c Mask film (third mask film) 11a Cap insulating film (Second cap insulating film) 11b Side wall (second side wall insulating film) 12 Insulating film 13 Conductor film (first Body film) 14 n-channel type MOS • FET 15 p-channel type MOS • FET 16 Insulating film 17 Insulating film 18d1, 18d2 Conductor film 19a Photoresist 20 Insulating film 21 Insulating film 22a-22d Connection hole 23 MOS • FET 23a Semiconductor Area 24a First layer wiring 24b Second layer wiring 24c Third layer wiring 25 Surface protective film M Memory cell area P Peripheral circuit area MC Memory cell WL Word line BL Bit line BL1, BL2 Conductor film (second conductor film)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideo Aoki 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Yoshitaka Tadaki 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Co., Ltd. Inside the center (72) Inventor Keizo Kawakita 2326 Imai, Ome-shi, Tokyo Metropolitan area, Device Development Center, Hitachi, Ltd. (72) Inventor Jun Murata 2326 Imai, Ome-shi, Tokyo Metropolitan area, Device Development Center, Hitachi (72) Inventor Katsuo Yuhara 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texus Instruments Co., Ltd. (72) Inventor Michio Nishimura 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan (72) Inventor Kazuhiko Saito 235 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture 0 Nihon Texus Instruments Co., Ltd. (72) Inventor Minoru Otsuka 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture (350) Nihon Textus Instruments Co., Ltd. (72) Masayuki Yasuda 2350 Kiura, Miura-mura, Inashiki-gun, Ibaraki -Instruments Co., Ltd. (72) Inventor Toshiyuki Kakiyama 2350 Miuramura, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. (72) Inventor Zhao Sung, 2350 Miura-mura Kihara, Inashiki-gun, Ibaraki Nippon Tex Instruments Instruments Co., Ltd. In the company

Claims (17)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a wiring layer on a semiconductor substrate, comprising the following steps. (A) A step of forming a plurality of wirings adjacent to each other on a semiconductor substrate. (B) A step of covering the upper surface and the side surface of the wiring with a cap insulating film and a sidewall insulating film made of silicon nitride. (C) A step of forming, on the semiconductor substrate, an insulating film having a flat upper surface made of a material having an etching rate faster than that of the silicon nitride and covering the cap insulating film and the sidewall insulating film. (D) A mask film made of a material having a slower etching rate than that of the insulating film is deposited on the upper surface of the insulating film, and then, a contact hole forming region located between the plurality of adjacent wirings in the mask film. Step of opening. (E) A step of forming a connection hole defined in a self-aligned manner by the cap insulating film and the sidewall insulating film by etching away the insulating film exposed from the opening region of the mask film. 2. A method of manufacturing a semiconductor integrated circuit device having a wiring layer on a semiconductor substrate, comprising the following steps. (A) A step of forming a plurality of wirings adjacent to each other on a semiconductor substrate. (B) A step of covering the upper surface and the side surface of the wiring with a cap insulating film and a sidewall insulating film made of silicon nitride. (C) A step of forming, on the semiconductor substrate, an insulating film having a flat upper surface made of a material having an etching rate faster than that of the silicon nitride and covering the cap insulating film and the sidewall insulating film. (D) A mask film made of a material having a slower etching rate than that of the insulating film is deposited on the upper surface of the insulating film, and then, a contact hole forming region located between the plurality of adjacent wirings in the mask film Step of opening. (E) A step of forming a connection hole defined in a self-aligned manner by the cap insulating film and the sidewall insulating film by etching away the insulating film exposed from the opening region of the mask film. (F) A step of depositing a conductor film on the semiconductor substrate after forming the connection hole, and then etching back the conductor film to embed the conductor film in the connection hole. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the mask film and the conductor film are made of low-resistance polysilicon. 4. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride. (B) Forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate and covering the first cap insulating film and the first sidewall insulating film . (C) After depositing a first mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the word lines adjacent to each other in the first mask film. A step of opening a first capacitor connection hole forming region. (D) A first capacitor connection hole that exposes one semiconductor region of the memory cell selection MISFET is formed by etching away the first insulating film portion exposed from the opening region of the first mask film. A step of forming holes in a self-aligned state defined by the first cap insulating film and the first sidewall insulating film. (E) A first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back so that the inside of the first capacitor connection hole is formed. Step of embedding the first conductor film. 5. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride. (B) Forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate and covering the first cap insulating film and the first sidewall insulating film . (C) After depositing a second mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the word lines adjacent to each other in the second mask film. A step of opening a formation region of the bit line connection hole located. (D) A bit line connection hole that exposes one semiconductor region of the memory cell selection MISFET is formed by etching away the first insulating film portion exposed from the opening region of the second mask film. 1 Step of perforating in a state of being defined in a self-aligned manner by the cap insulating film and the first sidewall insulating film. (E) A step of forming the bit line by depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole and then patterning the second conductor film. 6. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line so as to extend orthogonally to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride. (B) Forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate and covering the first cap insulating film and the first sidewall insulating film . (C) After depositing a first mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the word lines adjacent to each other in the first mask film. A step of opening a first capacitor connection hole forming region. (D) A first capacitor connection hole that exposes one semiconductor region of the memory cell selection MISFET is formed by etching away the first insulating film portion exposed from the opening region of the first mask film. A step of forming holes in a self-aligned state defined by the first cap insulating film and the first sidewall insulating film. (E) A first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back so that the inside of the first capacitor connection hole is formed. Step of embedding the first conductor film. (F) A step of depositing a second insulating film on the first insulating film after the step of filling the first conductive film. (G) After depositing a second mask film made of a material having an etching rate lower than that of the first insulating film and the second insulating film on the second insulating film, the second mask films are adjacent to each other. A step of forming a bit line connection hole forming region located between the word lines. (H) A bit line connection hole that exposes the other semiconductor region of the memory cell selection MISFET is formed by etching away the second insulating film and the first insulating film exposed from the opening region of the second mask film. A step of punching in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner. (I) A step of forming the bit line by depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole and then patterning the second conductor film. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first cap insulating film and the first sidewall insulating film are formed on the upper surface and the side surface of the gate electrode of the MISFET for the peripheral circuit. A method for manufacturing a semiconductor integrated circuit device, which is formed simultaneously with a cap insulating film and a sidewall insulating film. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first mask film, the second mask film, the first conductor film and the second conductor film are made of low resistance polysilicon. A method for manufacturing a semiconductor integrated circuit device, comprising: 9. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride. (B) Forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate and covering the first cap insulating film and the first sidewall insulating film . (C) After depositing a first mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the word lines adjacent to each other in the first mask film. A step of opening a first capacitor connection hole forming region. (D) A first capacitor connection hole that exposes one semiconductor region of the memory cell selection MISFET is formed by etching away the first insulating film portion exposed from the opening region of the first mask film. A step of forming holes in a self-aligned state defined by the first cap insulating film and the first sidewall insulating film. (E) A first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back so that the inside of the first capacitor connection hole is formed. Step of embedding the first conductor film. (F) A step of depositing a second insulating film on the first insulating film after the step of filling the first conductive film. (G) After depositing a second mask film made of a material having an etching rate lower than that of the first insulating film and the second insulating film on the second insulating film, the second mask films are adjacent to each other. A step of forming a bit line connection hole forming region located between the word lines. (H) A bit line connection hole that exposes the other semiconductor region of the memory cell selection MISFET is formed by etching away the second insulating film and the first insulating film exposed from the opening region of the second mask film. A step of punching in a state defined by the first cap insulating film and the first sidewall insulating film in a self-aligned manner. (I) A step of forming the bit line by depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole and then patterning the second conductor film. (J) A step of covering the upper surface and the side surface of the bit line with a second cap insulating film and a second sidewall insulating film made of silicon nitride. (K) A third insulating film having a flat upper surface made of a material having a higher etching rate than that of silicon nitride is deposited on the second insulating film to cover the second cap insulating film and the second sidewall insulating film. Process. (L) After depositing a third mask film made of a material having a slower etching rate than the third insulating film on the upper surface of the third insulating film, forming a first capacitor connection hole in the third mask film Step of opening an area. (M) By etching away the third insulating film and the second insulating film portion exposed from the opening region of the third mask film, the first conductor film embedded in the first capacitor connection hole is exposed. Such a connection hole for the second capacitor,
Perforating in a state defined by the second cap insulating film and the second sidewall insulating film in a self-aligned manner. (N) A first electrode in the capacitor for storing information by depositing a third conductor film on the semiconductor substrate after forming the second capacitor connection hole and then patterning the third conductor film. Forming part of the. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the first cap insulating film and the first sidewall insulating film are formed on an upper surface and a side surface of a gate electrode of a MISFET for a peripheral circuit. A method for manufacturing a semiconductor integrated circuit device, which is formed simultaneously with a cap insulating film and a sidewall insulating film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the first mask film, the second mask film, the third mask film, the first conductor film, the second conductor film, and the second mask film. A method of manufacturing a semiconductor integrated circuit device, wherein the third conductor film is made of low resistance polysilicon. 12. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride. (B) Forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate and covering the first cap insulating film and the first sidewall insulating film . (C) After depositing a second mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the word lines adjacent to each other in the second mask film. A step of opening a region for forming a connection hole for a bit line located. (D) A bit line connection hole that exposes one semiconductor region of the memory cell selection MISFET is formed by etching away the first insulating film portion exposed from the opening region of the second mask film. 1 Step of perforating in a state of being defined in a self-aligned manner by the cap insulating film and the first sidewall insulating film. (E) A step of forming the bit line by depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole and then patterning the second conductor film. (F) A step of covering the upper surface and the side surface of the bit line with a second cap insulating film and a second sidewall insulating film made of silicon nitride. (G) A third insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride is deposited on the first insulating film to cover the second cap insulating film and the second sidewall insulating film. The process of doing. (H) After depositing a third mask film made of a material having an etching rate slower than that of the third insulating film on the upper surface of the third insulating film, between the word lines adjacent to each other and in the third mask film. First located between bit lines adjacent to each other
A step of opening a capacitor connection hole formation region. (I) For the first capacitor such that the other semiconductor region of the memory cell selection MISFET is exposed by etching away the first insulating film and the third insulating film portion exposed from the opening region of the third mask film. A step of forming a connection hole in a state defined by the first cap insulating film, the first sidewall insulating film, the second cap insulating film, and the second sidewall insulating film in a self-aligned manner. (J) A first electrode in the capacitor for storing information by depositing a third conductor film on the semiconductor substrate after forming the connection hole for the first capacitor and then patterning the third conductor film. Forming part of the. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the first cap insulating film and the first sidewall insulating film are formed on an upper surface and a side surface of a gate electrode of a MISFET for a peripheral circuit. A method for manufacturing a semiconductor integrated circuit device, which is formed simultaneously with a cap insulating film and a sidewall insulating film. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the second mask film, the third mask film, the second conductor film and the third conductor film are made of low resistance polysilicon. A method for manufacturing a semiconductor integrated circuit device, comprising: 15. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bit line and a capacitor for storing information on an upper layer of the bit line, comprising: A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (A) A step of covering the upper surface and the side surface of the bit line with a second cap insulating film and a second sidewall insulating film made of silicon nitride. (B) A step of forming, on the semiconductor substrate, an insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride and covering the second cap insulating film and the second sidewall insulating film. (C) After depositing a mask film made of a material having an etching rate slower than that of the insulating film on the upper surface of the insulating film, first capacitor connection holes located between bit lines adjacent to each other in the mask film. A step of opening a formation region. (D) A first semiconductor region of the memory cell selection MISFET is exposed by etching away the insulating film portion exposed from the opening region of the mask film.
A step of forming a capacitor connection hole in a state of being defined by the second cap insulating film and the second sidewall insulating film in a self-aligned manner. (E) By depositing a conductor film on the semiconductor substrate after forming the connection hole for the first capacitor, and patterning the conductor film, a part of the first electrode in the capacitor for storing information is removed. Forming process. 16. A word line forming a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate, and a word line extending above the word line and extending so as to be orthogonal to the extending direction of the word line. A semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor-over-bitline structure, which comprises a bitline and a capacitor for storing information on an upper layer of the bitline,
A semiconductor integrated circuit device having the following configuration. (A) A first cap insulating film and a first sidewall insulating film made of silicon nitride for covering the upper surface and the side surface of the word line. (B) A second cap insulating film and a second sidewall insulating film made of silicon nitride for covering the upper surface and the side surface of the bit line. (C) A first insulating film having a flat upper surface that covers the first cap insulating film and the first sidewall insulating film. (D) A first connection hole that is perforated so that one semiconductor region of the memory cell selection MISFET is exposed while being defined in a self-aligned manner by the first cap insulating film and the first sidewall insulating film. (E) A first conductor film embedded in the first connection hole. (F) A second connection hole that is perforated so that the upper surface of the first conductor film is exposed in a state of being defined in a self-aligned manner by the second cap insulating film and the second sidewall insulating film. (G) A second conductor film formed in the second connection hole in a state of being electrically connected to the first conductor film. 17. The semiconductor integrated circuit device according to claim 16, wherein the first conductor film and the second conductor film are a part of a lower electrode of a capacitor for storing information of the memory cell. Semiconductor integrated circuit device.