JP2000124152A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bore a self-aligned contact hole capable of decreasing a necessary selection ratio, when a sidewall is removed. SOLUTION: A conductive layer 32 and an offset insulating film 21 are formed on a semiconductor substrate 10, a lightly-doped region 11 is formed inside the substrate 10, an etching stopper film 21 is formed, a sidewall mask layer is formed confronting the sidewall of the conductive layer 32, and a heavily-doped region 12 is formed using the sidewall mask layer as a mask. Then, the sidewall mask layer is removed, a first insulating film 23 is formed on the etching stopper film 21, a contact hole CH is bored to make the heavily- doped region exposed, second insulating films (24a and 25a) are formed on the inner wall of the contact hole CH, and an embedded electrode is formed inside the contact hole CH.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having fine contacts.

[0002]

2. Description of the Related Art As the integration and performance of semiconductor devices have progressed, as seen in recent VLSIs and the like, the technical elements of dry etching of silicon oxide (SiO ₂ ) -based material layers have also increased. It's getting tougher.

[0003] Among them, a self-aligned contact (SAC) technology, which can eliminate a design margin on a mask for positioning in a contact hole process, has attracted attention.

The development of this SAC technology is particularly
It is becoming active in the generations after the m rule, for several reasons. One is the limitation due to the performance of the exposure apparatus, and the other is to actively reduce the chip or cell area by using the SAC to improve the wafer yield and increase the operation speed.

[0005] In particular, the former is 0.25 μm recently announced.
This means that it is difficult to maintain the trend of miniaturization of wiring layers in an exposure machine for mass production. This is due to a lack of improvement in the variation in the alignment of the stepper, and the variation in the alignment is large, so that the design margin of the alignment is increased. As a result, there arises a problem that the wiring width is increased or the hole diameter becomes too small to form an opening. The signs are beginning to appear from the 0.3 μm rule, and the problem cannot be avoided with the 0.25 to 0.2 μm rule.

[0006] SAC is a technique that is said to eliminate the need for a design margin for this alignment. There are several methods for forming the SAC, each of which generally has the disadvantage of making the process somewhat more complicated than the conventional method using only exposure. However, its adoption is essential in the future,
Various studies have been made on SAC.

As a semiconductor device using the above SAC,
A description will be given of an SRAM (Static Random Access Memory) as an example. FIG. 9 is an equivalent circuit diagram of one memory cell of a conventional SRAM. One of the source / drain electrodes of the word transistors Tr1 and Tr2, which are NMOS gate controlled by the word line WL, is connected to the bit lines BL and BL , respectively.
The other source / drain electrode is a storage node A (node)
A) and a storage node B (node B). The storage node A is connected to the ground GND via a driver transistor Tr3 which is an NMOS, and further connected to a power supply voltage supply line Vcc via a load transistor Tr5 which is a PMOS. The storage node B is connected to the ground GND via a driver transistor Tr4 which is an NMOS, and is further connected to a power supply voltage supply line Vcc via a load transistor Tr6 which is a PMOS.
Connected to. The storage node A is connected to the gate electrodes of the driver transistor Tr4 and the load transistor Tr6, while the storage node B is connected to the gate electrodes of the driver transistor Tr3 and the load transistor Tr5. Thus, a circuit configuration called a flip-flop is formed.

FIG. 10 is a plan view of one memory cell of the SRAM. In the figure, hatched portions are gate electrodes, and shaded regions on both sides thereof indicate source / drain regions S / D. A word transistor Tr is connected to the word line WL.
1 and Tr2, a driver transistor Tr3 and a load transistor Tr5 are formed on the gate electrode G1, and an extension of the gate electrode G1 is connected to the source / drain connecting the word transistor Tr2 and the driver transistor Tr4 via the shared contact SC2. Connected to the area. Further, a driver transistor Tr4 and a load transistor Tr6 are formed on the gate electrode G2, and an extension of the gate electrode G2 is connected to the source / drain region of the load transistor Tr5 via a shared contact SC1. In the figure, SAC1 to 8 are self-aligned contacts, SAC1 and 2 are connected to a power supply voltage line, SAC3 and 4 are connected to ground, SAC5 and 6 are connected to bit lines, SAC7 is connected to SC1, and SAC8 is connected to SC2. It is formed. Here, it is shown that the portion indicated by Z in FIG. 9 corresponds to the gate electrode G2 in FIG.

FIG. 11 is a sectional view taken along the line AB in FIG. An n-type well 10a is formed in a p-type semiconductor substrate 10, a gate insulating film 20 is formed on an active region separated by a LOCOS element isolation insulating film 13, and a lower layer made of, for example, polysilicon is formed thereon. A gate electrode 32 having a polycide structure including a gate electrode 30 and an upper gate electrode 31 made of tungsten silicide is formed, and a source / drain diffusion layer (not shown) is formed in the semiconductor substrate 10 or the well 10a on both sides of the gate electrode. The transistor is formed as described above.

An offset insulating film 21 made of, for example, silicon oxide is formed on an upper layer of the gate electrode 32, and a first etching stopper film 22 made of, for example, silicon oxide is formed on the entire surface so as to cover the upper layer. A second etching stopper film 26 made of, for example, silicon nitride is formed thereon, and an interlayer insulating film 23 made of, for example, silicon oxide is formed thereon. Contact holes (SAC, SC) reaching the source / drain diffusion layers (not shown) formed in the substrate are opened in the interlayer insulating film 23, the second etching stopper film 26, and the first etching stopper film 22. An upper wiring 34 composed of an adhesion layer 34a, a wiring layer 34b, a barrier metal layer 34c, and the like is formed. Where SA
The contact indicated by C is a self-aligned contact,
The contact indicated by C is a shared contact that connects the gate electrode 32 and a source / drain diffusion layer (not shown).

In the above method for manufacturing a semiconductor device,
First, as shown in FIG.
An OCOS element isolation insulating film 13 and an n-type well 10a are formed, and a gate insulating film 20 is formed in an active region. On the upper layer, for example, a lower gate electrode 30 of polysilicon and an upper gate electrode 3 of tungsten silicide
A gate electrode 32 having a polycide structure composed of
For example, the offset insulating film 21 made of silicon oxide is patterned. Next, an LD (not shown) is ion-implanted.
A D (Lightly Doped Drain) diffusion layer is formed, then a first etching stopper film 22 made of, for example, silicon oxide is formed on the entire surface, and a polycrystalline material containing, for example, phosphorus is formed on the side walls of the offset insulating film 21 and the gate electrode 32. A sidewall mask layer 33a made of silicon or amorphous silicon is formed. Next, ion implantation is performed using the sidewall mask layer 33a as a mask to form a source / drain diffusion layer (not shown). With the above, LD
A transistor having a D structure is formed.

[0013] Next, as shown in FIG. 13, after performing an etching process having a selectivity with respect to the first etching stopper film 22 to remove the sidewall mask layer 33 a, a second surface made of, for example, silicon nitride is formed on the entire surface. An etching stopper film 26 is formed, and then an interlayer insulating film 23 made of, for example, silicon oxide is formed. If necessary, reflow, etch back, or CMP (Chemical Mechanical) is performed.
cal Polishing).

Next, a resist film having a contact opening pattern is formed, and an etching process such as RIE (reactive ion etching) is performed to open a contact hole.
In the contact hole, an adhesion layer 34a, a wiring layer 34b, a barrier metal layer 34c, and the like are formed and patterned to form an upper wiring 34, thereby obtaining the semiconductor device shown in FIG.

The method of opening a self-aligned contact used in the method of manufacturing a semiconductor device will be described in more detail with reference to FIGS.

FIG. 14 is a sectional view of a semiconductor device in which the above-described self-aligned contact is opened. In the active region having a channel formation region separated by an element isolation insulating film (not shown) of the silicon semiconductor substrate 10, a lower gate electrode 31 of polysilicon and a tungsten silicide are formed on the upper layer of the semiconductor substrate 10 via a gate insulating film 20. A gate electrode 32 having a polycide structure composed of the upper gate electrode 31 is formed. In the semiconductor substrate 10 on both sides of the gate electrode 32, an LDD diffusion layer 11 containing a low concentration of conductive impurities and a source / drain diffusion layer 12 containing a high concentration of a conductive impurity are formed. A transistor is formed. An offset insulating film 21 of silicon oxide is formed on the upper layer of the gate electrode 32, and covers the gate electrode 32 and the offset insulating film 21, for example, a first etching stopper film 22 of silicon oxide and a second etching of silicon nitride. Stopper film 2
6 are laminated, and an interlayer insulating film 23 of silicon oxide is formed thereon.

The interlayer insulating film 23, the second etching stopper film 26, and the first etching stopper film 22 have contact holes CH reaching the source / drain diffusion layers 12.
The adhesion layer 34a, the wiring layer 34b, and the barrier metal layer 34c are laminated and patterned to form an upper wiring 34 so as to cover and bury the inner wall of the hole.

Here, in the above-described semiconductor device, the opening position of the contact hole is shifted to the right in the drawing, but the second etching stopper film 23a and the first etching stopper film 22a are formed on the inner wall surface of the contact hole CH.
Are left, the gate electrode 32 is not exposed in the contact hole CH, and a stable contact connection between the upper wiring 34 and the source / drain diffusion layer 12 is formed.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 15A, an element isolation insulating film (not shown) is formed on the silicon semiconductor substrate 10, and a channel impurity (not shown) is introduced into an active region separated by the element isolation insulating film. For example, the gate insulating film 20 is formed by a thermal oxidation method, and the polysilicon film 30a, 100 having a thickness of 125 nm is formed thereover by, for example, a CVD method.
A tungsten silicide film 31a having a thickness of nm is deposited. Next, for example, TEOS (tetra-ethyl-
25 by low pressure CVD method using orthosilicate) as raw material.
Silicon oxide is deposited to a thickness of 0 nm to form an offset insulating film 21a. Next, the offset insulating film 21a
A resist film R1 having a gate electrode pattern is formed on the upper layer by a photolithography process.

Next, as shown in FIG. 15B, an etching treatment such as RIE is performed using the resist film R1 as a mask, and the polysilicon film 30a, the tungsten silicide film 31a, and the offset insulating film 21a are pattern-processed. A gate electrode 32 having a polycide structure including a lower gate electrode 30 of polysilicon and an upper gate electrode 31 of tungsten silicide and having an offset insulating film 21 is formed. After that, the resist film R1 is removed.

Next, as shown in FIG. 15C, a conductive impurity D1 is ion-implanted into the semiconductor substrate 10 using the offset insulating film 21 as a mask, and the LDD diffusion layer is self-aligned with the gate electrode 32. 11 is formed.

Next, as shown in FIG. 16D, the entire surface is covered with the gate electrode 32 and the offset insulating film 21 by a low pressure CVD method using, for example, TEOS as a raw material.
A first oxide stopper film 22 is formed by depositing a silicon oxide film with a thickness of 0 nm.

Next, as shown in FIG. 16E, a polysilicon or amorphous silicon containing phosphorus is deposited to a thickness of 90 nm by, for example, a CVD method to form a side wall mask layer 33, FIG.
As shown in (f), the entire surface is etched back by etching such as RIE to form a sidewall mask layer 33a.
To form

Next, as shown in FIG. 17G, using the sidewall mask layer 33a as a mask, conductive impurities D2 are ion-implanted into the semiconductor substrate 10 to form the source / drain diffusion layers 12. With the above, the source of the LDD structure
It can be a drain region. At this time, the width of the sidewall mask layer 33a becomes the LDD width, that is, the sidewall mask layer 33a becomes an LDD spacer.

Next, as shown in FIG. 17H, the sidewall mask layer 33a made of polysilicon or amosphasic silicon is removed with a selectivity to the first etching stopper film 22 of silicon oxide. The sidewall mask layer 33a is removed by etching under conditions (for example, plasma etching of a downflow type).

Next, as shown in FIG. 17I, silicon nitride is deposited to a thickness of 80 nm over the entire surface of the first etching stopper film 22 by, for example, a low pressure CVD method.
A second etching stopper film 26 is formed.

Next, as shown in FIG. 18J, silicon oxide (BPSG) containing boron and phosphorus is deposited by a CVD method using, for example, O ₃ and TEOS as raw materials. Back or C
A planarization process such as MP is performed to form an interlayer insulating film 23. Here, the total thickness T of the interlayer insulating film 23, the second etching stopper film 26, and the first etching stopper film 22 is formed to be, for example, 700 nm.

Next, as shown in FIG. 18K, a resist film R2 having a contact hole opening pattern is formed on the interlayer insulating film 23 by a photolithography process. Here, the drawing shows that a resist film R2 having a contact hole opening diameter Q of about 340 nm has a width of 12 in the R direction with respect to an interval S of the gate electrode 32 of about 470 nm.
This shows a case where a pattern is formed with a shift of 0 nm.

Next, as shown in FIG. 19 (l), a contact hole CH for exposing the second etching stopper film 22 is opened by an etching process such as ECR type plasma etching. Here, etching is performed under the condition that the interlayer insulating film made of BPSG is etched with a selectivity with respect to the second etching stopper film 22 made of silicon nitride, so that the surface of the second etching stopper film 22 is exposed. To stop.

Next, as shown in FIG. 19 (m), the second etching stopper film 22 and the first etching stopper film left at the bottom of the contact hole CH are subjected to an etching process by changing the above etching conditions. 21 are removed by etching in order to form contact holes CH for exposing the source / drain diffusion layers 12.

Next, an adhesion layer 34a, a wiring layer 34b, and a barrier metal layer 34c are laminated on the entire surface of the source / drain diffusion layer 12 exposed in the contact hole by, for example, a sputtering method to form a pattern. By processing, an upper wiring 34 connected to the source / drain diffusion layer 12 is formed. Thus, the semiconductor device illustrated in FIG. 14 can be formed.

[0031]

However, in the above-described method of manufacturing a semiconductor device having a contact connection by SAC, the etching conditions for opening the contact hole CH for exposing the second etching stopper film 22 by the etching process are as follows. When etching the interlayer insulating film made of BPSG with respect to the second etching stopper film 22 made of silicon nitride, a high selectivity of about 15 is required (particularly, a high selectivity is required in a portion covering the shoulder portion of the gate electrode 32). On the other hand, it is very difficult to manage a selectivity of about 15 in a mass production line, so that the above method is very difficult to put into practical use.

As shown in FIG. 20A, the offset insulating film 21 and the sidewall insulating film 27 serving as LDD spacers are both formed of silicon nitride, and the interlayer insulating film 23 is formed of silicon oxide (eg, BPSG). 20B, the contact hole CH is opened in the interlayer insulating film 23 with a selectivity with respect to the offset insulating film 21 and the sidewall insulating film 27, as shown in FIG. Although the condition for the selectivity is relaxed, the contact hole is opened without removing the sidewall insulating film serving as the LDD spacer, particularly when the distance between the gate electrodes is reduced. Becomes smaller toward the bottom, CF
An extreme microloading effect called “etch stop” may be caused by system deposits, and the opening of the contact hole may not be possible. In order to avoid this phenomenon, it is necessary to perform a process of forming sidewalls serving as LDD spacers using polysilicon or the like and removing source / drain diffusion layers having an LDD structure after forming the sidewalls as in the above-described method.

The present invention has been made in view of the above circumstances. Therefore, the present invention provides a method of removing a sidewall serving as an LDD spacer by lowering a necessary selection ratio and forming a contact hole in a self-aligned manner. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be opened.

[0034]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a conductive layer on a semiconductor substrate and forming an offset insulating film on the conductive layer. A step of performing ion implantation using the offset insulating film as a mask to form a low-concentration impurity-containing region containing conductive impurities at a low concentration in the semiconductor substrate; and covering the offset insulating film and the conductive layer. Forming an etching stopper film, forming a sidewall mask layer on the etching stopper film in opposition to a sidewall surface of the offset insulating film and the conductive layer, and masking the sidewall mask layer. Ion implantation is performed, and a high concentration of conductive impurities is contained in the semiconductor substrate to connect to the low concentration impurity-containing region. Forming an impurity-containing region,
Removing the sidewall mask layer with an etching selectivity to the etching stopper film;
Forming a first insulating film over the entire surface of the etching stopper film; opening a contact hole exposing the high-concentration impurity-containing region in the etching stopper film and the first insulating film; Forming a second insulating film on the inner wall surface of the substrate, and forming a buried electrode connected to the high-concentration impurity-containing region by filling the contact hole with a conductor.

The method of manufacturing a semiconductor device according to the present invention described above includes:
A conductive layer is formed on a semiconductor substrate, an offset insulating film is formed over the conductive layer, ions are implanted using the offset insulating film as a mask, and a low-concentration impurity-containing region containing conductive impurities at a low concentration in the semiconductor substrate. Forming an etching stopper film by covering the offset insulating film and the conductive layer; forming a sidewall mask layer on the etching stopper film so as to face the side wall surface of the offset insulating film and the conductive layer; Ion implantation is performed by using the mask layer as a mask to form a high-concentration impurity-containing region in the semiconductor substrate which contains conductive impurities at a high concentration and is connected to the low-concentration impurity-containing region. Next, the sidewall mask layer is removed with an etching selectivity to the etching stopper film, a first insulating film is formed on the entire surface of the etching stopper film, and a contact hole exposing the high-concentration impurity-containing region is etched. Openings are formed in the stopper film and the first insulating film. Next, a second insulating film is formed on the inner wall surface of the contact hole, and the inside of the contact hole is filled with a conductor to form a buried electrode connected to the high-concentration impurity-containing region.

According to the method of manufacturing a semiconductor device of the present invention described above, in the method of removing a sidewall serving as an LDD spacer, a contact hole exposing a high-concentration impurity-containing region is formed in an etching stopper film and a first insulating film. After that, a second insulating film is formed again on the inner wall surface of the contact hole. Thereby, even if the opening pattern of the contact hole is shifted and the conductive layer is exposed in the contact hole, the conductive layer can be covered with the second insulating film, and the buried electrode and the conductive layer formed in the contact hole can be covered. It is possible to form a contact connection in a self-aligned manner by securing insulation (withstand voltage) from the contact. For this reason, at the time of opening the contact hole, the etching selectivity of silicon oxide to silicon nitride of about 10 is sufficient, and the etching selectivity required at the time of opening the contact hole can be made lower than before.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, the step of forming the second insulating film includes the steps of: covering an inner wall surface of the contact hole and the exposed high-concentration impurity-containing region, and depositing an insulator on a front surface; Leaving the upper part of the inner wall of
Removing the insulator while exposing the high-concentration impurity-containing region. Thereby, the second insulating film covering the inner wall surface of the contact hole can be obtained.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the second insulating film,
It is formed using a stacked body of silicon oxide and silicon nitride.
Alternatively, it is preferably formed of silicon oxide. Alternatively, preferably, the method further includes, before the step of forming the etching stopper film, a step of oxidizing a side wall surface of the conductive layer, and the step of forming the second insulating film is made of silicon nitride. Thereby, even if the conductive layer is exposed in the contact hole, the conductive layer can be covered to form a second insulating film that can secure insulation from the embedded wiring formed in the contact hole.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the step of forming the offset insulating film is made of silicon nitride. This makes it possible to use the offset insulating film as a mask that prevents the shoulder of the conductive layer from being etched even when the conductive layer is exposed when the contact hole is opened.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the step of forming the sidewall mask layer includes a step of forming a sidewall mask layer over the entire surface of the etching stopper film and a step of opposing a sidewall surface of the offset insulating film and the first conductive layer. And etching back the entire surface of the sidewall mask layer while leaving a portion of the sidewall mask layer. Thereby, a sidewall mask layer can be formed at a position facing the side wall surface of the offset insulating film and the conductive layer.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, before the step of forming a conductive layer on the semiconductor substrate, further comprising a step of forming a channel formation region in the semiconductor substrate, and a step of forming a gate insulating film on the semiconductor substrate, The step of forming a conductive layer on a semiconductor substrate is a step of forming a conductive layer on the gate insulating film, and a field effect transistor using the conductive layer as a gate electrode is formed. From a gate insulating film, a conductive layer (gate electrode) above the channel formation region, and a low-concentration impurity-containing region (LDD diffusion layer) and a high-concentration impurity-containing region (source / drain diffusion layer) connected to the channel formation region,
A field effect MOS transistor can be formed.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

The semiconductor device of the present embodiment has an SRAM (Static Random Acce
ss Memory). FIG. 1 is an equivalent circuit diagram of one memory cell of the SRAM. Word transistors Tr1 and T, which are NMOS gates controlled by word lines WL
r2 has one of the source / drain electrodes connected to the bit lines BL, B
L , the other source / drain electrode is a storage node A (n
node A) and the storage node B (node B). The storage node A is connected to the ground GND via a driver transistor Tr3 which is an NMOS, and further connected to a power supply voltage supply line Vcc via a load transistor Tr5 which is a PMOS. The storage node B is a driver transistor Tr which is an NMOS.
4 and to the power supply voltage supply line Vcc via a load transistor Tr6 which is a PMOS. The storage node A is connected to the gate electrodes of the driver transistor Tr4 and the load transistor Tr6, while the storage node B is connected to the gate electrodes of the driver transistor Tr3 and the load transistor Tr5. Thus, a circuit configuration called a flip-flop is formed.

FIG. 2 is a plan view of one memory cell of the SRAM. In the figure, hatched portions are gate electrodes, and shaded regions on both sides thereof indicate source / drain regions S / D. A word transistor Tr1 is connected to the word line WL.
Tr2 is formed, and a driver transistor Tr3 and a load transistor Tr5 are formed on the gate electrode G1.
Further, an extension of the gate electrode G1 is connected to a source / drain region connecting the word transistor Tr2 and the driver transistor Tr4 via the shared contact SC2. A driver transistor Tr4 and a load transistor Tr6 are formed on the gate electrode G2,
Further, the extension of the gate electrode G2 is connected to the source / drain region of the load transistor Tr5 via the shared contact SC1. In the figure, SAC1 to 8 are self-aligned contacts, SAC1 and 2 are connected to a power supply voltage line, SAC3 and 4 are connected to ground, SAC5 and 6 are connected to bit lines, SAC7 is connected to SC1, and SAC8 is connected to SC2. It is formed. Here, the portion indicated by Z in FIG. 1 corresponds to the gate electrode G2 in FIG. Here, one bit is displayed on the plan view. Actually, however, the basic cells are turned upside down in the drawing and arranged, for example, 4M cells are developed in units of two cells.

The write operation of the above SRAM will be described. For example, when the input data Din “0” is given, the bit line BL becomes “0”, the bit line BL becomes “1”, and when the word line WL becomes high, the word transistors Tr1 and Tr2 are turned on. At this time, the bit line
NodeA from BL through word transistor Tr1
Is transferred to "1". On the other hand, since the bit line BL is at 0 V, node B is output through the speech transistor Tr2.
, And the node B becomes “0”.

As described above, when the node A becomes "1", the gate electrodes of the driver transistor Tr4 and the load transistor Tr6 become "1", the load transistor Tr6 is turned off, and the driver transistor Tr4 is turned on. When nodeB becomes “0”, the gate electrodes of the driver transistor Tr3 and the load transistor Tr5 become “0”, and the load transistor Tr5
Turns on, and the driver transistor Tr3 turns off. Therefore, the node A is charged from the power supply voltage supply line Vcc through the load transistor Tr5. nod
e B is grounded GN through driver transistor Tr4
Connected to G and becomes "0".

After the writing, when the word line WL becomes "0" and the word transistors Tr1 and Tr2 are turned off, the nodes A and B become the bit lines BL and
The data separated and written from BL is stored (stored) as long as Vcc is applied by the flip-flop.

The read operation of the above SRAM will be described. It is assumed that data is written and stored as data as described above. When the word line WL is set to "1" and the word transistors Tr1 and Tr2 are turned on, no current flows between the bit line BL and the node A of the cell, while Tr2 in the cell flows from the bit line BL.
A current flows to GND through Tr4, and the potential of the bit line BL decreases. At this time, the potential difference between the bit lines BL, BL is sense-amplified and output to the I / O terminal.

The method of opening the self-aligned contact SAC used in the above semiconductor device will be described with reference to FIGS.
This will be described in detail with reference to FIG.

FIG. 3 is a sectional view of a semiconductor device in which the above-described self-aligned contact is opened. In an active region of the silicon semiconductor substrate 10 having a channel formation region separated by an element isolation insulating film (not shown), the semiconductor substrate 10
In the upper layer, a gate electrode 32 having a polycide structure including a lower gate electrode 31 of polysilicon and an upper gate electrode 31 of tungsten silicide is formed via a gate insulating film 20. In the semiconductor substrate 10 on both sides of the gate electrode 32, an LDD (Lightly Doped Drain) diffusion layer 11 containing a low concentration of conductive impurities and a source / drain diffusion layer 12 containing a high concentration of a conductive impurity are formed. Thus, a transistor having an LDD structure is formed. An offset insulating film 21 of silicon nitride is formed on the upper layer of the gate electrode 32, and an etching stopper film 22 of, for example, silicon oxide is formed to cover the gate electrode 32 and the offset insulating film 21. A first interlayer insulating film 23 of silicon oxide is formed.

A contact hole CH reaching the source / drain diffusion layer 12 is opened in the first interlayer insulating film 23 and the etching stopper film 22, and a silicon oxide film 24a and a silicon nitride film 25a are formed on the inner wall surface of the hole.
The contact layer 34a, the wiring layer 34b, and the barrier metal layer 34c are laminated and patterned so as to cover and bury the inside of the contact hole. Thus, an upper wiring 34 is formed.

Here, in the above-mentioned semiconductor device, although the opening position of the contact hole is shifted to the right in the drawing, the silicon oxide film 2 is formed on the inner wall surface of the contact hole CH.
The gate electrode 32 is not exposed in the contact hole CH because the second interlayer insulating film made of a stacked body of the silicon nitride film 4a and the silicon nitride film 25a is formed. A contact connection is formed.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 4A, an element isolation insulating film (not shown) is formed on the silicon semiconductor substrate 10, and a channel impurity (not shown) is introduced into an active region separated by the element isolation insulating film. For example, the gate insulating film 20 is formed by a thermal oxidation method, and an upper layer thereof is formed by, for example, a CVD method.
125 nm thick polysilicon film 30a, 100 nm
A tungsten silicide film 31a having a thickness of is deposited. Next, for example, TEOS (tetra-ethyl-or
thosilicate) as a raw material by low pressure CVD
Offset insulating film 2 made of silicon oxide with a thickness of nm
1a is deposited. Next, a resist film R1 having a gate electrode pattern is formed on the offset insulating film 21a by a photolithography process.

Next, as shown in FIG. 4B, an etching treatment such as RIE (reactive ion etching) is performed using the resist film R1 as a mask, and the polysilicon film 30 is formed.
a, a tungsten silicide film 31a and an offset insulating film 21a are patterned to form a gate electrode 32 having an offset insulating film 21 having a polycide structure including a lower gate electrode 30 of polysilicon and an upper gate electrode 31 of tungsten silicide. Form. After that, the resist film R1 is removed.

Next, as shown in FIG. 4C, the conductive impurity D1 is ion-implanted into the semiconductor substrate 10 using the offset insulating film 21 as a mask, and the LDD diffusion layer is self-aligned with the gate electrode 32. 11 is formed.

Next, as shown in FIG. 5D, the entire surface is covered with the gate electrode 32 and the offset insulating film 21.
For example, 30n by a low pressure CVD method using TEOS as a raw material.
An etching stopper film 22 is formed by depositing a silicon oxide film with a thickness of m.

Next, as shown in FIG.
Polysilicon or amorphous silicon containing phosphorus is deposited in a thickness of 90 nm by a VD method to form a sidewall mask layer 33, and then, as shown in FIG. To form a sidewall mask layer 33a.

Next, as shown in FIG. 6G, using the sidewall mask layer 33a as a mask, the conductive impurity D2 is ion-implanted into the semiconductor substrate 10 to form the source / drain diffusion layer 12. Thus, the source / drain region having the LDD structure can be obtained. At this time, the width of the sidewall mask layer 33a becomes the LDD width, that is, the sidewall mask layer 33a becomes an LDD spacer.

Next, as shown in FIG. 6 (h), etching is performed under a condition of removing the sidewall mask layer 33a of polysilicon or amorphous silicon with a selectivity to the etching stopper film 22 of silicon oxide. The sidewall mask layer 33a is removed by, for example, a downflow type plasma etching.

Next, as shown in FIG.
Silicon oxide (BPSG) containing boron and phosphorus is deposited by a CVD method using ₃ and TEOS as raw materials, and if necessary, reflow, etchback or CM
A first interlayer insulating film 23 is formed by performing a flattening process such as P (Chemical Mechanical Polishing). Here, the total thickness T of the first interlayer insulating film 23 and the etching stopper film 22 is, for example, 500 nm.

Next, as shown in FIG. 7J, a resist film R2 having a contact hole opening pattern is formed on the first interlayer insulating film 23 by a photolithography process. Here, the drawing shows that a resist film R2 having an opening diameter Q of a contact hole of about 340 nm corresponds to an interval S of the gate electrode 32 of about 470 nm by 1 in the R direction.
The case where the pattern is formed with a shift of 20 nm is shown.

Next, as shown in FIG.
A contact hole CH for exposing the source / drain diffusion layer 12 is opened by an etching process such as a CR type plasma etching. At this time, since the resist film R2 is formed shifted as described above, the gate electrode 32 is formed.
Is exposed, but since the silicon nitride offset insulating film 21 is formed thereover, the shoulder of the gate electrode 32 can be prevented from being etched.
Here, for example, the opening of the contact hole is slightly tapered (a forward tapered shape narrowing toward the substrate side, a taper angle θ).
= 86 °) and the opening diameter Q ′ at the bottom of the contact hole can be about 250 nm.

Next, as shown in FIG.
A silicon oxide film 24 having a thickness of 10 nm is deposited on the entire surface by covering the inner wall of the contact hole CH by a low pressure CVD method using EOS as a raw material, and further, as shown in FIG. A silicon nitride film 25 is deposited on the entire surface by covering the upper layer of the silicon film 24, and a second interlayer insulating film made of a laminate of the silicon oxide film 24 and the silicon nitride film 25 is formed. Here, the second interlayer insulating film is formed as a stacked body of the silicon oxide film and the silicon nitride film in order to prevent the gate electrode 32 exposed in the contact hole CH from coming into direct contact with the silicon nitride film. For example, the second interlayer insulating film may be a single layer of silicon oxide. Further, the gate electrode 3
By forming an oxide film on the side wall portion of the second layer, the second interlayer insulating film of a single layer of silicon nitride can be used.

Next, as shown in FIG. 8 (n), an etching process such as RIE is performed to remove the second interlayer insulating films (24, 25) formed at the bottoms of the contact holes. Then, the source / drain diffusion layer 12 is exposed again. The opening diameter Q ″ at this time is, for example, 15
It is about 0 nm.

Next, an adhesion layer 34a, a wiring layer 34b, and a barrier metal layer 34c are laminated on the entire surface of the source / drain diffusion layer 12 exposed in the contact hole by, for example, a sputtering method to form a pattern. By processing, an upper wiring 34 connected to the source / drain diffusion layer 12 is formed. Thus, the semiconductor device illustrated in FIG. 3 can be formed.

According to the method of manufacturing a semiconductor device of the present embodiment, in the method of removing the sidewalls serving as the LDD spacer, the contact hole CH exposing the source / drain diffusion layer is formed by etching the etching stopper film 22 and the first interlayer. After the opening in the insulating film 23, the second interlayer insulating film (24, 2) is formed on the inner wall surface of the contact hole CH again.
Since 5) is formed, even if the opening pattern of the contact hole is shifted and the gate electrode 32 is exposed in the contact hole CH, the second interlayer insulating film (24, 25) is formed.
Accordingly, the gate electrode 32 can be covered, and insulation (withstand voltage) between the buried electrode formed in the contact hole and the gate electrode 32 can be ensured, and a contact connection can be formed in a self-aligned manner. For this reason, at the time of opening the contact hole, the etching selectivity of silicon oxide to silicon nitride of about 10 is sufficient, and the etching selectivity required at the time of opening the contact hole can be made lower than before.

Further, by forming the offset insulating film of silicon nitride, it is possible to make the offset insulating film thinner than in the prior art. It is advantageous. Further, since the stress applied to the substrate is reduced as compared with the conventional case where the silicon nitride film covers the entire surface, there is no concern about introduction of defects into the substrate. Further, in the etch-back step of forming the sidewall mask layer serving as the LDD spacer, it is possible to prevent the element isolation insulating film such as the LOCOS film from being etched.

The present invention relates to a method for contacting a region between narrow conductive layers formed on a semiconductor substrate, such as a semiconductor device of a MOS transistor such as a DRAM, a bipolar semiconductor device, or an A / D converter. The method can be applied to any method of manufacturing a semiconductor device that forms holes, and is particularly preferably applied to a method of manufacturing a semiconductor device having a field-effect MOS transistor having the above-described conductive layer as a gate electrode, such as an SRAM or a DRAM. it can.
Also. As the SRAM, in addition to the CMOS type SRAM,
CM using high resistance element type SRAM or TFT
It can be applied to the SRAM of the OS.

The present invention is not limited to the above embodiment. For example, the second interlayer insulating film formed by covering the inner wall of the contact hole may have a single-layer structure or a multilayer structure.
In the case of a single layer structure, a single layer of silicon oxide or a single layer of silicon nitride may be used. Each of the side wall mask layers may be a single layer, or may have a multilayer structure or more. Also,
The conductive layer such as the gate electrode may be a single layer or a multilayer. The etching stopper film can be formed of silicon nitride or the like in addition to silicon oxide. In addition, various changes can be made without departing from the spirit of the present invention.

[0070]

According to the present invention, in a method of removing a sidewall serving as an LDD spacer, there is provided a method of manufacturing a semiconductor device in which a required selectivity can be reduced and a contact hole can be opened in a self-aligned manner. can do.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment.

FIG. 2 is a plan view of the semiconductor device according to the embodiment;

FIG. 3 is a cross-sectional view of the semiconductor device for explaining a contact hole opening method of the semiconductor device according to the embodiment;

4A to 4C are cross-sectional views illustrating a manufacturing process of the method for manufacturing the semiconductor device illustrated in FIG. 3; FIG. 4A illustrates a process up to a resist film process of a gate pattern; FIG. (C) shows up to the step of forming the LDD diffusion layer.

FIG. 5 is a sectional view showing a step that follows the step in FIG. 4;
(D) shows the process up to the step of forming the etching stopper film;
4A shows up to the step of forming the sidewall mask layer, and FIG. 4F shows the steps up to the step of forming the sidewall mask layer.

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;
(G) shows the steps up to the step of forming the source / drain diffusion layers.
(H) shows the process up to the step of removing the sidewall mask layer.
(I) shows up to the step of forming the first interlayer insulating film.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(J) shows up to the step of forming a resist film of a contact opening pattern, and (k) shows up to the step of opening a contact hole.

FIG. 8 is a sectional view showing a step subsequent to that of FIG. 7;
(L) until the step of forming a silicon oxide film (second interlayer insulating film), (m) until the step of forming a silicon nitride film (second interlayer insulating film), and (n) the second interlayer insulating film at the bottom of the contact hole. The steps up to the step of removing the film are shown.

FIG. 9 is an equivalent circuit diagram of a semiconductor device according to a first conventional example.

FIG. 10 is a plan view of a semiconductor device according to a first conventional example.

FIG. 11 is a sectional view taken along a line AB in FIG. 9;

FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 11, which shows a process up to the step of forming a source / drain diffusion layer.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 11 and shows a process up to the step of forming an interlayer insulating film;

FIG. 14 is a cross-sectional view of the semiconductor device for explaining a method of forming a contact hole in the semiconductor device according to the first conventional example.

15A and 15B are cross-sectional views illustrating a manufacturing process of the method for manufacturing the semiconductor device illustrated in FIG. 14; FIG. 15A illustrates a process up to a resist film process of a gate pattern; FIG. (C) shows up to the step of forming the LDD diffusion layer.

16 is a cross-sectional view showing a step that follows the step shown in FIG. 15; FIG. 16 (d) shows up to the step of forming a first etching stopper film; FIG. 16 (e) shows up to the step of forming a sidewall mask layer; ) Shows the steps up to the step of forming the sidewall mask layer.

17 is a cross-sectional view showing a step subsequent to that of FIG. 16; FIG. 17 (g) shows up to a step of forming a source / drain diffusion layer; FIG. 17 (h) shows a step up to a step of removing a sidewall mask layer;
(I) shows up to the step of forming the second etching stopper film.

18 is a cross-sectional view showing a step subsequent to that of FIG. 17; (j) shows up to a step of forming an interlayer insulating film; and (k) shows a step up to a step of forming a resist film of a contact opening pattern.

19 is a cross-sectional view showing a step subsequent to that of FIG. 18; (l) shows a step of opening a contact hole exposing a second etching stopper film; and (m) shows a second etching of the bottom of the contact hole. The steps up to the step of removing the stopper film and the first etching stopper film are shown.

FIGS. 20A and 20B are cross-sectional views showing a manufacturing process of a method of manufacturing a semiconductor device according to a second conventional example, in which FIG. 20A shows up to a step of forming an interlayer insulating film, and FIG. Is shown.

[Explanation of symbols]

10 semiconductor substrate, 11 LDD diffusion layer, 12 source / drain diffusion layer, 13 LOCOS element isolation insulating film,
20: gate insulating film, 21: offset insulating film, 22 ...
(First) etching stopper film, 23 (first) interlayer insulating film, 24, 24a ... silicon oxide film, 25, 25a ...
Silicon nitride film, 26 ... second etching stopper film, 3
0: Lower gate electrode, 31: Upper gate electrode, 32: Gate electrode, 33: Layer for sidewall mask, 33a ...
Sidewall mask layer, 34a: adhesion layer, 34b: wiring layer, 34c: barrier metal layer, 34: upper wiring, Tr
1 to 6: transistors, WL: word lines, BL, BL ...
Bit line, Vcc: power supply voltage supply line, GND: ground, SAC: self-aligned contact, SC: shared contact, D1, D2: conductive impurities, R1, R2: resist film, CH: contact hole.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 27/11 F term (Reference) 4M104 AA01 BB01 CC01 DD04 DD08 DD16 DD17 DD19 DD26 EE12 EE15 EE17 FF13 FF14 FF16 GG09 GG15 GG16 HH14 5F033 NN12 5F048 AB01 BC06 BF16 5F083 BS05 MA03 MA19 PR03 PR10 PR29

Claims (8)

[Claims] A step of forming a conductive layer on the semiconductor substrate; a step of forming an offset insulating film on the conductive layer; and performing ion implantation using the offset insulating film as a mask to form a conductive layer in the semiconductor substrate. A step of forming a low-concentration impurity-containing region containing impurities at a low concentration; a step of covering the offset insulating film and the conductive layer to form an etching stopper film; a side wall surface of the offset insulating film and the conductive layer Forming a sidewall mask layer on the etching stopper film in opposition to the above, and performing ion implantation using the sidewall mask layer as a mask, containing a high concentration of conductive impurities in the semiconductor substrate, Forming a high-concentration impurity-containing region connected to the low-concentration impurity-containing region; Removing the sidewall mask layer with an etching selectivity, forming a first insulating film over the entire surface of the etching stopper film, and forming a contact hole exposing the high-concentration impurity-containing region. Forming an opening in an etching stopper film and the first insulating film; forming a second insulating film on an inner wall surface of the contact hole; filling the contact hole with a conductor to form a high-concentration impurity-containing region; Forming a buried electrode to be connected. 2. The step of forming the second insulating film, the steps of: covering an inner wall surface of the contact hole and the exposed high-concentration impurity-containing region, and depositing an insulator on a front surface; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising removing the insulator while exposing the high-concentration impurity-containing region while leaving a portion on the inner wall surface of the hole. 3. The method according to claim 1, wherein in the step of forming the second insulating film, the second insulating film is formed of a laminate of silicon oxide and silicon nitride. 4. The method according to claim 1, wherein in the step of forming the second insulating film, the second insulating film is formed of silicon oxide. 5. The method according to claim 1, further comprising, before the step of forming the etching stopper film, a step of oxidizing a side wall surface of the conductive layer, and the step of forming the second insulating film is made of silicon nitride. Item 2. A method for manufacturing a semiconductor device according to Item 1. 6. The method according to claim 1, wherein the step of forming the offset insulating film is performed by using silicon nitride. 7. The step of forming the sidewall mask layer includes: forming a sidewall mask layer over the entire surface of the etching stopper film; and forming side walls of the offset insulating film and the first conductive layer. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: etching back the entire surface of the sidewall mask layer while leaving an opposite portion of the sidewall mask layer. 3. 8. A semiconductor device further comprising: before forming a conductive layer on the semiconductor substrate, forming a channel formation region on the semiconductor substrate, and forming a gate insulating film on the semiconductor substrate. 2. The manufacturing of a semiconductor device according to claim 1, wherein the step of forming a conductive layer on the semiconductor substrate is a step of forming a conductive layer on the gate insulating film, and forming a field-effect transistor using the conductive layer as a gate electrode. Method.