JP2009246374A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of increasing performance of a semiconductor device including a memory element and a logic element consolidated therein. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1; an insulating layer 19 on the semiconductor substrate 1; a plurality of contact plugs 16 and 66 in the insulating layer 19; an insulating layer 30; and a capacitor 82, a plurality of contact plugs 25 and 75, barrier metal layers 27 and 87, and copper interconnect lines 29 and 88 provided in the insulating layer 30. Source and drain regions 9 in the top surface of the semiconductor substrate 1 are electrically connected to copper interconnect lines 29. Furthermore, one of source and drain regions 59 in a top surface of the semiconductor substrate 1 is electrically connected to the copper interconnect line 88. Then, the other of the source and drain regions 59 is electrically connected to the capacitor 82. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory / logic mixed type semiconductor device in which a memory device and a logic device are formed on a semiconductor substrate.

  39 to 51 are cross-sectional views showing a conventional manufacturing method of a mixed memory / logic semiconductor device in the order of steps. In a conventional memory / logic mixed semiconductor device, a DRAM having a memory cell with a CUB (Capacitor Under Bit line) structure is adopted as a memory device, and a dual gate salicide CMOS transistor is adopted as a logic device, for example. The

  First, as shown in FIG. 39, the element isolation insulating film 2 is formed in the upper surface of the semiconductor substrate 1 which is an n-type silicon substrate, for example, by a well-known LOCOS isolation technique or trench isolation technique. Then, p-type well regions 3 and 53 and an n-type well region 54 are formed in the upper surface of the semiconductor substrate 1. Specifically, a well region 53 is formed in the upper surface of the semiconductor substrate 1 in a region where a memory device is formed (hereinafter referred to as “memory formation region”), and a well region 54 is formed at the bottom thereof. Further, a well region 3 is formed in the upper surface of the semiconductor substrate 1 in a region where a logic device is formed (hereinafter referred to as “logic formation region”). Then, channel implantation is performed.

  Next, a plurality of gate structures 61 that form a predetermined distance from each other are formed on the semiconductor substrate 1 in the memory formation region. Each gate structure 61 includes, in this order, a gate insulating film 55 employing a silicon oxide film, a gate electrode 56 employing a polycrystalline silicon film, and a silicon oxide film 57 employing a TEOS film, for example. It has a laminated structure. In addition, a plurality of gate structures 11 are formed on the semiconductor substrate 1 in the logic formation region so as to form a predetermined distance from each other. Each gate structure 11 includes, in this order, a gate insulating film 5 employing a silicon oxide film, a gate electrode 6 employing a polycrystalline silicon film, and a silicon oxide film 7 employing a TEOS film, for example. It has a laminated structure.

Then, using the gate structures 11 and 61 and the element isolation insulating film 2 as a mask, impurities such as phosphorus and arsenic are ion-implanted into the upper surface of the semiconductor substrate 1 at a relatively low concentration. As a result, an n ⁻ type impurity region 58a is formed in the upper surface of the semiconductor substrate 1 in the memory formation region, and an n ⁻ type impurity region 8a is formed in the upper surface of the semiconductor substrate 1 in the logic formation region. The

  Next, as shown in FIG. 40, for example, after a silicon nitride film is formed on the entire surface by CVD, the silicon nitride film is etched by anisotropic dry etching with a high etching rate in the depth direction of the semiconductor substrate 1. . As a result, the sidewall 60 is formed on the side surface of the gate structure 61, and the sidewall 10 is formed on the side surface of the gate structure 11.

Then, impurities such as phosphorus and arsenic are ion-implanted into the upper surface of the semiconductor substrate 1 at a relatively high concentration using the gate structures 11 and 61, the element isolation insulating film 2 and the sidewalls 10 and 60 as a mask. As a result, an n ⁺ -type impurity region 58b is formed in the upper surface of the semiconductor substrate 1 in the memory formation region, and an n ⁺ -type impurity region 8b is formed in the upper surface of the semiconductor substrate 1 in the logic formation region. The

  Through the above steps, a plurality of source / drain regions 59 each consisting of impurity regions 58a, 58b and having a predetermined distance from each other are formed in the upper surface of the semiconductor substrate 1 in the memory formation region, and further, adjacent source / drain regions 59 are formed. A gate structure 61 is formed on the upper surface of the semiconductor substrate 1 between the drain regions 59. A plurality of source / drain regions 9 each consisting of impurity regions 8a and 8b and having a predetermined distance from each other are formed in the upper surface of the semiconductor substrate 1 in the logic formation region. A gate structure 11 is formed on the upper surface of the semiconductor substrate 1 therebetween.

  The impurity regions 8b and 58b are formed deeper than the impurity regions 8a and 58a for the following reason. That is, when a cobalt silicide film 12 to be described later is formed on the semiconductor substrate 1, the cobalt silicide film 12 may be partially formed deeply, and the electrical connection between the cobalt silicide film 12 and the well regions 3 and 53 may occur. In order to avoid connection, impurity regions 8b and 58b are formed deeper than impurity regions 8a and 58a. At this time, if the concentration of the impurity region 58b is too high, a leakage current in the channel direction increases, which may deteriorate the charge retention characteristics (also referred to as “refresh characteristics”) of the memory device. In order to prevent such deterioration, the concentration of the impurity region 58b in the memory formation region is set lower than that of the impurity region 8b in the logic formation region.

  Next, as shown in FIG. 41, the silicon oxide film 57 of the gate structure 61 and the silicon oxide film 7 of the gate structure 11 are removed using, for example, hydrofluoric acid.

  Next, a cobalt film is formed on the entire surface by, eg, sputtering. Then, for example, by performing a heat treatment using a lamp annealing apparatus, cobalt is reacted with silicon in contact therewith. As a result, as shown in FIG. 42, the upper surface of the semiconductor substrate 1 is partially silicided, and a cobalt silicide film 12 is formed on the source / drain regions 9 and 59. At the same time, the upper surfaces of the gate electrodes 6 and 56 are silicided to form the cobalt silicide film 12. As a result, a gate structure 11 having the cobalt silicide film 12 on the gate electrode 6 and a gate structure 61 having the cobalt silicide film 12 on the gate electrode 56 are formed. Thereafter, the unreacted cobalt film is removed.

  Next, as shown in FIG. 43, an insulating layer 19 composed of the stopper film 13 and the interlayer insulating film 14 is formed on the semiconductor substrate 1 so as to cover the gate structures 11 and 61. Specifically, the stopper film 13 is formed on the entire surface, and then the interlayer insulating film 14 is formed on the stopper film 13. Then, the interlayer insulating film 14 is planarized by a CMP method or the like. Thereby, the insulating layer 19 having a flat upper surface is formed on the semiconductor substrate 1. For example, a silicon nitride film is used as the stopper film 13, and a BPTEOS film is used as the interlayer insulating film 14, for example.

  Next, as shown in FIG. 44, contact plugs 16 and 66 are formed in the insulating layer 19. The contact plug 16 is electrically connected to the semiconductor substrate 1 in the logic formation region via the cobalt silicide film 12, and the upper surface is exposed from the interlayer insulating film 14 of the insulating layer 19. The contact plug 66 is electrically connected to the semiconductor substrate 1 in the memory formation region through the cobalt silicide film 12, and the upper surface is exposed from the interlayer insulating film 14 of the insulating layer 19. A method for manufacturing the contact plugs 16 and 66 will be specifically described below.

  First, a contact hole 65 reaching the cobalt silicide film 12 on the semiconductor substrate 1 in the memory formation region and a contact hole 15 reaching the cobalt silicide film 12 on the semiconductor substrate 1 in the logic formation region are formed in the insulating layer 19.

When the contact holes 15 and 65 are formed, first, a photoresist (not shown) having a predetermined opening pattern is formed on the interlayer insulating film 14 of the insulating layer 19 by photolithography. Then, using the photoresist as a mask, the interlayer insulating film 14 is removed by etching using the stopper film 13 as an etching stopper. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. Then, the photoresist is removed, and the exposed stopper film 13 is removed by etching. In this etching, anisotropic dry etching using a mixed gas of CHF ₃ , O ₂ and Ar is employed. As a result, the contact hole 15 positioned above the source / drain region 9 while being positioned on the side of the gate electrode 6 and the source / drain region 59 positioned on the side of the gate electrode 56 are positioned. Contact holes 65 are formed in the insulating layer 19 in the logic formation region and the memory formation region, respectively.

  Next, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium or tungsten is formed on the entire surface. Then, the stacked film on the upper surface of the insulating layer 19 is removed by CMP. As a result, the contact plug 16 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 15, and the contact plug 66 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 65. Is formed. As a result, the source / drain region 59 and the contact plug 66 are electrically connected, and the source / drain region 9 and the contact plug 16 are electrically connected. Although not shown, a contact plug that is electrically connected to the gate electrode 56 or the gate electrode 6 through the cobalt silicide film 12 is also formed in the insulating layer 19.

  Next, as shown in FIG. 45, an insulating layer 20 including a stopper film 17 and an interlayer insulating film 18 is formed on the entire surface. Specifically, first, a stopper film 17 employing, for example, a silicon nitride film is formed on the entire surface. Then, an interlayer insulating film 18 is formed on the stopper film 17. Thereby, the insulating layer 20 is provided on the insulating layer 19 and the contact plugs 16 and 66. For example, a BPTEOS film is employed as the interlayer insulating film 18.

  Next, as shown in FIG. 46, an opening 69 exposing a part of the plurality of contact plugs 66, specifically, the contact plug 66 electrically connected to one of the adjacent source / drain regions 59 is formed. It is formed in the insulating layer 20.

When forming the opening 69, first, a photoresist (not shown) having a predetermined opening pattern is formed on the interlayer insulating film 18 of the insulating layer 20, and the photoresist is used as a mask to form a stopper film. The interlayer insulating film 18 is removed by etching using 17 as an etching stopper. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. Then, the photoresist is removed, and the exposed stopper film 17 is removed by etching. In this etching, anisotropic dry etching using a mixed gas of CHF ₃ , O ₂ and Ar is employed. Thereby, the opening 69 is formed in the insulating layer 20.

  Next, a capacitor of a DRAM memory cell that contacts the exposed contact plug 66 is formed in the opening 69. Specifically, first, a metal film containing a refractory metal such as ruthenium is formed on the entire surface. Then, the opening 69 is covered with a photoresist (not shown), and the metal film on the upper surface of the interlayer insulating film 18 is removed by anisotropic dry etching. As a result, as shown in FIG. 47, the lower electrode 70 of the capacitor containing a refractory metal such as ruthenium is formed in the opening 69. Although the metal film on the upper surface of the interlayer insulating film 18 is removed by anisotropic dry etching, the metal film may be removed using a CMP method.

  Next, an insulating film made of tantalum pentoxide and a metal film containing a refractory metal such as ruthenium are laminated in this order, and then patterned using a photoresist. Thus, as shown in FIG. 48, the dielectric film 71 of the capacitor made of tantalum pentoxide and the upper electrode 72 of the capacitor containing a refractory metal such as ruthenium are formed, and the capacitor is completed in the opening 69. .

  Next, as shown in FIG. 49, an insulating layer 23 is formed on the entire surface and planarized by a CMP method. As a result, the insulating layer 23 covering the capacitor 82 is formed on the interlayer insulating film 18 of the insulating layer 20. As the insulating layer 23, for example, a TEOS film is employed and functions as an interlayer insulating film.

  Next, contact holes 24 and 74 are formed in the insulating layers 20 and 23. The contact hole 24 reaches the contact plug 16 from the upper surface of the insulating layer 23, and the contact hole 74 reaches the contact plug 66 not in contact with the capacitor from the upper surface of the insulating layer 23.

When the contact holes 24 and 74 are formed, first, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 23, and using the photoresist as a mask, the stopper film 17 is used as an etching stopper. Then, the insulating layer 23 and the interlayer insulating film 18 are removed by etching. In this etching, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. Then, the photomask is removed, and the exposed stopper film 17 is removed by etching. In this etching, anisotropic dry etching using a mixed gas of CHF ₃ , O ₂ and Ar is employed. Thereby, contact holes 24 and 74 are formed. Although not shown, a contact hole reaching the upper electrode 72 from the upper surface of the insulating layer 23 is formed simultaneously with the contact holes 24 and 74.

  Next, as shown in FIG. 50, the contact plug 25 is composed of a barrier metal layer and a refractory metal layer and fills the contact hole 24, and is composed of a barrier metal layer and a refractory metal layer. A contact plug 75 to be filled is formed. Specifically, first, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium, tungsten or the like is formed on the entire surface with the barrier metal layer facing down. Then, the stacked film on the upper surface of the insulating layer 23 is removed by CMP. As a result, the contact plug 25 that is electrically connected to the contact plug 16 and whose upper surface is exposed from the insulating layer 23 is electrically connected to the contact plug 66 that is not in contact with the capacitor 82, and the upper surface is exposed from the insulating layer 23. Contact plugs 75 are formed in the insulating layers 20 and 23.

  Next, as shown in FIG. 51, the aluminum wiring 127 sandwiched between the titanium nitride layers 126 and 128 is formed on the insulating layer 23 by being electrically connected to the contact plug 25, and the titanium nitride layers 176 and 178. The aluminum wiring 177 sandwiched between the upper and lower portions is electrically connected to the contact plug 75 and formed on the insulating layer 23. Aluminum wiring 177 is a bit line of the DRAM memory cell.

  Through the above steps, a memory device is formed in the memory formation region, and a logic device is formed in the logic formation region.

  The above-described conventional technology is the content described in Patent Document 1.

  Further, there are Patent Documents 2 to 4 as prior art document information relating to a semiconductor device including a DRAM memory cell.

JP 2003-289131 A JP-A-8-107188 JP-A-11-307742 JP 2000-307085 A

  As described above, in the prior art, since the wiring provided in the upper layer is an aluminum wiring, it is difficult to reduce the wiring resistance of the semiconductor device. Therefore, it is difficult to improve the performance of the memory device provided in the memory formation region and the logic device provided in the logic formation region.

  Accordingly, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique that enables high performance of a memory / logic mixed type semiconductor device.

  The semiconductor device according to the present invention includes a semiconductor substrate, first and second insulating layers, first to fifth contact plugs, a capacitor, and first and second copper wirings. The semiconductor substrate has a first region where a memory device is formed and a second region where a logic device is formed. The first insulating layer is provided on the semiconductor substrate. Each of the first and second contact plugs is provided in the first insulating layer so as to be electrically connected to the semiconductor substrate in the first region while an upper surface thereof is exposed from the first insulating layer. It has been. The third contact plug is provided in the first insulating layer so as to be electrically connected to the semiconductor substrate in the second region while an upper surface of the third contact plug is exposed from the first insulating layer. . The second insulating layer is provided on the first insulating layer and the first to third contact plugs. The capacitor is electrically connected to the first contact plug and provided in the second insulating layer. The fourth and fifth contact plugs are electrically connected to the second and third contact plugs, respectively, and are respectively provided in the second insulating layer. The first and second copper wirings are electrically connected to the fourth and fifth contact plugs, respectively, and are respectively provided in the second insulating layer.

  According to the present invention, since the copper wiring is adopted as the upper layer wiring in the first and second regions, the wiring resistance can be reduced as compared with the case where the aluminum wiring is adopted as the wiring. Therefore, a memory / logic mixed type semiconductor device can be improved in performance.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention in order of a process. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the first embodiment is a memory / logic mixed type semiconductor device. As the memory device, for example, a DRAM having a CUB structure memory cell is adopted, and as the logic device, for example, Dual Gate salicide. A CMOS transistor is employed.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 1, an insulating layer 19 provided on the semiconductor substrate 1, which includes a stopper film 13 and an interlayer insulating film 14, and an insulating layer 19. A plurality of contact plugs 16, 66 provided in the insulating layer 30, an insulating layer 30 composed of the insulating layers 20, 23, 28, a capacitor 82, a plurality of contact plugs 25, 75 and a copper wiring 29 provided in the insulating layer 30. , 88.

  The semiconductor substrate 1 is, for example, an n-type silicon substrate, and an element isolation insulating film 2 is provided in the upper surface thereof. A p-type well region 3 is provided in the upper surface of the semiconductor substrate 1 in the logic formation region, and a p-type well region 53 is provided in the upper surface of the semiconductor substrate 1 in the memory formation region. . An n-type well region 54 is provided at the bottom of the well region 53.

  A plurality of source / drain regions 9 having a predetermined distance are provided in the upper surface of the well region 3, and a plurality of source / drain regions 59 having a predetermined distance are provided in the upper surface of the well region 53. It has been.

  On the semiconductor substrate 1 in the memory formation region, there are provided a plurality of gate structures 61 that form a predetermined distance from each other. Each gate structure 61 includes a gate insulating film 55 that employs, for example, a silicon oxide film, and a polycrystalline structure, for example. A gate electrode 56 employing a silicon film and a cobalt silicide film 12 are stacked in this order. Each gate structure 61 is provided on the upper surface of the semiconductor substrate 1 between adjacent source / drain regions 59, and sidewalls 60 are provided on the side surfaces thereof.

  On the semiconductor substrate 1 in the logic formation region, a plurality of gate structures 11 having a predetermined distance from each other are provided. Each gate structure 11 includes a gate insulating film 5 employing, for example, a silicon oxide film, and a polycrystalline film, for example. A gate electrode 6 employing a silicon film and a cobalt silicide film 12 are stacked in this order. Each gate structure 11 is provided on the upper surface of the semiconductor substrate 1 between the adjacent source / drain regions 9, and side walls 10 are provided on the side surfaces thereof.

  The cobalt silicide film 12 is also provided on the source / drain regions 9 and 59. The contact plug 66 has an upper surface exposed from the insulating layer 19 and is electrically connected to the semiconductor substrate 1 in the memory formation region, specifically, the source / drain region 59. Further, the upper surface of the contact plug 16 is exposed from the insulating layer 19 and is electrically connected to the semiconductor substrate 1 in the logic formation region, specifically, the source / drain region 9.

  The insulating layer 30 is provided on the insulating layer 19 and the contact plugs 16 and 66. The capacitor 82 is electrically connected to a part of the plurality of contact plugs 66, specifically, to the contact plug 66 electrically connected to one of the adjacent source / drain regions 59.

  The contact plug 25 is electrically connected to the contact plug 16, and the contact plug 75 is electrically connected to a contact plug 66 that is not electrically connected to the capacitor 82. The copper wiring 29 is electrically connected to the contact plug 25 via the barrier metal layer 27, and the copper wiring 88 is electrically connected to the contact plug 75 via the barrier metal layer 87. The copper wiring 88 is a bit line of the DRAM memory cell and is located above the capacitor 82.

  As described above, since the semiconductor device according to the first embodiment includes the copper wiring as the upper layer wiring in the memory formation region and the logic formation region, the conventional semiconductor device includes the aluminum wiring as the wiring. The wiring resistance can be reduced as compared with (see FIG. 51). Therefore, a memory / logic mixed type semiconductor device can be improved in performance.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. 1 to 3 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. A method for manufacturing the semiconductor device shown in FIG. 1 will be described below with reference to FIGS.

  First, the structure shown in FIG. 50 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 2, an insulating layer 28 employing, for example, a silicon oxide film is formed on the entire surface. As a result, the insulating layer 28 is provided on the insulating layer 23 and the contact plugs 25 and 75.

  Next, a photoresist (not shown) having a predetermined pattern is formed on the insulating layer 28, and the insulating layer 28 is etched and removed using the photoresist as a mask. Thereby, as shown in FIG. 3, an opening 26 exposing the contact plug 25 and an opening 86 exposing the contact plug 75 are formed in the insulating layer 28.

  Next, a barrier metal layer made of tantalum nitride or the like is formed on the entire surface, and then a copper material filling the openings 26 and 86 is formed on the entire surface. Then, the barrier metal layer and the copper material on the upper surface of the insulating layer 28 are removed by a CMP method or the like. As a result, the opening 26 is filled and the copper wiring 29 electrically connected to the contact plug 25 via the barrier metal layer 27 and the opening 86 are filled and the capacitor 82 is connected via the barrier metal layer 87. A copper wiring 88 electrically connected to the contact plug 66 that is not in contact is formed, and the structure shown in FIG. 1 is completed.

  Through the above steps, a memory device is formed in the memory formation region, and a logic device is formed in the logic formation region.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, since the copper wiring is used for the wiring formed in the upper layer of the memory formation region and the logic formation region, the aluminum wiring is used for the wiring. The wiring resistance can be reduced as compared with the conventional method for manufacturing a semiconductor device. Therefore, a memory / logic mixed type semiconductor device can be improved in performance.

Embodiment 2. FIG.
In the method of manufacturing the semiconductor device according to the first embodiment, when the opening 69 is formed (see FIG. 46) or when the contact holes 15, 65, 24, and 74 are formed (see FIGS. 44 and 49). Uses the stopper films 13 and 17 as etching stoppers, etches the interlayer insulating films 14 and 18, and then etches the stopper films 13 and 17. At this time, when the interlayer insulating films 14 and 18 are etched using the mixed gas as described above, a fluorocarbon (CxFy) deposition film is deposited on the upper surfaces of the stopper films 13 and 17. By generating this deposition film, the selectivity for the stopper films 13 and 17 when the interlayer insulating films 14 and 18 are etched is enhanced.

  If the stopper films 13 and 17 are etched with the deposition film deposited on the stopper films 13 and 17, the stopper films 13 and 17 cannot be normally etched because the deposition film serves as a mask. In order to avoid this problem, a photoresist removal process is performed before the stopper films 13 and 17 are etched, and the deposition film is also removed in this process.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, when forming the opening 69 or the contact holes 15, 65, 24, 74, the step of etching the interlayer insulating films 14, 18; A process of etching the stopper films 13 and 17 is necessary, and a process of removing the photoresist is necessary between the processes. Therefore, when forming the opening 69 or the contact holes 15, 65, 24, 74, it is necessary to replace the manufacturing apparatus from the etching apparatus to the ashing apparatus or from the ashing apparatus to the etching apparatus. As a result, it took time to manufacture the semiconductor device.

  Therefore, the second embodiment and the third embodiment to be described later provide a manufacturing method capable of shortening the manufacturing time of the semiconductor device as compared with the manufacturing method according to the first embodiment described above.

  4-11 is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. The semiconductor device according to the second embodiment is a memory / logic mixed type semiconductor device. As the memory device, for example, a DRAM having a CUB structure memory cell is adopted, and as the logic device, for example, Dual Gate salicide. A CMOS transistor is employed. A method for manufacturing a semiconductor device according to the second embodiment will be described below with reference to FIGS.

  First, the structure shown in FIG. 42 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 4, an insulating layer 19 composed of the stopper films 13 and 17 and the interlayer insulating film 14 is formed on the semiconductor substrate 1 so as to cover the gate structures 11 and 61. Specifically, the stopper film 13 is formed on the entire surface, and the interlayer insulating film 14 is formed on the stopper film 13. Then, a stopper film 17 is formed on the interlayer insulating film 14.

  In the first embodiment, the stopper film 17 is included in the insulating layer 20, but in the second embodiment, the stopper film 17 is included in the insulating layer 19 instead of the insulating layer 20 described later. That is, the insulating layer 19 includes the stopper film 17 on the upper layer, and the insulating layer 20 described later does not include the stopper film 17.

  Next, as shown in FIG. 5, contact plugs 16 and 66 are formed in the insulating layer 19. The contact plug 16 is electrically connected to the semiconductor substrate 1 in the logic formation region via the cobalt silicide film 12, and the upper surface is exposed from the stopper film 17 of the insulating layer 19. The contact plug 66 is electrically connected to the semiconductor substrate 1 in the memory formation region via the cobalt silicide film 12, and the upper surface is exposed from the stopper film 17 of the insulating layer 19. A method for manufacturing the contact plugs 16 and 66 will be specifically described below.

  First, a contact hole 65 reaching the cobalt silicide film 12 on the semiconductor substrate 1 in the memory formation region and a contact hole 15 reaching the cobalt silicide film 12 on the semiconductor substrate 1 in the logic formation region are formed in the insulating layer 19.

When forming the contact holes 15 and 65, first, a photoresist (not shown) having a predetermined opening pattern is formed on the stopper film 17 of the insulating layer 19 by photolithography. Then, using the photoresist as a mask, the stopper film 17 is removed by etching. In this etching, anisotropic dry etching using, for example, a mixed gas of CHF ₃ , O ₂ and Ar is employed.

Next, the etching conditions such as the gas used are changed, and the interlayer insulating film 14 of the insulating layer 19 is etched using the photoresist on the stopper film 17 as a mask again. At this time, the stopper film 13 functions as an etching stopper. In this etching, for example, a mixed gas of C ₅ F ₈ , O ₂ and Ar is used.

Then, the photoresist is removed, the entire surface is etched, and the exposed stopper film 13 is removed. In this etching, anisotropic dry etching using a mixed gas of CHF ₃ , O ₂ and Ar is employed. As a result, the contact hole 15 positioned above the source / drain region 9 while being positioned on the side of the gate electrode 6 and the source / drain region 59 positioned on the side of the gate electrode 56 are positioned. Contact holes 65 are formed in the insulating layer 19 in the logic formation region and the memory formation region, respectively. When the stopper film 13 is etched, the stopper film 17 is also etched because the entire surface is etched. Therefore, the film thickness of the stopper film 17 is adjusted so that a predetermined thickness remains when the etching of the stopper film 13 is completed.

  Next, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium or tungsten is formed on the entire surface. Then, the stacked film on the upper surface of the insulating layer 19 is removed by CMP. As a result, the contact plug 16 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 15, and the contact plug 66 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 65. Is formed. As a result, the source / drain region 59 and the contact plug 66 are electrically connected, and the source / drain region 9 and the contact plug 16 are electrically connected. Although not shown, a contact plug that is electrically connected to the gate electrode 56 or the gate electrode 6 through the cobalt silicide film 12 is also formed in the insulating layer 19.

Next, as shown in FIG. 6, an insulating layer 20 composed of an interlayer insulating film 18 is formed on the entire surface. Thus, the insulating layer 20, that is, the interlayer insulating film 18 is provided on the stopper film 17 and the contact plugs 16 and 66 of the insulating layer 19. Then, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 20, and the insulating layer 20 is etched using the photoresist as a mask and the stopper film 17 and the contact plug 66 as an etching stopper. And remove. Then, the photoresist is removed. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. As a result, an opening 69 is formed in the insulating layer 20 to expose the contact plug 66 electrically connected to one of the adjacent source / drain regions 59.

  In the etching method employed when removing the insulating layer 20, the contact plug 66 is difficult to be etched, and the selection ratio between the insulating layer 20 and the contact plug 66 is usually sufficiently large. Therefore, like the stopper film 17, the contact plug 66 can function as an etching stopper, and the opening 69 can be prevented from reaching the gate electrode 56 or the semiconductor substrate 1.

  Next, a capacitor 82 of a DRAM memory cell that contacts the contact plug 66 is formed in the opening 69. Specifically, first, a metal film containing a refractory metal such as ruthenium is formed on the entire surface. Then, the opening 69 is covered with a photoresist (not shown), and the metal film on the upper surface of the insulating layer 20 is removed by anisotropic dry etching. As a result, as shown in FIG. 7, the lower electrode 70 of the capacitor is formed in the opening 69. Although the metal film on the upper surface of the insulating layer 20 is removed by anisotropic dry etching, the metal film may be removed using a CMP method.

  Next, an insulating film made of tantalum pentoxide and a metal film containing a refractory metal such as ruthenium are laminated in this order, and then patterned using a photoresist. As a result, as shown in FIG. 8, the dielectric film 71 and the upper electrode 72 of the capacitor are formed, and the capacitor 82 is completed in the opening 69.

Next, as shown in FIG. 9, an insulating layer 23 is formed on the entire surface and planarized by CMP. Thereby, the insulating layer 23 covering the capacitor 82 is formed on the insulating layer 20. Then, contact holes 24 and 74 are formed in the insulating layers 20 and 23. Specifically, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 23, and using the photoresist as a mask, the stopper film 17 and the contact plugs 16 and 66 are used as etching stoppers. The insulating layers 20 and 23 are removed by etching. Then, the photoresist is removed. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed.

  Thus, a contact hole 24 reaching the contact plug 16 from the upper surface of the insulating layer 23 and a contact hole 74 reaching the contact plug 66 not in contact with the capacitor from the upper surface of the insulating layer 23 are formed.

  In the etching method employed when removing the insulating layers 20 and 23, the contact plugs 16 and 66 are not easily etched, and usually the selectivity between the insulating layers 20 and 23 and the contact plugs 16 and 66 is sufficient. Big. Therefore, the contact plugs 16 and 66 can function as an etching stopper. Although not shown, a contact hole reaching the upper electrode 72 from the upper surface is also formed in the insulating layer 23.

  Next, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium, tungsten or the like is formed on the entire surface with the barrier metal layer facing down. Then, the stacked film on the upper surface of the insulating layer 23 is removed by CMP. As a result, as shown in FIG. 10, the contact plug 25 filling the contact hole 24 and the contact plug 75 filling the contact hole 74 are formed.

  Next, the insulating layer 28, the openings 26 and 86, the barrier metal layers 27 and 87, and the copper wirings 29 and 88 are formed by the same manufacturing method as in the first embodiment. Thereby, the structure shown in FIG. 11 is obtained.

  Through the above steps, a memory device is formed in the memory formation region, and a logic device is formed in the logic formation region.

  As described above, in the method of manufacturing the semiconductor device according to the second embodiment, the contact plugs 16 and 66 are also formed in the stopper film 17, so that the opening 69 or the contact holes 24 and 74 are formed. Therefore, the stopper film 17 is not etched. In the second embodiment, since it is necessary to remove the photoresist after etching the interlayer insulating film, it is necessary to switch from the etching apparatus to the ashing apparatus. What is the manufacturing method according to the first embodiment described above? In contrast, when the opening 69 or the contact holes 24 and 74 are formed, switching from the ashing device to the etching device is not necessary. Therefore, the time required for forming the opening 69 or the contact holes 24 and 74 can be shortened. As a result, the manufacturing time of the semiconductor device can be shortened compared to the manufacturing method according to the first embodiment.

  It should be noted that when comparing the step of forming contact holes 15 and 65 in the second embodiment (see FIG. 5) with the step of forming contact holes 15 and 65 in the first embodiment (see FIG. 44), this embodiment In the second embodiment, a step of etching the stopper film 17 is further required. However, since the process following the etching of the stopper film 17 is a process of etching the interlayer insulating film 14, there is no need to switch the manufacturing apparatus, and the interlayer insulation is changed from the process of etching the stopper film 17 only by changing the etching conditions. It is possible to switch to the step of etching the film 14. For this reason, the increase in the manufacturing time caused by the addition of the step of etching the stopper film 17 is much smaller than the reduction in the manufacturing time described above, and hardly affects the total manufacturing time.

Embodiment 3 FIG.
12-16 is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention in order of a process. The semiconductor device according to the third embodiment is a memory / logic mixed type semiconductor device. As the memory device, for example, a DRAM having a memory cell having a CUB structure is adopted, and as the logic device, for example, Dual Gate salicide. A CMOS transistor is employed. A method for manufacturing a semiconductor device according to the third embodiment will be described below with reference to FIGS.

  First, the structure shown in FIG. 44 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 12, an insulating layer 20 composed of an interlayer insulating film 18 is formed on the entire surface. As a result, the insulating layer 20 is formed on the interlayer insulating film 14 and the contact plugs 16 and 66 of the insulating layer 19. Although the insulating layer 20 according to the first embodiment described above includes the stopper film 17, the insulating layer 20 according to the third embodiment does not include the stopper film 17.

Next, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 20, and the insulating layer 20 is removed by etching using the photoresist as a mask. Then, the photoresist is removed. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. As a result, an opening 69 is formed in the insulating layer 20 to expose the contact plug 16 electrically connected to one of the adjacent source / drain regions 59.

  In the etching method employed when removing the insulating layer 20, the contact plug 66 is difficult to be etched, and the selection ratio between the insulating layer 20 and the contact plug 66 is usually sufficiently large. In addition, by increasing the uniformity of the film thickness of the insulating layer 20 and stabilizing the etching rate of the insulating layer 20, the amount of overetching when the insulating layer 20 is etched can be reduced. Thus, it is possible to prevent the opening 69 from reaching the gate electrode 56 or reaching the semiconductor substrate 1.

  Next, a capacitor 82 of a DRAM memory cell that contacts the contact plug 66 is formed in the opening 69. Specifically, first, a metal film containing a refractory metal such as ruthenium is formed on the entire surface. Then, the opening 69 is covered with a photoresist (not shown), and the metal film on the upper surface of the insulating layer 20 is removed by anisotropic dry etching. Thereby, as shown in FIG. 13, the lower electrode 70 of the capacitor is formed in the opening 69. Although the metal film on the upper surface of the insulating layer 20 is removed by anisotropic dry etching, the metal film may be removed using a CMP method.

  Next, an insulating film made of tantalum pentoxide and a metal film containing a refractory metal such as ruthenium are laminated in this order, and then patterned using a photoresist. As a result, as shown in FIG. 14, the dielectric film 71 and the upper electrode 72 of the capacitor are formed, and the capacitor 82 is completed in the opening 69.

Next, as shown in FIG. 15, an insulating layer 23 is formed on the entire surface and planarized by CMP. Thereby, the insulating layer 23 covering the capacitor 82 is formed on the insulating layer 20. Then, contact holes 24 and 74 are formed in the insulating layers 20 and 23. Specifically, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 23, and the insulating layers 20 and 23 are removed by etching using the photoresist as a mask. Then, the photoresist is removed. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed.

  Thus, a contact hole 24 reaching the contact plug 16 from the upper surface of the insulating layer 23 and a contact hole 74 reaching the contact plug 66 not in contact with the capacitor from the upper surface of the insulating layer 23 are formed.

  In the etching method employed when removing the insulating layers 20 and 23, the contact plugs 16 and 66 are not easily etched, and usually the selectivity between the insulating layers 20 and 23 and the contact plugs 16 and 66 is sufficient. Big. Further, by increasing the uniformity of the film thickness of the insulating layers 20 and 23 and stabilizing the etching rate of the insulating layers 20 and 23, the amount of overetching when the insulating layers 20 and 23 are etched can be reduced. As a result, even when the positions where the contact holes 24 and 74 are formed are shifted, the contact holes 24 and 74 can be prevented from reaching the gate electrode 56 or the semiconductor substrate 1. Although not shown, a contact hole reaching the upper electrode 72 from the upper surface is also formed in the insulating layer 23.

  Next, contact plugs 25 and 75, insulating layer 28, openings 26 and 86, barrier metal layers 27 and 87, and copper wirings 29 and 88 are formed by the same manufacturing method as in the second embodiment. Thereby, the structure shown in FIG. 16 is obtained.

  Through the above steps, a memory device is formed in the memory formation region, and a logic device is formed in the logic formation region.

  As described above, in the method of manufacturing the semiconductor device according to the third embodiment, since the stopper film 17 is not formed, that is, the interlayer insulating film 18 is formed directly on the insulating layer 19 and the contact plugs 16 and 66. Therefore, when the opening 69 or the contact holes 24 and 74 are formed, the step of etching the stopper film is not performed. In the third embodiment, since it is necessary to remove the photoresist after etching the interlayer insulating film, switching from the etching apparatus to the ashing apparatus is necessary, but the opening 69 or the contact holes 24 and 74 are formed. In this case, switching from the ashing apparatus to the etching apparatus is not necessary. Therefore, in such a case, the time required for forming the opening 69 or the contact holes 24 and 74 is shortened as compared with the manufacturing method according to the first embodiment which requires switching from the ashing device to the etching device. be able to. As a result, the manufacturing time of the semiconductor device can be shortened compared to the manufacturing method according to the first embodiment.

  Further, unlike the method for manufacturing the semiconductor device according to the first and second embodiments, the step of forming the stopper film 17 is not necessary, and therefore the manufacturing time can be further shortened.

Embodiment 4 FIG.
In the semiconductor device manufacturing method according to the above-described first to third embodiments, for example, as shown in FIG. 5, only the cobalt silicide film 12 exists between the upper surfaces of the gate electrodes 6 and 56 and the stopper film 13. In this period, there is no insulating film. Therefore, the contact hole 15 is not formed in the self-aligned structure with respect to the gate electrode 6 or the contact hole 65 is formed with respect to the gate electrode 56. Specifically, when the contact hole 15 is formed above the gate electrode 6 due to misalignment or the like, the cobalt silicide film 12 on the gate electrode 6 is exposed. 16 is short-circuited. Similarly, when the contact hole 65 is formed above the gate electrode 56, the cobalt silicide film 12 on the gate electrode 56 is exposed, and the gate electrode 56 and the contact plug 66 are short-circuited.

  Therefore, in order to prevent a short circuit between the contact plug 16 and the gate electrode 6 or a short circuit between the contact plug 66 and the gate electrode 56, (1) alignment accuracy, (2) dimensional variation of the contact hole, and (3) gate electrode. The distance m between the contact hole 15 and the gate electrode 6 (see FIG. 5) or the contact hole 15 and the gate electrode 56 It was necessary to determine the design value of the distance m between. Therefore, when the contact holes 15 and 65 cannot be formed in a self-aligned structure with respect to the gate electrode, in the manufacturing method according to the first to third embodiments, the dimensions of the memory formation region and the logic formation region are reduced. As a result, it is difficult to miniaturize the semiconductor device.

  Therefore, in the fourth embodiment, even when the contact hole cannot be formed in a self-aligned structure with respect to the gate electrode, a semiconductor capable of miniaturizing a memory / logic mixed type semiconductor device can be achieved. An apparatus manufacturing method is provided.

  First, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention corresponding to the first embodiment will be described below with reference to FIGS.

  First, the structure shown in FIG. 43 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 17, the contact hole 65 reaching the cobalt silicide film 12 on the semiconductor substrate 1 in the memory formation region and the semiconductor substrate 1 in the logic formation region by the manufacturing method similar to the first embodiment. A contact hole 15 reaching the cobalt silicide film 12 is formed in the insulating layer 19. Although not shown, a contact hole reaching the cobalt silicide film 12 on each gate electrode 6, 56 is formed in the insulating layer 19 simultaneously with the contact holes 15, 65.

  Next, an insulating film made of, for example, a silicon nitride film is formed on the entire surface, and the insulating film is anisotropically etched from its upper surface. Thus, as shown in FIG. 18, an insulating film 35 made of, for example, a silicon nitride film is formed on the side surfaces of the contact holes 15 and 65 and the contact holes (not shown) above the gate electrodes 6 and 56, respectively. .

  Next, as shown in FIG. 19, a contact plug 16 filling the contact hole 15 and a contact plug 66 filling the contact hole 65 are formed. The contact plug 16 is electrically connected to the semiconductor substrate 1 in the logic formation region via the cobalt silicide film 12, and the upper surface is exposed from the interlayer insulating film 14 of the insulating layer 19. The contact plug 66 is electrically connected to the semiconductor substrate 1 in the memory formation region via the cobalt silicide film 12, and the upper surface is exposed from the interlayer insulating film 14. A method for manufacturing the contact plugs 16 and 66 will be specifically described below.

  First, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium, tungsten or the like is formed on the entire surface with the barrier metal layer facing down. Then, the stacked film on the upper surface of the insulating layer 19 is removed by CMP. As a result, the contact plug 16 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 15, and the contact plug 66 is formed of the barrier metal layer and the refractory metal layer and fills the contact hole 65. Is formed. As a result, the source / drain region 59 and the contact plug 66 are electrically connected, and the source / drain region 9 and the contact plug 16 are electrically connected. When the contact plugs 16 and 66 are formed, a contact plug that fills the contact hole above the gate electrodes 6 and 56 is also formed at the same time. As a result, contact plugs electrically connected to the gate electrodes 6 and 56 are formed in the insulating layer 19 through the cobalt silicide film 12.

  Next, as shown in FIG. 20, an insulating layer 20 including a stopper film 17 and an interlayer insulating film 18 is formed on the entire surface. Specifically, first, the stopper film 17 is formed on the entire surface. Then, an interlayer insulating film 18 is formed on the stopper film 17. Thereby, the insulating layer 20 is provided on the insulating layer 19 and the contact plugs 16 and 66.

  Next, the insulating layers 23 and 28, the capacitor 82, the contact holes 24 and 74, the contact plugs 25 and 75, the openings 26 and 86, and the barrier metal layers 27 and 87 are manufactured by the same manufacturing method as in the first embodiment. And copper wirings 29 and 88 are formed. Thereby, the structure shown in FIG. 21 is obtained.

  As described above, in the method of manufacturing the semiconductor device according to the fourth embodiment corresponding to the first embodiment, the insulating film 35 is formed on the side surfaces of the contact holes 15 and 65 (see FIG. 18). A contact plug 16 filling the contact hole 15 and a contact plug 66 filling the contact hole 65 are formed (see FIG. 19).

  Therefore, the insulating film 35 is provided between the contact hole 15 and the gate electrode 6 or between the contact hole 65 and the gate electrode 56. Therefore, by setting the thickness of the insulating film 35 to a dimension that can ensure the insulation between the gate electrode 6 and the contact plug 16, the above-mentioned (1) alignment accuracy and (2) dimension variation of the contact hole are obtained. , The design value of the distance m (see FIG. 19) between the contact hole 15 and the gate electrode 6 can be determined, and (3) the insulation between the gate electrode and the contact plug can be determined. There is no need to consider the size of the insulating film that can be secured. In other words, it is not necessary to consider the insulation between the gate electrode 6 and the contact plug 16 when determining the design value of the distance m between the contact hole 15 and the gate electrode 6.

  Similarly, by setting the thickness of the insulating film 35 to a dimension that can ensure the insulation between the gate electrode 56 and the contact plug 66, the above-mentioned (3) insulation between the gate electrode and the contact plug is achieved. The design value of the distance m between the gate electrode 56 and the contact hole 65 can be determined without considering the size of the insulating film that can ensure the above.

  Therefore, even when the contact hole cannot be formed in a self-aligned structure with respect to the gate electrode, the distance between the contact hole and the gate electrode is larger than that in the method for manufacturing the semiconductor device according to the first embodiment. The design value of m can be reduced. Therefore, the dimensions of the memory formation region and the logic formation region can be reduced. As a result, the semiconductor device can be made finer than the manufacturing method according to the first embodiment.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention corresponding to the second embodiment will be described below with reference to FIGS.

  First, the structure shown in FIG. 42 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 22, the insulating layer 19 and the contact holes 15 and 65 are formed by the same manufacturing method as in the second embodiment. Although not shown, a contact hole reaching the cobalt silicide film 12 on each gate electrode 6, 56 is formed in the insulating layer 19 simultaneously with the contact holes 15, 65.

  Next, an insulating film made of, for example, a silicon nitride film is formed on the entire surface, and the insulating film is anisotropically etched from its upper surface. Thus, as shown in FIG. 23, the insulating film 35 is formed on the side surfaces of the contact holes 15 and 65 and the contact holes (not shown) above the gate electrodes 6 and 56, respectively.

  Next, as shown in FIG. 24, a contact plug 16 filling the contact hole 15 and a contact plug 66 filling the contact hole 65 are formed. The contact plug 16 is electrically connected to the semiconductor substrate 1 in the logic formation region via the cobalt silicide film 12, and the upper surface is exposed from the stopper film 17. The contact plug 66 is electrically connected to the semiconductor substrate 1 in the memory formation region via the cobalt silicide film 12, and the upper surface is exposed from the stopper film 17. A method for manufacturing the contact plugs 16 and 66 will be specifically described below.

  First, a laminated film of a barrier metal layer made of titanium nitride or the like and a refractory metal layer made of titanium, tungsten or the like is formed on the entire surface with the barrier metal layer facing down. Then, the stacked film on the upper surface of the stopper film 17 is removed by using a CMP method. As a result, a contact plug 16 filling the contact hole 15 and a contact plug 66 filling the contact hole 65 are formed. As a result, the source / drain region 59 and the contact plug 66 are electrically connected, and the source / drain region 9 and the contact plug 16 are electrically connected. When the contact plugs 16 and 66 are formed, a contact plug that fills the contact hole above the gate electrodes 6 and 56 is also formed at the same time. As a result, contact plugs electrically connected to the gate electrodes 6 and 56 are formed in the insulating layer 19 and the stopper film 17 through the cobalt silicide film 12.

  Next, as shown in FIG. 25, an insulating layer 20 made of an interlayer insulating film 18 is formed on the entire surface. Thereby, the insulating layer 20 is formed on the stopper film 17 and the contact plugs 16 and 66 of the insulating layer 19.

  Next, the openings 26, 69, 86, the capacitor 82, the insulating layers 23, 28, the contact holes 24, 74, the contact plugs 25, 75, and the barrier metal layers 27, 87 are manufactured by the same manufacturing method as in the second embodiment. And copper wirings 29 and 88 are formed. Thereby, the structure shown in FIG. 26 is obtained.

  As described above, in the method of manufacturing the semiconductor device according to the fourth embodiment corresponding to the second embodiment, the insulating film 35 is formed on the side surfaces of the contact holes 15 and 65 (see FIG. 23). A contact plug 16 filling the contact hole 15 and a contact plug 66 filling the contact hole 65 are formed (see FIG. 24). Therefore, the semiconductor device can be made finer than the manufacturing method according to the second embodiment for the reasons described above.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention corresponding to the third embodiment will be described below with reference to FIGS.

  First, the structure shown in FIG. 19 is formed by the manufacturing method described above. Next, as shown in FIG. 27, an insulating layer 20 made of an interlayer insulating film 18 is formed on the entire surface. Thereby, the insulating layer 20 is formed on the insulating layer 19 and the contact plugs 16 and 66.

Then, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 20, and the insulating layer 20 is etched and removed using the photoresist as a mask. Then, the photoresist is removed. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. As a result, an opening 69 is formed in the insulating layer 20 to expose the contact plug 16 electrically connected to one of the adjacent source / drain regions 59.

  Next, the capacitor 82, the insulating layers 23 and 28, the contact holes 24 and 74, the contact plugs 25 and 75, the openings 26 and 86, and the barrier metal layers 27 and 87 are manufactured by the same manufacturing method as in the third embodiment. And copper wirings 29 and 88 are formed. Thereby, the structure shown in FIG. 28 is obtained.

  As described above, in the method of manufacturing the semiconductor device according to the fourth embodiment corresponding to the third embodiment, the insulating film 35 is formed on the side surfaces of the contact holes 15 and 65, and then the contact holes 15 are filled. The contact plug 16 is formed, and the contact plug 66 filling the contact hole 65 is formed. Therefore, the semiconductor device can be made finer than the manufacturing method according to the third embodiment for the reasons described above.

Embodiment 5 FIG.
FIG. 29 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment of the present invention. The semiconductor device according to the fifth embodiment is basically the same as the semiconductor device according to the first embodiment described above, in which the contact plug and the copper wiring in the insulating layer 30 are formed integrally with each other. Contact plugs 43 and 93 and copper wirings 44 and 94 shown in FIG. 29 correspond to contact plugs 25 and 75 and copper wirings 29 and 88 according to the first embodiment, respectively.

  As shown in FIG. 29, the semiconductor device according to the fifth embodiment includes a capacitor 82 provided in the semiconductor substrate 1, the insulating layers 19 and 30, the plurality of contact plugs 16 and 66, and the insulating layer 30. A plurality of contact plugs 43 and 93 and copper wirings 44 and 94 are provided.

  Each contact plug 43 is electrically connected to the contact plug 16 via the barrier metal layer 45, and each contact plug 93 includes a contact plug 66 that is not electrically connected to the capacitor 82 and a barrier metal layer 95. It is electrically connected via. Each contact plug 43, 93 is made of copper. The contact plug 43 and the copper wiring 44 are formed integrally with each other, and the contact plug 93 and the copper wiring 94 are formed integrally with each other. The copper wiring 94 is a bit line of the DRAM memory cell and is located above the capacitor 82.

  Thus, in the semiconductor device according to the fifth embodiment, the contact plug 43 and the copper wiring 44 or the contact plug 93 and the copper wiring 94 are integrally formed with each other.

  In the semiconductor device according to the first embodiment described above, as shown in FIG. 1, the contact plug 25 and the copper wiring 29 or the contact plug 75 and the copper wiring 88 are formed separately from each other. Contact resistance is generated between the wiring 29 or between the contact plug 75 and the copper wiring 88. Therefore, when it is desired to further reduce the electrical resistance between the copper wirings 29, 88 and the source / drain regions 9, 59, it is not easy to meet the demand in the structure shown in FIG.

  On the other hand, in the semiconductor device according to the fifth embodiment, the contact plug 43 and the copper wiring 44 or the contact plug 93 and the copper wiring 94 are integrally formed with each other. Alternatively, there is no boundary between the contact plug 93 and the copper wiring 94. For this reason, no contact resistance is generated between the contact plug 43 and the copper wiring 44 or between the contact plug 93 and the copper wiring 94. Therefore, the contact resistance can be reduced, and even when it is desired to further reduce the electrical resistance between the copper wirings 44 and 94 and the source / drain regions 9 and 59, the demand can be sufficiently met. Is possible.

  Next, a method for manufacturing the semiconductor device shown in FIG. 29 will be described. 29 to 33 are cross-sectional views showing the method of manufacturing the semiconductor device according to the fifth embodiment in the order of steps. The manufacturing method of the semiconductor device according to the fifth embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment described above, except that the contact holes 24 and 74, the contact plugs 25 and 75, the openings 26 and 86, and the barrier metal layer. 27, 87, and copper wirings 29, 88, contact holes 41, 91, contact plugs 43, 93, openings 42, 92, barrier metal layers 45, 95, and copper wirings 44, 94 are formed. A method for manufacturing the semiconductor device shown in FIG. 29 will be described below with reference to FIGS.

  First, the structure shown in FIG. 48 is formed using the above-described conventional method for manufacturing a semiconductor device.

  Next, as shown in FIG. 30, insulating layers 23 and 28 are formed on the entire surface in this order, and planarized using a CMP method or the like. The insulating layers 23 and 28 may be the same insulating layer, and such insulating layers may be deposited on the entire surface at a time.

  Next, as shown in FIG. 31, contact holes 41 and 91 are formed in the insulating layer 30. The contact hole 41 reaches the contact plug 16 from the upper surface of the insulating layer 28, and the contact hole 91 reaches the contact plug 66 that is not in contact with the capacitor from the upper surface of the insulating layer 28.

When forming the contact holes 41 and 91, first, a photoresist (not shown) having a predetermined opening pattern is formed on the insulating layer 28, and using the photoresist as a mask, the stopper film 17 is used as an etching stopper. Then, the insulating layers 23 and 28 and the interlayer insulating film 18 are removed by etching. In the etching at this time, anisotropic dry etching using a mixed gas of C ₅ F ₈ , O ₂ and Ar is employed. Then, the photomask is removed, and the exposed stopper film 17 is removed by etching. In this etching, anisotropic dry etching using a mixed gas of CHF ₃ , O ₂ and Ar is employed. As a result, contact holes 41 and 91 are formed in the insulating layer 30. Although not shown, a contact hole reaching the upper electrode 72 from the upper surface is formed in the insulating layers 23 and 28 simultaneously with the contact holes 41 and 91.

  Next, a resist 99 is applied to the entire surface while filling the contact holes 41 and 91. Then, as shown in FIG. 32, the resist 99 is dry-etched from the upper surface, and the resist 99 above the insulating layer 23 is removed.

  Next, a photoresist (not shown) having a predetermined pattern is formed on the insulating layer 28, and the insulating layer 28 is etched and removed using the photoresist and the resist 99 as a mask. Then, the photoresist and the resist 99 are removed. Thereby, as shown in FIG. 33, an opening 42 communicating with the contact hole 41 and an opening 92 communicating with the contact hole 91 are formed in the insulating layer 28.

  Next, a barrier metal layer made of tantalum nitride or the like is formed on the entire surface, and thereafter, a copper material filling each of the contact holes 41 and 91 and the openings 42 and 92 is formed on the insulating layer 28 at a time. Then, the barrier metal layer and the copper material on the upper surface of the insulating layer 28 are removed by a CMP method or the like. 29 is completed, the barrier metal layer 45 covering the surface of the contact hole 41 and the opening 42, the contact plug 43 filling the contact hole 41, and the copper wiring 44 filling the opening 42, Is formed. At the same time, a barrier metal layer 95 that covers the surfaces of the contact hole 91 and the opening 92, a contact plug 93 that fills the contact hole 91, and a copper wiring 94 that fills the opening 92 are formed.

  As described above, according to the method for manufacturing a semiconductor device according to the fifth embodiment, the contact hole 41 and the opening 42 are filled with the copper material at the same time, so that the contact plug 43 and the copper wiring 44 are formed at the same time. Is done. Similarly, since the contact hole 91 and the opening 92 are filled with a copper material at the same time, the contact plug 93 and the copper wiring 94 are formed at the same time.

  On the other hand, in the above-described first embodiment, after the contact plugs 25 and 75 are formed, the openings 26 and 86 are formed, and then the copper wirings 29 and 88 are formed. That is, the contact plug 25 and the copper wiring 29, or the contact plug 75 and the copper wiring 88 are formed in separate processes, and are not formed at the same time.

  Therefore, according to the manufacturing method of the semiconductor device according to the fifth embodiment, the manufacturing process can be reduced and the mass productivity can be reduced as compared with the case where the contact plug and the copper wiring are separately formed as in the first embodiment. Excellent.

  In the method for manufacturing a semiconductor device according to the above-described second to fourth embodiments, contact holes 24 and 74, contact plugs 25 and 75, openings 26 and 86, barrier metal layers 27 and 87, and copper wirings 29 and 88 are formed. Instead, contact holes 41 and 91, contact plugs 43 and 93, openings 42 and 92, barrier metal layers 45 and 95, and copper wirings 44 and 94 may be formed.

  Specifically, in each of the second to fourth embodiments, after the capacitor 82 is formed, the insulating layers 23 and 28 are formed on the entire surface in this order (see FIG. 30), and then contacted by the above-described manufacturing method. Holes 41 and 91 and openings 42 and 92 are formed (see FIGS. 31 to 33). Then, a barrier metal layer is formed on the entire surface, and thereafter, a copper material filling each of the contact holes 41 and 91 and the openings 42 and 92 is formed on the insulating layer 28 at a time. Thereafter, the barrier metal layer and the copper material on the upper surface of the insulating layer 28 are removed by a CMP method or the like. Thereby, the structure shown in FIGS. The structures shown in FIGS. 34 and 35 correspond to the second and third embodiments, respectively. The structures shown in FIGS. 36 to 38 correspond to Embodiments 4 corresponding to Embodiments 1 to 3, respectively.

  As described above, in addition to the effects obtained in the respective embodiments by applying the invention according to the fifth embodiment to each of the semiconductor device manufacturing methods according to the above-described second to fourth embodiments, the above-described effects can be obtained. The effect is obtained.

  1 semiconductor substrate, 6,56 gate electrode, 9,59 source / drain region, 11,61 gate structure, 15, 24, 65, 74, 41, 91 contact hole, 16, 25, 66, 75, 43, 93 contact Plug, 17 Stopper film, 18 Interlayer insulating film, 19, 20, 23, 28, 30 Insulating layer, 29, 88, 44, 94 Copper wiring, 35 Insulating film, 69, 26, 86, 42, 92 Opening, 82 Capacitor.

Claims (3)

A semiconductor substrate having a first region in which a memory device is formed and a second region in which a logic device is formed;
A first insulating layer provided on the semiconductor substrate;
First and second contacts provided in the first insulating layer, each being electrically connected to the semiconductor substrate in the first region, with each upper surface exposed from the first insulating layer. Plug and
A third contact plug provided in the first insulating layer and electrically connected to the semiconductor substrate in the second region, with an upper surface exposed from the first insulating layer;
A second insulating layer provided on the first insulating layer and the first to third contact plugs;
A capacitor electrically connected to the first contact plug and provided in the second insulating layer;
A fourth contact plug electrically connected to the second contact plug and provided in the second insulating layer;
A fifth contact plug electrically connected to the third contact plug and provided in the second insulating layer;
A first copper wiring electrically connected to the fourth contact plug and provided in the second insulating layer;
A semiconductor device comprising: a second copper wiring electrically connected to the fifth contact plug and provided in the second insulating layer. Each of the fourth and fifth contact plugs is made of copper,
The first copper wiring and the fourth contact plug are formed integrally with each other,
The semiconductor device according to claim 1, wherein the second copper wiring and the fifth contact plug are integrally formed with each other. First and second source / drain regions provided in an upper surface of the semiconductor substrate in the first region and having a predetermined distance from each other;
A gate structure provided on the semiconductor substrate between the first and second source / drain regions;
The first and second contact plugs are electrically connected to the first and second source / drain regions, respectively.
The semiconductor device according to claim 1, wherein the first copper wiring is a bit line of the memory device and is located above the capacitor.

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