JP2008205032A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured easily as a high-reliability device, with high performance and with high integration density for circuit elements. <P>SOLUTION: The semiconductor device 60 is constituted by forming a plurality of circuit elements 22 in a semiconductor substrate 10, laminating a first inter-layer insulating film 30 and a second inter-layer insulating film 45, in this order, so as to cover the circuit elements, and respectively connecting damascene wiring parts 53, 57 formed in the second inter-layer insulating film to the prescribed circuit elements, formed in the semiconductor substrate with the use of prescribed contact plug parts 35 formed in the first inter-layer insulating film. When the semiconductor device 60 is constituted, the plurality of damascene wiring parts include at least one first damascene wiring part 53, which is partially in contact with the upper surface and side surface upper part of the corresponding contact plug part and is electrically connected to the contact plug part. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having damascene wiring.

  The integration density of circuit elements in a semiconductor device in which a desired integrated circuit is formed on a semiconductor substrate is steadily increasing. With the high integration of circuit elements, the performance and miniaturization of individual circuit elements are increasing. In addition, miniaturization of wiring in a multilayer wiring portion formed on a semiconductor substrate is attempted. For example, the line width of the gate electrode in the field effect transistor is gradually narrowed to 130 nm, 90 nm, 65 nm, and 45 nm. In order to form a fine and low electrical resistance wiring, a material having high conductivity such as copper and aluminum has been widely used as a wiring material, and the forming method is also formed on an interlayer insulating film. The method of patterning the conductive film into a predetermined shape has changed to the damascene method.

  The damascene method can be divided into a single damascene method and a dual damascene method. In either method, a wiring is formed by filling a wiring groove formed in an interlayer insulating film with a conductive material. A via contact is formed by filling a via hole formed in the film with a conductive material. In the single damascene method, the embedding of the conductive material into the via hole and the embedding of the conductive material into the wiring groove are performed in separate steps, and in the dual damascene method, the embedding of the conductive material into the via hole and the wiring groove is performed. Conductive material embedding is performed in the same process.

  In many cases, a barrier metal layer for preventing the conductive material from diffusing into the interlayer insulating film covers the wall surface of the via hole, the wall surface of the wiring groove, and the surface of the underlying layer exposed from the bottom of the via hole. After that, a conductive material is buried in the via hole and the wiring groove. In this specification, wiring formed by the damascene method is referred to as a “damascene wiring portion”, and the damascene wiring portion includes the barrier metal layer (hereinafter referred to as “wiring portion barrier metal layer”). To do. Also, in the damascene wiring part, the region formed by embedding a conductive material in the wiring groove after forming the barrier metal layer is referred to as “wiring region”, and the conductive material is applied to the via hole after forming the barrier metal layer. A region formed by embedding is referred to as a “via contact region”, and a wiring region and a via contact region are collectively referred to as a “damascene body”.

  Nowadays, the via contact region is also narrowed along with the narrowing of the damascene wiring portion, and the lowermost damascene wiring portion formed in the multilayer wiring portion, that is, 2 from the semiconductor substrate, is counted. In the damascene wiring portion formed in the second interlayer insulating film (hereinafter referred to as “second interlayer insulating film”), the lowermost interlayer insulating film (hereinafter referred to as “the second interlayer insulating film”) is connected in order to connect the damascene wiring portion and the circuit element. The dimension of the upper surface of the contact plug formed in the first interlayer insulating film) may be larger than the dimension of the bottom surface of the via contact region.

  In a semiconductor device having a high integration density of circuit elements, a second interlayer insulating film is usually stacked on the first interlayer insulating film via a liner film. In forming the damascene wiring portion in the second interlayer insulating film, a through-hole is previously formed by dry etching in a region of the liner film that will be located below the via contact region, Ensure electrical continuity with the contact plug. Since a large number of contact plugs are formed in one semiconductor device, in consideration of manufacturing variations, dry etching for obtaining the liner film by forming the above-described through hole in the film that is the base of the liner film is This is performed slightly more than the thickness of the liner film.

  As the width of the damascene wiring portion is reduced, higher shape accuracy and higher position accuracy are required for the damascene wiring portion. For example, if the shape accuracy or position accuracy of the damascene wiring portion formed in the second interlayer insulating film is low and the contact area between the damascene wiring portion and the contact plug becomes too narrow than the design value, the electrical resistance between the two increases. In addition, the electromigration resistance is reduced.

  In order to obtain a high-performance and highly reliable semiconductor device, it is necessary to form wiring grooves and via holes for forming damascene wiring portions on the interlayer insulating film with high shape accuracy and high position accuracy. However, for example, in a 45 nm generation semiconductor device, it is inevitable that some of the plurality of damascene wiring portions formed in the second interlayer insulating film cause misalignment with the contact plug corresponding to the damascene wiring portion. Therefore, it is required to narrow the width of the damascene wiring portion to a level that occurs in the above.

  As described above, the liner film interposed between the first interlayer insulating film and the second interlayer insulating film is obtained by forming a through hole at a predetermined position of the original film, and the through hole is formed. The amount of dry etching is slightly larger than the thickness of the liner film. For this reason, even if misalignment occurs during the formation of the damascene wiring portion, the damascene wiring portion is in partial contact with and electrically connected to the upper surface and upper side surface of the corresponding contact plug. Seems also.

  However, the vertical cross-sectional shape of the contact plug is often an inverted mesa shape, and when the vertical cross-sectional shape of the contact plug is an inverted mesa shape, the etching amount when forming a through hole in the liner film is selected as described above. Even so, the region located in the vicinity of the side surface of the contact plug in the first interlayer insulating film is behind the upper surface of the contact plug and is difficult to be etched, so that it is difficult to expose the side surface of the contact plug. Further, according to the research of the present inventors, when the etching amount when forming a through hole by selectively removing a predetermined portion of the film that becomes the liner film by dry etching is selected as described above, the alignment shift is caused. When the first interlayer insulating film is partially dry etched, the reaction product generated at this time is reattached to the upper part of the side surface of the contact plug or the first interlayer insulating film remaining thinly on the upper side of the contact plug. It became clear.

  For these reasons, when the width of the damascene wiring portion is reduced, the electrical resistance between the damascene wiring portion and the contact plug increases or the electromigration resistance decreases, resulting in high performance and high reliability. It becomes difficult to obtain a semiconductor device.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to obtain a semiconductor device in which circuit elements have a high integration density, and are easy to manufacture with high performance and high reliability.

  A semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate, and a first interlayer formed on the semiconductor substrate so as to cover the plurality of circuit elements. Insulating film, a plurality of contact plug portions penetrating through the first interlayer insulating film, a second interlayer insulating film stacked on the first interlayer insulating film, and a plurality of damascenes formed on the second interlayer insulating film Each of the plurality of damascene wiring units is a semiconductor device connected to a predetermined circuit element formed on the semiconductor substrate via a predetermined contact plug unit, and the plurality of damascene wiring units are It includes at least one first damascene wiring portion that is in partial contact with the upper surface and the upper portion of the side surface of the corresponding contact plug portion.

  Another semiconductor device of the present invention that achieves the above object is formed on a semiconductor substrate so as to cover the semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate, and the plurality of circuit elements. A first interlayer insulating film, a plurality of contact plug portions penetrating the first interlayer insulating film, a second interlayer insulating film stacked on the first interlayer insulating film, and the second interlayer insulating film. A plurality of damascene wiring portions, each of the plurality of damascene wiring portions being a semiconductor device connected to a predetermined circuit element formed on the semiconductor substrate via a predetermined contact plug portion, and having a conductive material And having a cap layer interposed between each of the plurality of contact plug portions and the damascene wiring portion corresponding to the contact plug portion, and the plurality of damascene wiring portions corresponding to the contact plug portion. A cap layer partially covering the upper surface and upper side surface of the contact plug portion is interposed between the lug portion, and at least one first damascene wiring portion is in contact with the cap layer so as to cover the cap layer It is characterized by including.

  In the semiconductor device of the present invention, as described above, the plurality of damascene wiring portions formed in the second interlayer insulating film includes at least one first damascene wiring portion. Then, the first damascene wiring part is in contact with each of the upper surface and the upper part of the side surface of the corresponding contact plug part, or a cap layer that partially covers the upper surface and the upper part of the side surface of the corresponding contact plug part. And is in contact with the cap layer so as to cover the cap layer.

  Of course, when such a first damascene wiring portion is intentionally formed, even when the first damascene wiring portion is generated due to misalignment with the corresponding contact plug portion, the contact area between the two is relatively small. Since it becomes wide, it is easy to keep the electrical resistance between the first damascene wiring portion and the contact plug portion corresponding to the first damascene wiring portion low. Moreover, it is easy to suppress a decrease in electromigration resistance. Therefore, according to the present invention, it is easy to obtain a semiconductor device with high integration density of circuit elements, high performance and high reliability.

  Hereinafter, embodiments of a semiconductor device of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
FIG. 1 is a partial sectional view schematically showing an example of a semiconductor device of the present invention. The semiconductor device 60 shown in FIG. 1 includes a semiconductor substrate 10, a plurality of circuit elements formed on the semiconductor substrate 10, and a first interlayer insulating film 30 formed on the semiconductor substrate 10 so as to cover these circuit elements. A plurality of contact plug portions penetrating the first interlayer insulating film 30, a second interlayer insulating film 45 stacked on the first interlayer insulating film 30, and a plurality of damascenes formed on the second interlayer insulating film 45 And a wiring section. In FIG. 1, one field effect transistor 22 is shown as the circuit element. Also, two contact plug portions 35, 35 of the plurality of contact plug portions are shown, and one first damascene wiring portion 53 and one second damascene of the plurality of damascene wiring portions are shown. The wiring part 57 is shown.

  The semiconductor substrate 10 is obtained by arranging a P-type well 3 and an N-type well 5 in a predetermined pattern on a silicon single crystal substrate 1 and electrically isolating these wells by an element isolation region 7. Instead of the silicon single crystal substrate 1, a substrate made of a compound semiconductor such as gallium arsenide or an SOI (Silicon On Insulator) substrate can be used. The plurality of circuit elements formed on the semiconductor substrate 10 constitute an integrated circuit together with the multilayer wiring portion formed on the semiconductor substrate 10, and how many circuit elements are formed on the semiconductor substrate 10. This is appropriately selected according to the function required for the semiconductor device 60, the use of the semiconductor device 60, and the like.

  A field effect transistor 22 shown as a circuit element in FIG. 1 includes a gate electrode 14 disposed on a semiconductor substrate 10 (on a P-type well 3) via a gate insulating film 12, and a source region formed in the semiconductor substrate 10. 16 and drain region 18, extension regions 19 a and 19 b formed in semiconductor substrate 10, offset spacer films 20 and 20 formed on both sides in the line width direction of gate electrode 14, and lines of offset spacer films 20 and 20 This is a field effect transistor having an LDD (Lightly Doped Drain) structure having sidewall spacers 21 and 21 formed on the outer surface in the width direction.

  The gate electrode 14 has a polysilicon region 14a formed on the gate insulating film 12, and a metal silicide region 14b formed on the polysilicon region 14a. The source region 16 has an N-type impurity diffusion region 16a formed in the semiconductor substrate 10 and a metal silicide region 16b formed on the N-type impurity diffusion region 16a. Similarly, the drain region 18 has an N-type impurity diffusion region 18a formed in the semiconductor substrate 10 and a metal silicide region 18b formed on the N-type impurity diffusion region 18a. The extension region 19a protrudes from the upper portion of the source region 16 on the drain region 18 side to the drain region 18 side, and the extension region 19b extends from the upper portion of the drain region 18 on the source region 16 side to the source region 16 side. When a predetermined voltage is applied to the gate electrode 14, a channel is formed in a region of the P-type well 3 located between the extension region 19a and the extension region 19b.

  Offset spacer films 20 and 20 are formed on both side surfaces in the line width direction of the gate electrode 14 in order to regulate the positions of the ends of the extension regions 19a and 19b on the gate electrode 14 side when the extension regions 19a and 19b are formed. Has been. Further, in order to regulate the position of the end of the N-type impurity diffusion regions 16a and 18a on the gate electrode 14 side when the N-type impurity diffusion regions 16a and 18a are formed, the offset spacer films 20 and 20 are arranged outside the line width direction. Side wall spacers 21 and 21 are formed on the side surfaces.

  In the semiconductor device 60 shown in FIG. 1, the etching stopper film 25 is formed so as to cover the upper surface of the semiconductor substrate 10 and each circuit element, and the first interlayer insulating film 30 covers the etching stopper film 25. Formed on the semiconductor substrate 10. The etching stopper film 25 is formed of, for example, silicon carbonitride or silicon nitride, and is used as an etching stopper when a contact hole for forming a contact plug portion is provided. The first interlayer insulating film 30 is formed of, for example, silicon oxide or a low dielectric constant dielectric.

  Each of the contact plug portions 35, 35 penetrating the first interlayer insulating film 30 includes a plug main body 35a formed of a conductive material such as tungsten, and covers the side and bottom surfaces of the plug main body 35a from the plug main body 35a. And a plug portion barrier metal layer 35b for preventing diffusion of components. For example, when the plug body 35a is formed of tungsten, the plug portion barrier metal layer 35b is formed of titanium nitride, tantalum, tantalum nitride, or the like. The vertical cross-sectional shape of each contact plug portion 35 is, for example, an inverted mesa shape. In a contact plug portion having a reverse mesa shape with a vertical cross section, the upper surface dimension is larger than the lower surface dimension. The lower end of one contact plug in the two contact plug portions 35, 35 shown in FIG. 1 passes through the passivation film 25 and reaches the upper surface of the drain region 18, and the lower end of the other contact plug portion 35 is the passivation film 25. And reaches the upper surface of the source region 16.

  The second interlayer insulating film 45 is formed, for example, by depositing silicon oxide, a low dielectric constant dielectric, or the like on the first interlayer insulating film 30 directly or via a liner film. In the semiconductor device 60 shown in FIG. 1, a second interlayer insulating film 45 is stacked on the first interlayer insulating film 30 via a liner film 40 formed of silicon carbonitride or the like. A plurality of damascene wiring portions are formed in the second interlayer insulating film 45. Each of the plurality of damascene wiring portions includes a damascene main body and a wiring portion barrier metal layer covering the side surface and the bottom surface of the damascene main body. Have. The damascene body includes a wiring region formed by embedding a conductive material such as copper in a wiring groove formed in the second interlayer insulating film 45, and a via hole formed in the second interlayer insulating film 45, such as copper. The via contact region is formed by embedding the conductive material, and the via contact region extends from the lower surface of the wiring region to the first interlayer insulating film 30 side.

The first damascene wiring portion 53 shown in FIG. 1 includes a damascene main body 51 and a wiring portion barrier metal layer 52 that prevents diffusion of components from the damascene main body 51. The damascene body 51 is a dual damascene wiring composed of a wiring region 51a and a via contact region 51b, and the vertical cross-sectional shape of the via contact region 51b is an inverted mesa shape. To facilitate understanding of the wiring area 51a and via contact region 51b, it is indicated by a chain line L ₁ boundary between the wiring area 51a and via contact region 51b in FIG.

The lower end portion of the via contact region 51b in the first damascene wiring portion 53 is a region R located on the upper surface of the contact plug portion 35 whose one end is in contact with the drain region 18 of the two contact plug portions 35 and 35. ₁ and a region R ₂ penetrating through the liner film 40 and entering the first interlayer insulating film 30. In the wiring portion barrier metal layer 52, the region covering the lower surface of the region R ₁ partially covers the upper surface of the contact plug portion 35 corresponding to the first damascene wiring portion 53. Further, a region located around the region R _{2 in} the wiring portion barrier metal layer 52 penetrates into the first interlayer insulating film 30 to the same depth as the film thickness of the liner film 40, and the contact plug portion described above. It is in surface contact with the upper part of the side surface of 35. The first damascene wiring portion 53 is formed corresponding to the contact plug portion 35 and is misaligned. The first damascene wiring portion 53 is partially in contact with each of the upper surface and the upper side surface of the contact plug portion 35. ing.

On the other hand, the second damascene wiring portion 57 shown in FIG. 1 includes a damascene main body 55 and a wiring portion barrier metal layer 56 that prevents diffusion of components from the damascene main body 55. The damascene body 55 is a dual damascene wiring composed of a wiring region 55a and a via contact region 55b, and the vertical cross-sectional shape of the via contact region 55b is an inverted mesa shape. To facilitate understanding of the wiring area 55a and via contact regions 55b, it represents the boundary between the wiring regions 55a and via contact region 55b other by a one-dot chain line L ₁ in FIG. 1.

  The lower end portion of the via contact region 55b in the second damascene wiring portion 53 penetrates the liner film 40, and the region covering the lower surface of the via contact region 55b in the wiring portion barrier metal layer 56 is two contact plug portions 35. , 35 is in contact with the upper surface of the contact plug portion 35 whose one end is in contact with the source region 16. The second damascene wiring portion 57 is formed corresponding to the contact plug portion 35 without substantially causing misalignment. The lower surface of the via contact region 55b in the wiring portion barrier metal layer 56 is formed. The entire region covering the surface is in contact with the upper surface of the contact plug portion 35 described above.

  In the semiconductor device 60, a liner film and an interlayer insulating film are repeatedly laminated in this order on the second interlayer insulating film 45, and a plurality of wirings and a plurality of via contacts are formed on each interlayer insulating film. Although the multilayer wiring part is constructed, these are not the main part of the present invention, and the illustration and description thereof are omitted here.

  In the semiconductor device 60 having the above-described configuration, the first damascene wiring portion 53 is in partial contact with each of the upper surface and the side surface of the contact plug portion 35 corresponding to the first damascene wiring portion 53, so that the contact area between the two Is relatively wide. Therefore, it is easy to suppress the electrical resistance between the first damascene wiring portion 53 and the contact plug portion 35. Moreover, it is easy to suppress a decrease in electromigration resistance.

  The second damascene wiring portion 57 and the contact plug portion 35 corresponding to the second damascene wiring portion 57 are such that the entire region covering the lower surface of the via contact region 55b in the wiring portion barrier metal layer 56 is the contact plug portion 35 described above. Therefore, the electrical resistance between the second damascene wiring portion 57 and the contact plug portion 35 can be kept low. In addition, a decrease in electromigration resistance can be suppressed.

  Therefore, in the semiconductor device 60, when the width of each damascene wiring portion is reduced in order to increase the integration density of circuit elements, performance due to an increase in electrical resistance between the damascene wiring portion and the contact plug portion is obtained. It is easy to suppress degradation and reliability degradation. As a result, it is easy to obtain a high integration density of circuit elements, high performance and high reliability.

  The semiconductor device 60 having such a technical effect can be manufactured, for example, by a method including a via hole forming step, a reaction product removing step, and a damascene wiring portion forming step described below in this order. Hereafter, each process is demonstrated with reference to drawings suitably.

<Via hole formation process>
In the via hole forming step, a via hole for forming a damascene wiring portion is formed in an insulating film (hereinafter referred to as “second insulating film”) that is a source of the second interlayer insulating film. This via hole can be formed before the wiring groove for forming the damascene wiring portion is formed in the second insulating film, or can be formed after the wiring groove is formed.

  FIG. 2A is a cross-sectional view schematically illustrating an example of the second insulating film. As shown in the figure, the second insulating film 45a is an inorganic film 40a (hereinafter referred to as a base film) of the liner film 40 (see FIG. 1) on the first interlayer insulating film 30 on which a desired number of contact plug portions 35 are formed. , "Second inorganic film 40a"), and then formed on the second inorganic film 40a.

  The first interlayer insulating film 30 forms a plurality of circuit elements on the semiconductor substrate 10, covers the circuit elements, and forms an inorganic film (hereinafter referred to as a “first film”) that serves as an etching stopper film 25 (see FIG. 1). An inorganic film) and an insulating film (hereinafter referred to as a “first insulating film”) that is the basis of the first interlayer insulating film 30; The through holes that are connected to the through holes and penetrate the first inorganic film are formed in this order. The first inorganic film is formed by, for example, chemical vapor deposition (CVD), and the first insulating film is formed by applying a desired inorganic material on the first inorganic film by, for example, CVD or physical vapor deposition (PVD). Then, the surface is planarized by chemical mechanical polishing (CMP). Each through hole is formed, for example, by selectively removing the first insulating film or the first inorganic film by anisotropic etching in a state where an etching mask having a predetermined shape is formed on the first insulating film. .

  Each contact plug portion 35 includes, for example, a conductive film (hereinafter referred to as “first conductive film”) serving as a base of the plug portion barrier metal layer and a conductive film (hereinafter referred to as “second conductive film”) serving as a plug body. Are formed in this order in each of the above-described through holes and on the first interlayer insulating film 30, and then the regions on the first interlayer insulating film 30 in each of the first conductive film and the second conductive film are subjected to CMP. It is formed by removing. The first conductive film is formed by, for example, CVD or PVD, and the second conductive film is formed by, for example, CVD.

  Each circuit element is formed on the semiconductor substrate 10 by various methods according to its structure, size, and the like. The field effect transistor 22 which is one of the circuit elements can be formed as follows, for example. First, an insulating film serving as a source of a gate insulating film 12 and a polycrystal are formed on a semiconductor substrate 10 in which a P-type well 3, an N-type well 5, and an element isolation region 7 are formed under a desired pattern on a silicon single crystal substrate 1. The silicon films are stacked in this order, and an etching mask having a desired shape is provided thereon, and then the insulating film and the polysilicon film are selectively etched to obtain the gate insulating film 12 and the polysilicon electrode.

  Next, a predetermined insulating film is formed so as to cover the gate insulating film 12 and the polysilicon electrode, and the insulating film is etched back to obtain the offset spacer films 20 and 20. Then, using these offset spacer films 20 and 20 as an ion implantation mask, N-type impurities are ion-implanted into the P-type well 3, and the impurities are activated by heat treatment to become extension regions 19a and 19b. A low concentration N-type impurity diffusion region is obtained.

  Next, a predetermined insulating film is formed on the semiconductor substrate 10 so as to cover the polysilicon electrode and the offset spacer films 20 and 20, respectively, and the insulating film is etched back so that the side wall spacers 21 and 21 are formed. Get. Then, using these sidewall spacers 21 and 21 as an ion implantation mask, N-type impurities are ion-implanted into the P-type well 3, and the impurities are activated by heat treatment, so that the N-type impurity diffusion regions 16a and 18a are formed. A high-concentration N-type impurity diffusion region is obtained as a base. At this time, the extension regions 19a and 19b are also formed. The N-type impurity implantation depth in the high-concentration N-type impurity diffusion region is deeper than the N-type impurity implantation depth in the low-concentration N-type impurity diffusion region described above.

  Thereafter, a desired refractory metal film made of nickel (Ni), cobalt (Co), platinum (Pt) or the like is formed by, for example, PVD so as to cover the polysilicon electrode and each high-concentration N-type impurity diffusion region. Forming and reacting the refractory metal film with the underlying polysilicon electrode and each high-concentration N-type impurity diffusion region by heat treatment, so that the upper portion of the polysilicon electrode and the upper portion of each high-concentration N-type impurity diffusion region are Metal silicide. Thereby, gate electrode 14 having polysilicon region 14a and metal silicide region 14b is obtained, source region 16 having N-type impurity diffusion region 16a and metal silicide region 16b, and N-type impurity diffusion region 18a and metal A drain region 18 having a silicide region 18b is obtained, and a field effect transistor 22 is obtained.

  The via hole for forming the damascene wiring portion is formed, for example, by providing an etching mask having a predetermined shape on the second insulating film 45a shown in FIG. 2A and using the second inorganic film 40a as an etching stopper. Is selectively patterned by anisotropic etching to form a through hole in the second insulating film 45, and then the second inorganic film 40a is selectively patterned using the etching mask as an etching mask. It is obtained by forming a through hole in the second inorganic film 40a. The through holes are formed in the second inorganic film 40a by, for example, dry etching, and conditions are set so that overetching corresponding to the thickness of the second inorganic film 40a occurs in consideration of manufacturing variations.

  As described above, the via hole for forming the damascene wiring part can be formed before the wiring groove for forming the damascene wiring part is formed in the second insulating film 45a, or can be formed after the wiring groove is formed. The formation of the wiring groove can be obtained by providing an etching mask having a predetermined shape on the second insulating film 45a and selectively patterning the second insulating film 45a by anisotropic etching. The liner film 40 is obtained by forming the through hole in the second inorganic film 40a as described above, and the second interlayer insulation is formed by forming the through hole and the wiring groove in the second insulating film 45a as described above. A membrane 45 is obtained.

Figure 2-2 is a sectional view showing an example of the second interlayer insulating film schematically, Figure 2-3 is an enlarged view of a region surrounded by one-dot chain line L ₂ in Figure 2-2. As shown in FIG. 2B, in the second interlayer insulating film 45, the via hole VH _{1 in} which the misalignment with respect to the corresponding contact plug portion 35 is caused and the via hole VH _{2 in} which the misalignment is not substantially caused. And are formed. Further, the wiring trench T is formed in a predetermined pattern. In the figure, the boundaries between the via holes VH ₁ and VH ₂ and the wiring trench T are indicated by a one-dot chain line L ₁ .

The above via hole VH ₁ is formed in a state that caused misalignment with respect to the contact plug portion 35 which is one end to the drain region 18 in contact with the two contact plugs 35 and 35, the via holes VH ₁ Although a part of the contact reaches the upper surface of the contact plug portion 35 and stops at the upper surface, the remaining portion penetrates into the first interlayer insulating film 30 to the same depth as the film thickness of the liner film 40. . Then, as shown in Figure 2-2 and Figure 2-3, the contact plug 35 corresponding to the via hole VH _1, on a region facing the via hole VH ₁ in the side surface upper portion of the plug portion the barrier metal layer 35b In addition, the reaction product generated in the above-described over-etching is redeposited to form the reaction product layer BP. Since the first interlayer insulating film 30 is made of an electrically insulating material, the reaction product layer BP has electrical insulation.

On the other hand, the via hole VH ₂ is formed without causing a substantial misalignment with respect to the contact plug part 35 of which the one end is in contact with the source region 16 of the two contact plug parts 35, 35. VH ₂ reaches the upper surface of the contact plug portion 35 and stops at the upper surface.

<Reaction product removal step>
In the reaction product removing step, the reaction product layer BP (see FIG. 2-2) generated in the via hole forming step is removed. Since the reaction product layer BP is more susceptible to wet etching than the first interlayer insulating film 30 (see FIG. 2-2), the reaction product layer BP is short using an etchant that can selectively wet-etch the first interlayer insulating film 30. By performing wet etching for a time, the reaction product layer BP can be easily removed. For example, when the first interlayer insulating film 30 is formed of silicon oxide, the reaction product layer BP is removed by performing wet etching for a short time using a hydrofluoric acid-based etchant.

FIG. 2-4 is a cross-sectional view schematically showing the second interlayer insulating film and each contact plug portion that have gone through the reaction product removal step. As shown in the figure, by removing the reaction product layer BP (see FIG. 2-3) in the reaction product removing step, the upper surface of the contact plug portion 35 corresponding to the via hole VH ₁ is partially partially exposed to the via hole VH _1. not only exposed to, (the upper side surface of the plug portion the barrier metal layer 35b) side upper also partially and thus exposed to the via hole VH _1.

Incidentally, the upper side surface of the contact plug portion 35 corresponding to the via hole VH _1, even when the first interlayer insulating film 30 in the shadow of the upper surface of the contact plug portion 35 has remained thin during the formation of the via hole VH _1, The remaining first interlayer insulating film can be removed by the wet etching described above to expose the upper side surface of the contact plug portion 35. At this time, the dimensions of the via holes VH ₁ and VH ₂ and the wiring trenches T do not change greatly because the etching time is short.

<Damascene wiring section formation process>
In the damascene wiring portion forming step, a damascene wiring portion is formed in the second interlayer insulating film. The damascene wiring portion includes, for example, a conductive film (hereinafter referred to as “third conductive film”) serving as a base of the wiring portion barrier metal layers 52 and 56 (see FIG. 1) in each of the via holes VH ₁ and VH ₂ described above. After filling each via hole VH ₁ , VH ₂ and each wiring trench T with copper formed in each wiring trench T and on the second interlayer insulating film 45 and deposited on the third conductive film by electrolytic plating, Of the three conductive films, the region located on the second interlayer insulating film 45 and the copper overflowing on the second interlayer insulating film 45 are removed by CMP.

  FIG. 2-5 is a cross-sectional view schematically illustrating an example of a damascene wiring portion. The figure shows a first damascene wiring portion 53 that has undergone misalignment and a second damascene wiring portion 57 that has not substantially caused misalignment. Since the reaction product layer BP (see FIG. 2-2) is removed in the reaction product removal step described above, the first damascene wiring portion 53 is a contact plug portion corresponding to the first damascene wiring portion 53. 35 is in partial contact with each of the top and side surfaces of 35.

  Thereafter, a liner film and an interlayer insulating film are repeatedly laminated in this order on the second interlayer insulating film 45, and a plurality of wirings and a plurality of via contacts are formed on each interlayer insulating film, thereby forming the semiconductor film 10 on the semiconductor substrate 10. A desired multilayer wiring portion is constructed. The semiconductor device 60 shown in FIG. 1 is obtained by constructing the multilayer wiring portion in this way.

Embodiment 2. FIG.
In the semiconductor device of the present invention, when a liner film is interposed between the first interlayer insulating film and the second interlayer insulating film, the via contact region in the first damascene wiring portion has a depth of about three times the thickness of the liner film. It is also possible to penetrate the first interlayer insulating film.

FIG. 3 is a cross-sectional view schematically showing an example of a semiconductor device having a deep penetration depth of the via contact region into the first interlayer insulating film in the first damascene wiring portion. In the semiconductor device 70 shown in the figure, the region R ₂ in the via contact region 61 b in the first damascene wiring part 63 penetrates into the first interlayer insulating film 30 to a depth of about three times the film thickness of the liner film 40. . Since the other configuration of the semiconductor device 70 is the same as that of the semiconductor device 60 shown in FIG. 1, among the components shown in FIG. 3, the same components as those shown in FIG. The same reference numerals as those used in FIG.

In the semiconductor device 70 having the above-described configuration, a region located around the region R _{2 in} the wiring portion barrier metal layer 62 constituting the first damascene wiring portion 63 corresponds to the first damascene wiring portion 63. The contact area with the upper part of the side surface of the contact plug portion 35 is larger than that in the semiconductor device 60 shown in FIG. For this reason, in the semiconductor device 70, even when compared with the semiconductor device 60, when the width of each damascene wiring portion is reduced, the electrical resistance between the damascene wiring portion and the contact plug portion increases. It is easy to suppress degradation and reliability degradation. It is easier to obtain a circuit element with a high integration density, high performance and high reliability.

When the penetration depth of the region R ₂ into the first interlayer insulating film 30 exceeds three times the film thickness of the liner film 40, the wiring groove in which the wiring region 61a of the first damascene wiring part 63 is formed is formed. Since the shoulder is easily dropped, the penetration depth is preferably about three times or less the thickness of the liner film 40. Further, in the case where the inter-wiring capacitance or wiring resistance in the semiconductor device 70 is to be approximately the same as the inter-wiring capacitance or wiring resistance in the semiconductor device 60, the region R in the first damascene wiring section 63 shown in FIG. _The depth of penetration of the first interlayer insulating film 30 into the first interlayer insulating film 30 shown in FIG. 1 is greater than the depth of penetration of the region R ₂ into the first interlayer insulating film 30 in the first damascene wiring portion 53 shown in FIG. It is preferable to make the film thickness of the second interlayer insulating film 45 in FIG. 2 smaller than the film thickness of the second interlayer insulating film 45 in the semiconductor device 60.

Embodiment 3 FIG.
In the semiconductor device of the present invention, the second interlayer insulating film can be directly laminated on the first interlayer insulating film without a liner film. FIG. 4 is a cross-sectional view schematically showing an example of a semiconductor device in which a second interlayer insulating film is directly stacked on the first interlayer insulating film. The semiconductor device 80 shown in the figure is the same as the semiconductor device 70 shown in FIG. 3 except that the second interlayer insulating film 45 is directly laminated on the first interlayer insulating film 30 without a liner film. It has a configuration. In FIG. 4, the same reference numerals as those used in FIG. 3 are assigned to the components common to those shown in FIG.

  In the semiconductor device 80 having such a configuration, similarly to the semiconductor device 70 shown in FIG. 3, when the width of each damascene wiring portion is reduced, the electrical resistance between the damascene wiring portion and the contact plug portion is reduced. It is easy to suppress performance degradation and reliability degradation due to the increase. It is easier to obtain a circuit element with a high integration density, high performance and high reliability. In addition, it is easier to reduce the wiring capacitance and the wiring interlayer capacitance than the semiconductor devices 60 and 70 described in the first embodiment or the second embodiment. Further, since the liner film is not formed on the first interlayer insulating film 30, the number of steps is reduced and the process flow is facilitated.

  As in the semiconductor device 70 described in the second embodiment, the penetration depth of the via contact region 61b into the first interlayer insulating film 30 in the semiconductor device 80 is the wiring groove in which the wiring region 61a is formed. Appropriately selected so that the shoulder does not fall.

Embodiment 4 FIG.
In the semiconductor device of the present invention, a cap layer formed of a conductive material can be interposed between the damascene wiring portion and the contact plug corresponding to the damascene wiring portion. The cap layer is formed between the first damascene wiring portion and the contact plug corresponding to the first damascene wiring portion, and between the second damascene wiring portion and the contact plug corresponding to the second damascene wiring portion, respectively. Be placed.

  FIG. 5 is a cross-sectional view schematically showing an example of a semiconductor device having the cap layer described above. In the semiconductor device 90 shown in the figure, a first cap layer 83a is interposed between the first damascene wiring section 63 and the contact plug section 35 corresponding to the first damascene wiring section 63, and the second damascene wiring section 57 and A second cap layer 83 b is interposed between the contact plug portion 35 corresponding to the second damascene wiring portion 57. Among the components shown in FIG. 5, those having the same functions as those shown in FIG. 4 are denoted by the same reference symbols as those used in FIG.

Prior to the formation of the wiring portion barrier metal layer 62 constituting the first damascene wiring portion 63, the first cap layer 83a is formed in the contact plug portion 35 (first plug) exposed in the via hole VH ₁ (see FIG. 2-4). 1 corresponding to one damascene wiring portion 63) and selectively formed on the upper surface and the upper side surface. The first damascene wiring part 63 is in contact with the first cap layer 83a so as to cover the first cap layer 83a.

Since the vertical cross section of the via hole VH ₁ is inverted mesa shape that corresponds to the vertical cross-section of the via contact portion 61b, the total area of the exposed surface of the first cap layer 83a which is exposed to the via hole VH ₁ is the first It is wider than the total area of the exposed surface of the contact plug portion 35 exposed to the via hole VH ₁ before the one cap layer 83a is provided. Therefore, the contact area between the first damascene wiring portion 63 and the first cap layer 83a is such that the first damascene wiring portion 63 when the first damascene wiring portion 63 is formed without providing the first cap layer 83a and the above-described area. The contact area with the contact plug portion 35 is large.

On the other hand, the second cap layer 83b is exposed to the via plug VH ₂ (see FIG. 2-4) prior to the formation of the wiring part barrier metal layer 56 constituting the second damascene wiring part 57. It is selectively formed on the upper surface of (corresponding to the second damascene wiring part 35). The second damascene wiring part 57 is in contact with the second cap layer 83b so as to cover the second cap layer 83b.

Since the vertical cross-sectional shape of the via hole VH ₂ is an inverted mesa shape corresponding to the vertical cross-sectional shape of the via contact portion 55b, the area of the upper surface of the second cap layer 83b is equal to the contact before the second cap layer 83b is provided. It is wider than the area of the upper surface of the plug part 35. Therefore, the contact area between the second damascene wiring portion 57 and the second cap layer 83b is the same as that of the second damascene wiring portion 63 when the second damascene wiring portion 57 is formed without providing the second cap layer 83b. The contact area with the contact plug portion 35 is large.

  As described above, in the semiconductor device 90, when the contact area between each damascene wiring portion 63, 57 and the contact plug portion 35 corresponding to the damascene wiring portion 63, 57 is not the first cap layer 83a or the second cap layer 83b. Since it is wider than the semiconductor device 80 shown in FIG. 4, the electrical resistance between the damascene wiring portion and the contact plug portion increases when the width of each damascene wiring portion is reduced. In particular, it is easy to suppress a decrease in performance and a decrease in reliability. It is easier to obtain a circuit element with a high integration density, high performance and high reliability.

  In such a semiconductor device 90, for example, the cap layer forming process is performed after the reaction product removing process described in the first embodiment is performed, and then the damascene wiring section forming process described in the first embodiment is performed. Is obtained.

FIG. 6 is a cross-sectional view schematically showing an example of the cap layer formed in the cap layer forming step. As shown in the figure, each of the cap layers 83a and 83b is selectively formed on the surface of the contact plug portion 35 exposed on the corresponding via holes VH ₁ and VH ₂ . For example, when the cap layers 83a and 83b are to be formed of tungsten silicide, the cap layers 83a and 83b are formed by applying a CVD method using tungsten hexafluoride (WF ₆ ) and silane gas as source gases. Can be selectively formed at a desired location. 6 that are the same as those shown in FIG. 2-4 or FIG. 4 are assigned the same reference numerals as those used in FIG. 2-4 or FIG. The description is omitted.

  As mentioned above, although four embodiments of the semiconductor device of the present invention have been described, the present invention is not limited to these embodiments as described above. For example, the second damascene wiring portion is not an essential constituent element, and all the damascene wiring portions formed in the second interlayer insulating film may be the first damascene wiring portion.

  In addition, the size of the via contact region in the individual damascene wiring section when viewed from the bottom is not necessarily smaller than the dimension of the upper surface of the contact plug section corresponding to the damascene wiring section, and the corresponding contact plug. It can be the same size as the top surface of the part, or can be larger than the top surface size of the corresponding contact plug part.

  FIG. 7 is a cross-sectional view schematically showing an example of a semiconductor device in which the size of the via contact region in each damascene wiring portion when viewed from the bottom is larger than the size of the upper surface of the contact plug portion corresponding to the damascene wiring portion. It is. In the semiconductor device 100 shown in the figure, the size of the first damascene wiring portion 93 formed in the second interlayer insulating film 45 when viewed from the bottom and the via contact region of the second damascene wiring portion 97. The dimensions when the bottom surface view of 95b is designed to be larger than the dimensions of the upper surface of the contact plug portion 35 corresponding to the damascene wiring portions 93 and 97, respectively.

  The first damascene wiring portion 93 is in partial contact with each of the upper surface and upper side surface of the corresponding contact plug portion 35. On the other hand, the second damascene wiring portion 97 is in contact with the entire upper surface of the corresponding contact plug portion 35 and is in contact with the entire periphery of the upper side surface. 7 that are the same as those shown in FIG. 1 are assigned the same reference numerals as those used in FIG. 1 and description thereof is omitted. The semiconductor device of the present invention can be variously changed, modified, combined, etc. in addition to those described above.

It is a fragmentary sectional view showing roughly an example of a semiconductor device of the present invention. It is sectional drawing which shows roughly an example of the 2nd insulating film which is formed in manufacturing the semiconductor device of this invention, and becomes the origin of the 2nd interlayer insulating film. It is sectional drawing which shows roughly an example of the 2nd interlayer insulation film formed in manufacturing the semiconductor device of this invention. It is an enlarged view of the area | region enclosed with the dashed-dotted line in FIG. It is sectional drawing which shows schematically the 2nd interlayer insulation film and each contact plug part which passed through the reaction product removal process performed in manufacturing the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the damascene wiring part formed in the damascene wiring part formation process performed in manufacturing the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the penetration depth to the 1st interlayer insulation film of the via contact area | region in a 1st damascene wiring part among the semiconductor devices of this invention. It is sectional drawing which shows roughly an example of what laminated | stacked the 2nd interlayer insulation film directly on the 1st interlayer insulation film among the semiconductor devices of this invention. It is sectional drawing which shows roughly an example of what interposed the cap layer between the damascene wiring part and the contact plug corresponding to this damascene wiring part among the semiconductor devices of this invention. FIG. 6 is a cross-sectional view schematically showing an example of a cap layer formed in a cap layer forming process performed when manufacturing the semiconductor device shown in FIG. 5. 1 schematically shows an example of a semiconductor device according to the present invention in which a size of a via contact region in each damascene wiring portion when viewed from the bottom is larger than that of a contact plug portion corresponding to the damascene wiring portion. It is sectional drawing.

Explanation of symbols

10 Semiconductor substrate 22 Field effect transistor (circuit element)
30 1st interlayer insulation film 35 Contact plug part 35a Plug body 35b Plug part barrier metal layer 40 Liner film 45 2nd interlayer insulation film 51, 61, 91 Damascene body 51a, 61a, 91a Wiring area 51b, 61b, 91b Via contact area 52, 62, 92 Wiring part barrier metal layer 53, 63, 93 First damascene wiring part 55, 95 Damascene main body 55a, 95a Wiring area 55b, 95b Via contact area 56, 96 Wiring part barrier metal layer 57, 97 Second damascene Wiring unit 60, 70, 80, 90, 100 Semiconductor device 83a First cap layer 83b Second cap layer

Claims (6)

A semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of circuit elements, and the first interlayer insulating film penetrating A plurality of contact plug parts, a second interlayer insulating film laminated on the first interlayer insulating film, and a plurality of damascene wiring parts formed on the second interlayer insulating film, Each of the units is a semiconductor device connected to a predetermined circuit element formed on the semiconductor substrate via a predetermined contact plug unit,
The plurality of damascene wiring portions include at least one first damascene wiring portion that is in partial contact with the upper surface and the upper side surface of the corresponding contact plug portion, respectively.   The plurality of damascene wiring portions include at least one second damascene wiring portion that is in contact with the entire top surface of the corresponding contact plug portion or in contact with the entire top surface of the corresponding contact plug portion. 2. The semiconductor device according to 1. Each of the plurality of contact plug portions includes a plug body, and a plug portion barrier metal layer covering a side surface and a bottom surface of the plug body,
Each of the plurality of damascene wiring portions includes a damascene body including a wiring region and a via contact region extending from the lower surface of the wiring region to the first interlayer insulating film side, and wiring covering a side surface and a bottom surface of the damascene body A barrier metal layer,
The semiconductor device according to claim 1, wherein: A liner film interposed between the first interlayer insulating film and the second interlayer insulating film;
The via contact region penetrates the liner film;
The semiconductor device according to any one of claims 1 to 3.   The via contact region in the first damascene wiring portion penetrates into the first interlayer insulating film to a depth corresponding to 1 to 3 times the film thickness of the liner film. Semiconductor device. A semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of circuit elements, and the first interlayer insulating film penetrating A plurality of contact plug parts, a second interlayer insulating film laminated on the first interlayer insulating film, and a plurality of damascene wiring parts formed on the second interlayer insulating film, Each of the units is a semiconductor device connected to a predetermined circuit element formed on the semiconductor substrate via a predetermined contact plug unit,
A cap layer formed of a conductive material and interposed between each of the plurality of contact plug portions and a damascene wiring portion corresponding to the contact plug portion;
The plurality of damascene wiring portions have cap layers that partially cover the upper surface and upper side surfaces of the contact plug portions between the corresponding contact plug portions, and the cap layers so as to cover the cap layers. Including at least one first damascene wiring portion in contact with the layer;
A semiconductor device.

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