JP2000049301A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a capacitor pattern suited for phase shift lithography and to secure a capacitor planar area by laying out the capacitor pattern at an equal interval twodimensionally with proper periodicity. SOLUTION: A polycrystalline silicon 3 is deposited and a silicon nitride 4 is deposited. After gate machining, an impurity is implanted, thus forming a diffused layer 17 of a memory cell region and a peripheral circuit region. A silicon nitride 41 is deposited. A silicon oxide film 5 is deposited, and the oxide film is left on a gate electrode. A plug contact at the lower portion of a bit line is opened. A silicon nitride 42 is deposited, and a contact hole is opened. A contact is opened at the peripheral circuit region, titanium and titanium nitride are deposited, tungsten 8 is deposited, and a plug is formed. A silicon oxide film 501 is deposited and a trench 9 is dug for laying out at an equal interval twodimensionally, thus making a layout out a capacitor pattern suitable for phase shift lithography and hence securing a capacitor planar area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device. In particular, a high-performance dynamic random access memory (DR) which is highly integrated and suitable for embedding with logic.
AM).

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM), which has been improving the integration at a rate of four times in three years,
The demand is growing ever more, driven by the explosive sales of personal computers in recent years. Already, 16
Mass production of megabits has passed its peak, and development for mass production of 64 megabits using 0.20 μm, which is the next-generation microfabrication technology, is underway.

Many of the DRAM memory cells that have been commercialized to date have a so-called COB (Capacitor over bitline) structure in which a capacitor is formed above a bit line. This structure has a feature that the surface area can be maximized since there is no factor that hinders the layout when forming the capacitor.

[0004] Another typical cell structure is a CUB (Capacitor under bi-layer) in which a capacitor is formed below a bit line.
tline) structure. In the case of the CUB structure, since it is necessary to lay out the capacitor between the bit line contacts, there is a problem that the capacitor surface area is smaller than that of the COB structure, and as a result, the capacitor height is increased.

However, on the other hand, as shown in FIG.
The bit line is connected to the first wiring layer (15016/16 /
15) Since it can be formed at the same time, there is a great advantage that the number of masks is reduced by at least one compared with the COB structure, and the process can be simplified. Here, in FIG. 2, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 3 is polycrystalline silicon,
41 is a silicon nitride film, 5,501,502,
503 is an interlayer insulating film, 7 is a capacitor plug, 803 is tungsten, 10 is a capacitor lower electrode, 11 is a plate electrode, 15, 1501 are titanium nitride, 16
Is aluminum, and 17 is an impurity diffusion layer.

In fact, for a 16-megabit DRAM, Micron Corporation of the United States has realized a reduction in manufacturing cost by adopting a CUB structure. In the future, if the manufacturing cost reduction is the highest priority in the DRAM, the CUB structure may become more mainstream than the COB structure.

[0007]

Problems of the CUB cell will be described with reference to the drawings. FIG. 3 shows a mask layout of a typical CUB type cell. Although the layout of the capacitor pattern 20 is cyclical, it must be laid out with the bit line contact 21 therebetween.
In the direction perpendicular to 9 (horizontal direction in the figure), the intervals between adjacent capacitor patterns are not all the same. From the viewpoint of lithography resolution, this irregularity will be a problem in the future in the sense that the highest performance cannot be obtained in the extreme where miniaturization has advanced.

Next, this will be specifically described. The most suitable lithography for mass production is still optical lithography, and there are active studies to extend this resolution limit.
For achieving sub-0.2 micron dimensions, the most promising technique is called phase shift lithography.
This achieves a pattern size smaller than the resolution limit by causing lights having phases shifted by 180 degrees to interfere with each other. As is apparent from this principle, phase shift lithography is most effective for simple and periodic patterns.

In other words, in order to use phase shift lithography most effectively and obtain its critical dimension, the periodicity of the pattern is extremely important. In this sense, the capacitor pattern shown in FIG. 3 is not necessarily suitable for phase shift lithography, and it is not a layout that is suitable for maximizing the surface area of the capacitor pattern. .

An object of the present invention is to solve this problem, that is, to propose a method of manufacturing a CUB type DRAM which enables a layout of a capacitor pattern suitable for phase shift lithography. At the same time, in response to the increase in capacitor height, which is a serious problem with miniaturization,
It is intended to propose a method of manufacturing a DRAM which ensures a sufficient process margin.

[0011]

FIG. 1 shows a mask layout pattern according to the present invention for solving the above-mentioned problems. In the present invention, the capacitor patterns 20 are two-dimensionally laid out at regular intervals and with good periodicity. As a result, the capacitor pattern 20 is suitable for phase shift lithography, and it is possible to ensure the maximum capacitor plane area.

What has made this possible is the arrangement of the bit line contacts 24. In FIG. 3, since the bit line contacts are laid out between the adjacent capacitors, the capacitor interval in this portion is widened. To avoid this problem, in the present invention, the bit line contacts are shifted downward by a half pitch. As a result, the intervals between adjacent capacitors could be made equal.

Specifically, in order to achieve this object, in the present invention, the bit line plug has a structure in which two plugs are connected. By making the lower plug into a slot shape, the diffusion layer to which the bit line is connected is drawn out laterally, and the upper plug is connected to the drawn out portion.

In the present invention, the steps are complicated because of the laminated plug structure. However, from another point of view, this is a structure that suppresses a decrease in process margin due to a capacitor height that increases with miniaturization, and is an inevitable structure of a future DRAM.

[0015]

(Embodiment 1) Hereinafter, embodiments of the present invention will be described in detail while following the manufacturing steps. First, a semiconductor substrate 1 is prepared, and MOSFETs used for memory cells and peripheral circuits are formed. For this purpose, first, an inter-element isolation oxide film 2 for isolating the MOSFET is formed on the surface of the semiconductor substrate 1 by using a known selective oxidation method or a shallow trench isolation method (FIG. 4). In this embodiment, the surface can be flattened,
The shallow groove separation method was used. Therefore, first, a separation groove having a depth of about 0.3 μm is formed in the substrate by using a known dry etching method, and after removing the damage caused by the dry etching on the groove side wall and the bottom surface, a known CVD (Chemical Vapor Deposition) method is used. A silicon oxide film is deposited to a thickness of about 0.7 μm using the method described above, and the oxide film in a portion other than the groove is selectively polished by a well-known CMP (Chemical Mechanical Polishing) method to fill the groove. Only the oxide film 2 is left.

FIG. 5 shows a layout pattern of the element isolation region layer at this time. The element formation region 18 has a linear pattern as shown in FIG. 5 from the viewpoint of lithographic resolution and reduction of the parasitic diffusion layer capacitance. Next, though not shown in the figure, two different conductive wells were formed by implanting high-energy impurities.

Further, after cleaning the surface of the semiconductor substrate, a gate oxide film of the MOSFET was grown by a known thermal oxidation method. The oxidation temperature is 800 degrees, and the thickness of the oxide film is 6 nm. A gate electrode is formed on the surface of the gate oxide film. In the present embodiment, a polycrystalline polysilicon gate was used, but as a low-resistance gate, a barrier metal was interposed therebetween.
Of course, it is also possible to use a polymetal gate which is a laminated structure of metal and polycrystalline silicon.

First, polycrystalline silicon 3 containing a high concentration of impurities is deposited to a thickness of 100 nm, and then silicon nitride 4 is applied to apply a self-aligned contact process.
Deposit 00 nm. After the gate is processed by a lithography process and a dry etching process, impurities are implanted using the gate electrode and the resist as a mask to form a diffusion layer 17 in the memory cell region and the peripheral circuit region.

Specifically, 2 × 10 ¹⁵ arsenic is used for the switching transistor of the memory cell and the n-type MOSFET of the peripheral circuit.
/ Cm ² and the same amount of boron was implanted in the p-type MOSFET of the peripheral circuit. And 10 at 950 degrees
The diffusion layer was formed by heating the substrate under the condition of seconds and activating the implanted impurities. In this embodiment, a schematic view of a so-called single drain structure in which a diffusion layer is formed by one ion implantation step is drawn. However, an electric field relaxation type diffusion layer formed by two ion implantations can be used. It goes without saying that it is possible.

Subsequently, in order to apply a self-aligned contact in the memory cell region, as shown in FIG.
A 0 nm silicon nitride 41 is deposited by a CVD method. FIG. 7 shows a layout diagram of word lines in the memory array area. In the figure, 18 is an element isolation region and 19 is a word line.

Next, a silicon oxide film 5 is formed on the entire surface to a thickness of 0.1 mm.
7 μm is deposited, and is deposited using a known CMP method.
Surface irregularities caused by the gate electrode are flattened, and an oxide film of about 0.1 μm is left on the gate electrode. Subsequently, an opening is formed in the lower bit line plug contact in the memory cell region by a lithography and dry etching process. At this time, in order to prevent the gate electrode from being exposed, the oxide film was processed under the condition of high selection with respect to silicon nitride. Polysilicon containing a high concentration of impurities was buried in the contact to form a plug 6 as shown in FIG.

FIG. 9 shows a bit line lower plug contact 2.
2 shows a layout diagram. What is characteristic is that the shape of the contact is not a square but a so-called slot shape. This structure makes it possible to shift the position of a bit line contact to be formed later.

Subsequently, as shown in FIG.
m silicon nitride 42 is deposited by a known CVD method, and a contact hole for a capacitor in the memory array portion is opened by a lithography process and a dry etching process. At this time, the silicon oxide film was etched under the condition of a so-called self-aligned contact, that is, under the condition of high selection with respect to the silicon nitride 41, in order to avoid exposing the gate electrode as a condition of the dry etching. Polysilicon containing a high concentration of impurities is embedded in the contact, and a plug 7 is formed by a known CMP method.
become that way.

FIG. 11 shows a layout pattern of the storage node contact 23. Next, as shown in FIG. 12, a contact is opened in the peripheral circuit region, titanium is deposited to a thickness of 10 nm, titanium nitride is deposited to a thickness of 20 nm, and tungsten 8 is deposited to a thickness of 100 nm in order to reduce the contact resistance with the diffusion layer.
Then, a plug is formed using a known CMP method.

To form a three-dimensional capacitor electrode, a silicon oxide film 501 is deposited as an interlayer insulating film to a thickness of 700 nm.
As shown in FIG. Further, a trench 9 was dug by a lithography and dry etching process, as shown in FIG.

FIG. 15 shows a layout diagram of the capacitor at this time. It is laid out two-dimensionally at equal intervals and with good periodicity, and is suitable for applying phase shift lithography.

Next, the lower electrode 10 of the capacitor is formed.
30 nm of polycrystalline silicon containing a high concentration of impurities is deposited. To increase the surface area of this polycrystalline silicon,
A capacitor subjected to a process for forming irregularities was also manufactured. By providing the irregularities, the surface area can be doubled or more, and the storage capacity can be further increased. For the lower electrode 10 of the capacitor, in addition to polycrystalline silicon, tungsten or titanium nitride, or platinum or the like was used to correspond to a high dielectric film such as BST or PZT or a ferroelectric film. .

Next, the silicon oxide film 50 is formed by the CMP method.
1 Only the polycrystalline silicon on the upper surface is removed, and a lower electrode 10 made of polycrystalline silicon is embedded in the silicon oxide film.
The capacitor lower electrode is separated for each memory cell, as shown in FIG.

Next, on the surface of the capacitor lower electrode 10,
A capacitor insulating film (not shown) is formed, and a plate electrode 11 is formed over the entire surface of the memory cell so as to cover the capacitor insulating film. In the present embodiment, a laminated film of a tantalum pentoxide film and a silicon oxide film was used as the capacitor insulating film, and a 3 nm capacitor insulating film was realized in terms of the silicon oxide film thickness.

The capacitor insulating film is not limited to this, and a conventional laminated film of a silicon oxide film and a silicon nitride film, or a ferroelectric film with a lower electrode made of platinum or the like can also be used. It is. Although various metals can be used for the plate electrode 11, a titanium nitride film is used for a capacitor insulating film using a laminated film of a tantalum pentoxide film and a silicon oxide film, and a silicon oxide film and a silicon oxide film are used for the capacitor electrode. A polycrystalline silicon film was used for a film using a nitride film and a platinum film was used for a film using a ferroelectric film.

Next, interlayer oxide film 5 covering plate electrode 11
02 is formed as shown in FIG. The bit line contact holes 12 in the memory array and the contact holes 13 in the peripheral circuit region are opened by lithography and dry etching processes, as shown in FIG.

FIG. 20 is a layout diagram of the bit line contact 12 in the memory array. The bit line contact is connected to the lower plug 6 so as to be electrically connected to the lower plug 6.
It is arranged symmetrically at the center of the region between the two storage nodes.

Next, in order to prevent an electrical short circuit between the bit line and the plate electrode, a side wall insulating film 1 is formed in the contact hole.
4 is formed. Further, a tungsten plug 801 was formed, as shown in FIG. Subsequently, a thickness of 50 nm
Of titanium nitride 15, aluminum 16 having a thickness of 200 nm, and titanium nitride 1501 having a thickness of 50 nm are sequentially deposited and processed as a bit line in a memory array and as a wiring layer in a peripheral circuit, as shown in FIG. . Of course, copper having a lower resistance can be used instead of aluminum 16. FIG. 23 shows a layout diagram of the bit line 25 in the memory array.

Next, if necessary, a silicon oxide film 503 is deposited as an interlayer insulating film to a thickness of 500 nm and flattened by a known CMP method. A tungsten plug 802 is formed, and titanium nitride 1503 / aluminum 160
An uppermost layer wiring made of 1 / titanium nitride 1502 was formed, and the semiconductor memory device of the present invention shown in FIG. 24 was completed. Since the wiring in the uppermost layer has a very low density, that is, a very large dimension, a lenient design rule can be used.

As described above, in this embodiment, the bit line plug has a connection structure of a plurality of plugs in order to cope with an increase in the height of the capacitor, and the layout of the capacitor pattern is suitable for phase shift lithography by utilizing the structure. It is possible to optimize the position of the opening of the bit line contact hole so as to achieve the above.

(Embodiment 2) This embodiment relates to a contact opening method in a peripheral circuit. In the first embodiment, the bit line contacts of the memory array and the contacts of the peripheral circuits are formed simultaneously to simplify the process. As a result, the side wall oxide film 1 necessary only in the memory array
4 will also be formed in the peripheral circuit contact. This leads to an increase in the plug resistance and deteriorates circuit performance. Therefore, in this embodiment, the memory array and the plug of the peripheral circuit are formed separately. In this way, as shown in FIG. 25, no sidewall oxide film was formed on the plug of the peripheral circuit, and a higher performance semiconductor memory device was obtained.

(Embodiment 3) This embodiment relates to the formation of bit line plugs in a memory array. Since the size of the bit line contact in the memory array is the minimum processing size, the ratio between the plug height and the opening diameter, the so-called plug aspect ratio, is much larger than the peripheral circuit contact, making it difficult to form the plug . This embodiment, which shows a final cross-sectional view in FIG. 26, solves this problem. That is, polycrystalline silicon 602 containing impurities at a high concentration was used as the material of the bit line plug. Polycrystalline silicon used in Example 1 or 2 had much better coverage than tungsten and could avoid the above problems.

[0038]

In a DRAM having a so-called CUB type cell in which a capacitor is formed below a bit line, it is necessary to open a bit line contact between the capacitors, so that the periodicity of the layout pattern of the capacitor is required. However, there is a problem that the flat area of the capacitor cannot be sufficiently secured lithographically. At the same time, in the DRAM, there is also a problem that the height of the capacitor increases as the miniaturization progresses, and the process becomes difficult.

According to the present invention, by employing the plug-on plug structure, the difficulty of the process accompanying the increase in the height of the capacitor is eased. At the same time, it is possible to make the capacitor pattern a layout suitable for phase shift lithography, so that there is an effect that a maximum capacitor plane area can be secured in a CUB type DRAM.

[Brief description of the drawings]

FIG. 1 is a mask layout diagram of a CUB type DRAM of the present invention.

FIG. 2 is a cross-sectional view of a conventional CUB type DRAM.

FIG. 3 is a mask layout diagram of a conventional CUB type DRAM.

FIG. 4 is a cross-sectional view illustrating a manufacturing step of the semiconductor memory device of the present invention.

FIG. 5 is a layout diagram of an element isolation region of the semiconductor memory device of the present invention.

FIG. 6 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

FIG. 7 is a word line layout diagram of the semiconductor memory device of the present invention.

FIG. 8 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

FIG. 9 is a layout diagram of a lower bit line plug of the semiconductor memory device of the present invention.

FIG. 10 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention.

FIG. 11 is a capacitor contact layout diagram of the semiconductor memory device of the present invention.

FIG. 12 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 13 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 14 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

FIG. 15 is a capacitor layout diagram of the semiconductor memory device of the present invention.

FIG. 16 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention;

FIG. 17 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention.

FIG. 18 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

FIG. 19 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 20 is a layout diagram of an upper bit line plug of the semiconductor memory device of the present invention.

FIG. 21 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 22 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 23 is a bit line layout diagram of the semiconductor memory device of the present invention.

FIG. 24 is a cross-sectional view of a semiconductor memory device of the present invention.

FIG. 25 is a cross-sectional view of a semiconductor memory device of the present invention.

FIG. 26 is a cross-sectional view of a semiconductor memory device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation oxide film, 3 ... Polycrystalline silicon, 4,41,42 ... Silicon nitride film,
5, 501, 502, 503: interlayer insulating film, 6: lower bit line plug, 7: capacitor plug, 8, 801, 8
02, 803: tungsten, 9: capacitor forming trench, 10: capacitor lower electrode, 11: plate electrode, 12: upper bit line plug contact hole, 13: peripheral circuit contact hole, 14: side wall insulating film, 15, 150
1,1502,1503 ... titanium nitride, 16,
1601 ... aluminum, 17 ... impurity diffusion layer, 18 ...
Element isolation region, 19: word line, 20: capacitor, 2
1: bit line contact, 22: lower bit line plug,
23: Capacitor plug, 24: Upper bit line plug.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Yamanaka 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term in Hitachi Central Research Laboratory 5F083 AD24 AD48 JA14 JA15 JA36 JA37 JA38 JA39 JA40 JA56 KA05 LA21 MA02 MA06 MA17 MA18 MA19 MA20 PR01 PR10 PR29 PR40 PR43 PR44 PR45 PR46 PR53 PR54 PR55 PR56 ZA01

Claims (8)

[Claims] 1. A memory cell array section in which a plurality of memory cells each including a capacitor for storing electric charges and a switching transistor for reading information are arranged on a main surface of a semiconductor substrate;
In a semiconductor memory device in which a peripheral circuit composed of a plurality of MISFETs is arranged around the memory cell array section, one of diffusion layers of a switching transistor of the memory cell is provided.
A semiconductor memory device, wherein one of the conductors is connected to a data line, and the conductor connecting the diffusion layer and the data line has a stacked structure of a plurality of conductors. 2. The semiconductor device according to claim 1, wherein a conductor connecting the diffusion layer of the memory array portion to the data line and a conductor connecting the MISFET of the peripheral circuit portion to the wiring layer are made of the same material. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein at least one of the conductors connecting the diffusion layer of the memory array and the data lines is made of polycrystalline silicon. 4. The semiconductor memory device according to claim 1, wherein at least one of the conductors connecting the diffusion layer of the memory array and the data line is made of tungsten or titanium nitride. 5. The semiconductor memory device according to claim 1, wherein said data line in said memory cell region is arranged above said capacitor. 6. The memory cell region according to claim 1, wherein at least one of a plurality of conductors connecting said data line and said diffusion layer is covered with an insulator. The semiconductor memory device according to any one of the above. 7. The semiconductor memory device according to claim 1, wherein said capacitors in said memory cell region are arranged at equal intervals in a two-dimensional direction. 8. The semiconductor memory device according to claim 1, wherein a contact to said bit line in said memory cell region is surrounded by four capacitors adjacent to said contact. .