JPH1168064A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a contact hole, which connects a bit line and a storage node to source/drain regions in a DRAM memory cell to be easily aligned in lithography and formed to be high in reliability. SOLUTION: A polysilicon film 18 is formed under interlayered insulating films 19 and 23, holes are bored in the interlayered insulating films 19 and 23 making the polysilicon film 18 serve as a stopper to form contact holes 20 and 24 for a bit line 22 and a storage node 26, then the polysilicon film 18 is removed, and sidewall oxide films 21 and 25 are formed on the inner walls of the contact holes 20 and 24 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a contact structure for connecting an electrode layer to a semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 27 is a sectional view showing a structure of a conventional DRAM memory cell. In the figure, reference numeral 1 denotes a semiconductor substrate made of silicon single crystal or the like (hereinafter, referred to as substrate 1);
Is a field insulating film for separating the elements, 4 is formed on the substrate 1 via the gate oxide film 3, and a gate electrode serving as a word line. Here, the gate oxide film 3 is a thin film and is not shown for convenience. 5 is an oxide film as an insulating film formed on the surface of the gate electrode 4, 6 is a source / drain region as an impurity diffusion layer formed on both sides of the gate electrode 4, 7
Is a side wall oxide film as a side wall insulating film formed on the side surface of the gate electrode 4. 8 is an interlayer insulating film, 9 is a bit line contact hole provided in the interlayer insulating film, 10 is a bit line connected to one of the source / drain regions 6 via the bit line contact hole 9,
11 is a second interlayer insulating film, 12 is a second interlayer insulating film 11
A storage node contact hole provided in the interlayer insulating film 8; a storage node 13 serving as a lower electrode of a capacitor connected to the other of the source / drain regions 6 via the storage node contact hole 12;
14 is a dielectric film of the capacitor, and 15 is an upper electrode of the capacitor.

A method of manufacturing a conventional DRAM memory cell having the above structure will be described below with reference to FIG. First, after forming the field insulating film 2 on the substrate 1,
A polysilicon film serving as a gate electrode 4 is formed via the gate oxide film 3, and an oxide film 5 is formed thereon, followed by patterning. After that, a saddle oxide film 7 is formed on the side surface of the gate electrode 4, and a source / drain region 6 is formed by an ion implantation method (FIG. 28A). Next, after an interlayer insulating film 8 is formed on the entire surface, selective etching is performed to open a bit line contact hole 9 (FIG. 28B), and the source / drain region 6 is formed through the bit line contact hole 9. A bit line 10 connected to one is formed (FIG. 28)
(C)).

Next, after a second interlayer insulating film 11 is formed on the entire surface (FIG. 28 (d)), the second interlayer insulating film 11 and the interlayer insulating film 8 thereunder are selectively etched to store data. Open the node contact hole 12 (FIG. 28)
(E)), the storage node contact hole 12
, A storage node 13 connected to the other of the source / drain regions 6 is formed. Thereafter, a dielectric film 14 and an upper electrode 15 are formed thereon, and the storage node 1 is formed.
3. Form a capacitor comprising the dielectric film 14 and the upper electrode 15 (see FIG. 27)
Complete the memory cell.

In the above-described conventional semiconductor device, the contact holes 9 and 12 are formed so that each wiring is not short-circuited.
It is necessary to form the gate electrode 4 with a small opening diameter with high precision. With recent advances in miniaturization and high integration and further miniaturization, it is difficult with current lithography technology to form such fine contact holes in fine regions with high precision. Met.

As an existing method for solving the above problems, a method of manufacturing a DRAM memory cell by self-alignment will be described below with reference to FIG. First, similarly to FIG. 28A, a field insulating film 2 is formed on a substrate 1, a gate oxide film 3 (not shown), a gate electrode 4, an oxide film 5 on the surface of the gate electrode 4, and a sidewall oxide on the side surfaces. A film 7 and a source / drain region 6 are formed.
Thereafter, a nitride film 16 is formed on the entire surface, and an interlayer insulating film 8 made of an oxide film is formed on the entire surface thereof.
(A)). Next, the interlayer insulating film 8 is selectively etched to open the bit line contact holes 9a, and the nitride film 16 is formed.
Is partially exposed (FIG. 29B), and then the exposed nitride film 16 is removed by etching (FIG. 29C).

Next, the bit line 1 connected to one of the source / drain regions 6 via the bit line contact hole 9a
0a is formed. Thereafter, the second interlayer insulating film 11 is formed on the entire surface.
Is formed, and the second interlayer insulating film 11 and the lower interlayer insulating film 8 are selectively etched to open the storage node contact hole 12a to partially expose the nitride film 16 (FIG. 29D). Subsequently, the exposed nitride film 16 is removed by etching (FIG. 29E). Next, a storage node 13 connected to the other one of the source / drain regions 6 via the storage node contact hole 12a is formed, a dielectric film 14 and an upper electrode 15 are formed (see FIG. 27), and a predetermined process is performed. To complete a DRAM memory cell.

In this method, the contact holes 9a, 1
In the formation of 2a, the interlayer insulating films 9, 11 are etched using the nitride film 16 as a stopper, and then only the nitride film 16 at the bottom of the contact holes 9a, 12a is removed. Since the short circuit with the gate electrode 4 is prevented, the opening diameter can be increased, and the alignment margin in lithography can be secured. However, since the nitride film 16 has a small selectivity between the oxide film and the etching, the etching does not completely stop at the nitride film 16 as shown in FIG. Oxide films 5 and 7 covering nitride film 16 and further lower gate electrode 4 may be etched, which may cause deterioration of insulation and short-circuit between gate electrode 4 and bit line 10 or storage node 13. Was.

Next, an example of a manufacturing method using a polysilicon film having a large etching selectivity when etching the interlayer insulating films 9 and 11 will be described below with reference to FIG.
First, similarly to FIG. 28A, a field insulating film 2 is formed on a substrate 1, a gate oxide film 3 (not shown), a gate electrode 4, an oxide film 5 on the surface of the gate electrode 4, and a sidewall oxide on the side surfaces. A film 7 and a source / drain region 6 are formed. Thereafter, a polysilicon film is formed on the entire surface and is patterned to form a pad 17 made of the polysilicon film extending over the gate electrode 4 so as to cover the surface of the source / drain region 6. Thereafter, an interlayer insulating film 8 is formed on the entire surface (FIG. 3).
1 (a)).

Next, the interlayer insulating film 8 is selectively etched to open the bit line contact hole 9b and to form the pad 1
7 is partially exposed (FIG. 31B). Next, the bit line 10b is buried so as to fill the bit line contact hole 9b.
Is connected to one of the source / drain regions 6 via the pad 17. Thereafter, a second interlayer insulating film 11 is formed on the entire surface, the second interlayer insulating film 11 and the lower interlayer insulating film 8 are selectively etched, a storage node contact hole 12b is opened, and a pad 17 is formed. The part is exposed (FIG. 31 (c)). Next, the storage node 13 is embedded so as to fill the storage node contact hole 12b.
A connection is made to the other one of the source / drain regions 6 via the pad 17, a dielectric film 14 and an upper electrode 15 are formed (see FIG. 27), and predetermined processing is performed to complete a DRAM memory cell.

In this method, the polysilicon film used for the pad 17 has a large etching selectivity with respect to the interlayer insulating films 9 and 11 made of an oxide film. In addition, since the contact holes 9b and 12b may be formed on the pads 17, the opening diameter can be increased, and the alignment margin in lithography can be secured.

[0012]

However, in the method of manufacturing a semiconductor device using the pad 17 as described above, it is necessary to first form the pad 17 on each contact portion in a fine pattern with high precision. 17 were difficult to finely process. In addition, when forming the storage node contact 12b, it is only necessary to form the storage node contact 12b on the pad 17, and it is necessary to secure a margin so as not to short-circuit with the bit line 10b formed in the previous process. Was reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a contact that can be easily formed by sufficiently insulating each wiring layer from each other and ensuring a sufficient alignment margin in lithography. An object of the present invention is to provide a structure of a semiconductor device having a hole and a manufacturing method.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a gate electrode having an insulating film on a surface and a sidewall insulating film on a side surface; A first step of forming an impurity diffusion layer on both sides of the electrode; a second step of forming an interlayer insulating film on the conductive film after forming the conductive film; and sequentially etching the interlayer insulating film and the conductive film A third step of forming a contact hole exposing the surface of the impurity diffusion layer, and forming a sidewall insulating film on the inner wall of the contact hole to insulate the surface of the conductive film, and then forming the impurity through the contact hole. And a fourth step of forming an electrode layer connected to the diffusion layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a semiconductor substrate; an impurity diffusion layer on both sides of the gate electrode; and an insulating layer covering surfaces of the gate electrode and the impurity diffusion layer. A first step of forming a film, a second step of forming an interlayer insulating film on the conductive film after forming the conductive film, and sequentially etching the interlayer insulating film and the conductive film to form a contact hole A third step of forming an opening to expose the insulating film, forming a sidewall insulating film on the inner wall of the contact hole for insulating the conductive film surface, and etching the insulating film to remove the impurity diffusion layer surface; Forming the electrode layer connected to the impurity diffusion layer through the contact hole after the exposure.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, the conductive film formed in the second step is formed on the entire surface of the semiconductor substrate.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising a MOS capacitor and a MOS transistor, the method comprising the steps of: forming an insulating film on a surface of a semiconductor substrate; A first step of forming a gate electrode serving as a word line having an insulating film and impurity diffusion layers on both sides of the gate electrode; and a second step of forming an interlayer insulating film on the conductive film after forming the conductive film.
A third step of sequentially etching the interlayer insulating film and the conductive film to form a contact hole exposing the surface of the impurity diffusion layer; and a sidewall insulating the conductive film surface on the inner wall of the contact hole. Forming an insulating film, and then forming a bit line or a storage node connected to the impurity diffusion layer through the contact hole.

According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor memory device including a MOS capacitor and a MOS transistor, a gate electrode serving as a word line is provided on a semiconductor substrate. A first step of forming an impurity diffusion layer on both sides, an insulating film covering the surface of the gate electrode and the impurity diffusion layer, and a second step of forming an interlayer insulating film on the conductive film after forming the conductive film A step of sequentially etching the interlayer insulating film and the conductive film to form an opening serving as a contact hole to expose the insulating film, and a side insulating the conductive film surface on the inner wall of the contact hole. After forming a wall insulating film and etching the insulating film to expose the surface of the impurity diffusion layer, the insulating film is exposed through the contact hole. A fourth step of forming a bit line or a storage node connected to the pure things diffusion layer, and has a.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect, wherein
A memory cell region including a capacitor and a MOS transistor; and a peripheral circuit region. After an insulating film formed in the first step is formed on the entire surface of the semiconductor substrate, only in the peripheral circuit region. This is processed into a sidewall insulating film on the side surface of the gate electrode.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the fourth to sixth aspects, wherein the conductive film formed in the second step comprises a MOS capacitor and a MOS transistor. It is formed on the entire surface of the cell region.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the first to fourth steps are performed to form a bit line contact hole and to connect the bit line connected to the impurity diffusion layer. Then, a second interlayer insulating film is formed, and a third step is performed on the interlayer insulating film and the conductive film including the second interlayer insulating film to form a storage node contact hole. The fourth step is performed on the storage node contact hole to form a sidewall insulating film on the inner wall thereof and then form the storage node.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth aspect, when forming a storage node contact hole after forming the bit line, the edge of the bit line is exposed so as to be exposed. The second interlayer insulating film and the interlayer insulating film are etched, and then the exposed portions of the bit lines and the conductive film are etched.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, after the first and second steps are performed, a bit line contact hole is formed to diffuse the impurity. Form bit lines that connect to the layers,
Thereafter, after forming a second interlayer insulating film, a third step is performed to etch the interlayer insulating film including the second interlayer insulating film so that the end of the bit line is exposed. Forming a storage node contact hole by etching the exposed portion of the bit line and the conductive film and then performing a fourth step to form a sidewall insulating film on the inner wall of the storage node contact hole and then form a storage node It is.

In a semiconductor device according to an eleventh aspect of the present invention, a conductive film is formed on a semiconductor substrate having a gate electrode and an impurity diffusion layer formed on both sides of the gate electrode. An insulating film, a contact hole, and an electrode layer connected to the impurity diffusion layer through the contact hole, wherein the contact hole is provided in the conductive film and the interlayer insulating film so that their openings are aligned with each other. In addition, a sidewall insulating film for insulating the conductive film surface is formed on the inner wall thereof.

According to a twelfth aspect of the present invention, in the eleventh aspect, the electrode layer is a bit line or a storage node of a semiconductor memory device including a MOS capacitor and a MOS transistor.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a memory cell of a DRAM according to the first embodiment of the present invention. In the drawing, reference numeral 1 denotes a semiconductor substrate made of silicon single crystal or the like (hereinafter, referred to as a substrate 1), 2 denotes a field insulating film for isolating elements, 4 denotes a gate insulating film formed on the substrate 1, Gate electrode to be a line, here gate oxide film 3
Is a thin film and is not shown for convenience. 5 is an oxide film as an insulating film formed on the surface of the gate electrode 4, 6 is a source / drain region as an impurity diffusion layer formed on both sides of the gate electrode 4, and 7 is a side wall formed on the side surface of the gate electrode 4. It is a sidewall oxide film as an insulating film.

Reference numeral 18 denotes a polysilicon film serving as a conductive film, 19 denotes an interlayer insulating film formed on the polysilicon film 18, and 20 denotes an interlayer insulating film 19 and the polysilicon film 18.
A bit line contact hole provided with the openings aligned, 21 is a sidewall oxide film as a sidewall insulating film formed on the inner wall of the bit line contact hole 20, and 22 is via the bit line contact hole 20. The bit line is connected to one of the source / drain regions 6. Reference numeral 23 denotes a second interlayer insulating film formed on the interlayer insulating film 19 so as to cover the bit line 22, and reference numeral 24 denotes a second interlayer insulating film, the interlayer insulating film 19, and the polysilicon film 1.
Reference numeral 8 denotes a storage node contact hole provided with the opening part aligned, 25 denotes a sidewall oxide film as a sidewall insulating film formed on the inner wall of the storage node contact hole 24, and 26 denotes a storage node contact hole via the storage node contact hole. A storage node serving as a lower electrode of the capacitor connected to the other one of the source / drain regions 6, a dielectric film 27 of the capacitor, and an upper electrode 28 of the capacitor.

As shown in the figure, a polysilicon film 18 is formed below the interlayer insulating film 19, and a bit line contact hole 20 is formed in the interlayer insulating film 19 and the polysilicon film 18 so that their openings are aligned. A polysilicon film 18 is formed on the inner wall of the bit line contact hole 20.
A sidewall oxide film 21 for insulating the surface is formed, and a bit line 22 connected to the source / drain region 6 is buried. Similarly, the storage node contact hole 24 is formed in the interlayer insulating films 19 and 23 including the second interlayer insulating film 23 and the polysilicon film 18 thereunder so that the openings thereof are aligned. A sidewall oxide film 25 for insulating the surface of the polysilicon film 18 is formed on the inner wall of the storage node contact hole 24, and the storage node 26 connected to the source / drain region 6 is buried.

Next, the manufacturing method will be described below with reference to FIGS. In general, a DRAM has a built-in memory cell portion including a transistor and a capacitor and a peripheral circuit portion, but illustration of the peripheral circuit portion is omitted here. First, after a field insulating film 2 is formed on a substrate 1, a polysilicon film serving as a gate electrode 4 is formed via a gate oxide film 3, and an oxide film 5 is formed thereon.
Patterning is performed so that an interval dimension is about 0.45 μm to 0.5 μm. Thereafter, a sidewall oxide film 7 is formed on the side surface of the gate electrode 4, and a source / drain region 6 is formed by an ion implantation method (FIG. 2). Next, a polysilicon film 18 is formed on the entire surface of the memory
A film having a thickness of 0.1 μm is formed, and an interlayer insulating film 19 is formed over the entire surface (FIG. 3).

Next, an opening is formed by selectively removing the interlayer insulating film 19 by etching, and then the exposed polysilicon film 18 is exposed.
Is removed by etching to open a bit line contact hole 20. At this time, when etching the interlayer insulating film 19, the polysilicon film 18 having a high etching selectivity serves as a stopper, and the polysilicon film 18
Since only the etching is performed, only the bit line contact hole 20 can be formed without causing a problem such as a short circuit with the gate electrode 4 due to overetching and an insulation failure.
The opening diameter of the bit line contact hole 20 on the substrate 1 is about 0.26 μm to 0.35 μm (FIG. 4).
Next, after depositing an oxide film on the entire surface, a sidewall oxide film 21 is formed on the inner wall of the bit line contact hole 20 to have a width of about 0.05 μm to 0.1 μm by anisotropic etching (FIG. 5).

Next, the bit line 22 is buried in the bit line contact hole 20 to have a thickness of about 0.07 μm to 0.15 μm.
After being formed to a thickness of m and being connected to the source / drain region 6, a second interlayer insulating film 23 is formed on the entire surface (FIG. 6).
Next, the second interlayer insulating film 23 and the interlayer insulating film 19 are selectively etched to form openings, and then the exposed polysilicon film 18 is etched to form storage node contact holes 24 on the substrate 1. Opening diameter 0.26μ
Open at m to 0.35 μm. Next, after an oxide film is deposited on the entire surface, a sidewall oxide film 25 is formed on the inner wall of the storage node contact hole 24 by anisotropic etching to a thickness of about 0.1.
It is formed to have a width of 05 μm to 0.1 μm. Also in the case of forming the storage node contact hole 24, as in the case of the bit line contact hole 20, problems such as a short circuit with the gate electrode 4 due to overetching and insulation failure can be avoided (FIG. 7).

Next, the storage node 26 is buried in the storage node contact hole 24 to form a connection with the source / drain region 6, and thereafter, a dielectric film 26 and an upper electrode 28 are formed (see FIG. 1). To complete the semiconductor device.

In this embodiment, the contact hole 2
Since the polysilicon film 18 is used as an etching stopper when forming the layers 0 and 24, the interlayer insulating films 19 and 2 are used.
It is not necessary to form the opening 3 between the fine gate electrodes 4, so that the opening diameters of the contact holes 20, 24 can be increased, and the alignment margin in lithography is sufficiently secured to be about 0.15 μm. Can be performed, and problems due to overetch can be prevented. In addition, the polysilicon film 18 can be easily formed on the entire surface of the memory cell portion, and when an ion implantation process is performed on the entire surface in a later step, the polysilicon film 18 remains on almost the entire surface of the memory cell portion. There is also an effect of reducing the influence on the field insulating film 2 and the like. Further, the polysilicon film 18 which is a conductive film is used as an etching stopper at the time of forming the contact holes 20 and 24.
Sidewall oxide films 21 and 25 are formed on inner walls 0 and 24 to insulate the surface of the polysilicon film 18. Therefore, the gate electrode 4, the bit line 22, and the storage node 26
The contact holes 20, 24 in which the respective wiring layers are well insulated from each other and a sufficient alignment margin in lithography can be easily formed with high reliability.

Although the polysilicon film 18 is used as the conductive film, the present invention is not limited to this. Any film may be used as long as it has a sufficient etching selectivity with respect to the oxide film. In addition, when the nitride film used in the conventional example is used other than the conductive film, for example, the etching selectivity is not sufficient, so that the contact holes 20 and 24 are slightly over-etched when the contact holes 20 and 24 are formed. By forming, problems such as insulation failure and short circuit can be improved.

Embodiment 2 Next, a second embodiment of the present invention will be described. FIG. 8 is a sectional view showing a structure of a memory cell of the DRAM according to the second embodiment of the present invention. FIG. 9 is a plan view showing a general structure of a memory cell. FIGS. 1 to 7 used in the first embodiment are A to A.
FIG. 4 is a cross-sectional view taken along a line.
The description will be made with reference to a cross-sectional view taken along a line. In this embodiment, illustration and description of the storage node 26, the dielectric film 27, and the upper electrode 28 are omitted. 8 and 9
1, 2, 4, 6, 18 to 20 and 22 to 2
Reference numeral 4 denotes the same as in the first embodiment, reference numeral 29 denotes a storage node contact hole, and reference numeral 30 denotes a sidewall oxide film as a sidewall insulating film formed on the inner wall of the storage node contact hole 29.

Next, the manufacturing method will be described below with reference to FIG. As in the first embodiment, the steps shown in FIGS. 2 to 6 are performed to form the bit lines 22 and thereafter up to the second interlayer insulating film 23. Here, FIG. 6 and FIG. 10A are cross-sectional views showing the same process. At this time, the bit lines 22 are formed at intervals of the dimension a (0.26 μm to 0.35 μm) (FIG. 10A). Next, the second interlayer insulating film 23 and the interlayer insulating film 19 are selectively etched to be opened by using the underlying polysilicon film 18 as an etching stopper to form openings, thereby forming storage node contact holes 29. At this time, the opening is formed so that the bit line 22 is exposed (FIG. 10B). Next, the exposed portion of the bit line 22 and the polysilicon film 18 at the bottom of the storage node contact hole 29 are removed (FIG. 10C), and then a sidewall is formed on the inner wall of the storage node contact hole 29 as in the first embodiment. An oxide film 30 is formed.
As a result, the interlayer insulating films 19 and 23 and the polysilicon film
A storage node contact hole 29 is formed in such a manner that the openings of the storage node contact hole 29 are aligned with each other. (See FIG. 8).

Also in the conventional example or the first embodiment, usually, when forming the storage node contact hole 24, a margin for alignment with the bit line 22 in lithography is required so as not to short-circuit with the bit line 22. However, in this embodiment, when forming the storage node contact hole 29, the bit line 22 is exposed and etched, so that a margin for alignment with the bit line 22 is not required. Therefore, the same effect as that of the first embodiment can be obtained, and alignment in lithography at the time of forming storage node contact hole 29 can be further facilitated. Further, since the exposed portion of the bit line 22 and the polysilicon film 18 at the bottom of the storage node contact hole 29 can be removed at the same time, the process is simple. In the case where anisotropic etching is used at the time of this etching, the polysilicon film 18 is formed so as to have a thickness equal to or greater than the thickness of the bit line 22.

In this case, since the storage node contact hole 29 is formed by etching the bit line 22, the width of the bit line 22 can be increased in advance, and even if the diameter of the bit line contact hole 20 is increased,
The bit line 22 can reliably fill the bit line contact hole 20, and the process reliability is improved.
Furthermore, not only in the case where the bit line 22 is intentionally exposed, but also in the course of manufacturing by the manufacturing method of the first embodiment, the bit line 22 is shifted due to misalignment in lithography when the storage node contact hole 24 (29) is opened. Can be applied even if is exposed. Further, as shown in the figure, the opening diameter of the storage node contact hole 29 on the substrate 1 can be determined by the interval a between the bit lines 22.

Embodiment 3 Next, a third embodiment of the present invention will be described. FIG. 11 is a cross-sectional view showing a structure of a memory cell of a DRAM according to the third embodiment of the present invention, and shows a cross-sectional structure taken along line A-A in the plan view of FIG. In the figure, 1, 2, 4 to 6 and 19 to 25 are the same as those in the first embodiment, and 31 is an insulating film formed so as to cover the gate electrode 4 and extend on the surface of the source / drain region 6. An oxide film 32 is a polysilicon film as a conductive film formed on the oxide film 31.

Next, the manufacturing method will be described below with reference to FIGS. As in the first embodiment, the substrate 1
After forming a field insulating film 2 thereon, a gate oxide film 3 is formed.
A polysilicon film to be the gate electrode 4 is formed via a not-shown (not shown), and an oxide film 5 is formed thereon, followed by patterning. Thereafter, after an oxide film 31 is formed on the entire surface, the DRAM
In the peripheral circuit portion (not shown) of FIG. 1, the oxide film 31 is processed into a sidewall oxide film on the side surface of the gate electrode 4 by anisotropic etching, and in the memory cell portion, the oxide film 31 is formed.
Are left in the state at the time of formation, and the source / drain region 6 is formed (FIG. 12). Next, a polysilicon film 32 is formed to a thickness of about 0.05 μm to 0.1 μm on the entire surface in the memory cell portion, and an interlayer insulating film 19 is formed on the entire surface thereof (FIG. 13).

Next, the interlayer insulating film 19 is selectively removed by etching using the underlying polysilicon film 32 as an etching stopper to open a bit line contact hole 20 (FIG. 14). The oxide film 31 is exposed at the bottom of the bit line contact hole 20 by removal by anisotropic etching (FIG. 15). Next, after depositing an oxide film on the entire surface, a sidewall oxide film 21 is formed to a width of about 0.05 μm to 0.1 μm on the inner wall of the bit line contact hole 20 by anisotropic etching. The oxide film 31 is also removed (FIG. 16). Next, as in the first embodiment, after forming the bit line 22, a second interlayer insulating film 23 is formed (FIG. 17), and then the bit line contact hole 24 is formed.
Similarly, the interlayer insulating films 19 and 23 and the polysilicon film 32 are selectively and sequentially etched to form the storage node contact holes 29 (FIGS. 18 and 19). The oxide film 31 at the bottom of the node contact hole 29 is removed. As a result, contact holes 20 and 24 are formed in the interlayer insulating film 19 (23) and the polysilicon film 18 thereunder so that the openings are aligned with each other.
1 has a structure in which sidewall oxide films 21 and 25 for insulating the surface of the polysilicon film 18 are formed on the inner wall 24.
1).

In this embodiment, the same effects as those of the first embodiment are obtained, and since the sidewall oxide film 7 on the side surface of the gate electrode 4 is not formed in the memory cell portion, etching damage to the substrate 1 can be reduced. . The oxide film 31 on the surface of the substrate 1 is
The process can be simplified since it can be removed simultaneously by anisotropic etching for forming the sidewall oxide films 21 and 25 on the inner walls 0 and 24.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. FIG. 20 is a cross-sectional view showing the structure of the memory cell of the DRAM according to the fourth embodiment of the present invention, and shows a cross-sectional structure taken along line A-A in the plan view of FIG. In the figure, 1, 2, 4 to 6, 19,
22, 23 and 26 to 31 are the same as those in the first to third embodiments, 33 is a polysilicon film as a conductive film formed on the oxide film 31, 34 is a bit line contact hole, 35 is a bit line contact hole 34 is a side wall oxide film formed on the inner wall.

Next, the manufacturing method will be described below with reference to FIGS. FIG. 21, FIG. 22, FIG. 23 (a), FIG. 24 (a), FIG. 25 (a) and FIG. 26 (a) show cross-sectional structures along the line A-A in the plan view of FIG.
(B), FIG. 24 (b), FIG. 25 (b) and FIG.
(B) shows a cross-sectional structure taken along line B-B. First, similarly to the third embodiment, the field insulating film 2 is formed on the substrate 1.
After forming the gate electrode 4, the oxide film 5, the source / drain region 6, and the oxide film 31, a polysilicon film 33 is formed on the entire surface, and covers the source / drain region 6 for connecting the storage node 26 in a later step. Then, patterning is performed so as to extend over the substrate 4 (FIG. 21).

Next, the interlayer insulating film 19 and the oxide film 31 are selectively etched to form bit line contact holes 34.
After forming a sidewall oxide film 35 on the inner wall of the bit line contact hole 34, the bit line 22 is connected to one of the source / drain regions 6 via the bit line contact hole 34 (FIG. 22). Next, an interlayer insulating film 23 is formed on the entire surface. Here, it is assumed that the bit lines 22 formed in the previous step are arranged at intervals of the dimension b (FIG. 2).
3). Next, as in the second embodiment, the bit line 22
After opening the interlayer insulating films 19 and 23 so as to expose the storage node contact holes 29 having the opening diameter b on the substrate 1 (FIG. 24), the exposed portions of the bit lines 22 and the storage node contacts are formed. The polysilicon film 33 at the bottom of the hole 29 is removed by anisotropic etching, and the oxide film 31 is formed at the bottom of the storage node contact hole 29.
Is exposed (FIG. 25).

Next, as in the third embodiment, a sidewall oxide film 21 is formed on the inner wall of the storage node contact hole 29, and at the same time, the oxide film 31 at the bottom of the storage node contact hole 29 is removed (FIG. 26).

In this embodiment, the side wall oxide film 35 is formed on the inner wall of the bit line contact hole 34. However, the side wall oxide film 35 may not be provided. A contact hole 34 may be formed.

In this embodiment, the second and third embodiments are applied to the formation of the storage node contact hole 29. Etching damage to the substrate 1 can be reduced, and the bit line 20 can be formed by a simple process.
In addition, the gate electrode 4 and the storage node 26 are satisfactorily insulated from each other, and a sufficient alignment margin in lithography can be ensured. In particular, the alignment can be easily performed without considering the alignment margin with the bit line 22, and the reliability is improved. . In addition, since the polysilicon film 33 is formed so as to be patterned so as to extend over the gate electrode 4 so as to cover the source / drain region 6 connecting the storage node 26, the present invention is applied only to the storage node contact hole 29. The processing of the polysilicon film 33 is not particularly fine and can be easily formed. A polysilicon film 33 is formed on the entire surface of the memory cell portion, and a bit line contact hole 34 is also formed according to the present invention (in this case, the second and third embodiments are used together).
Obviously, can be applied.

In the third and fourth embodiments, the oxide film 31 is a film processed into the sidewall oxide film 7 on the side surface of the gate electrode 4 in the peripheral circuit portion.
The film is not limited to this, and may be a film formed separately.

In the first to fourth embodiments, the bit line contact hole 20 and the storage node contact holes 24 and 29 in the memory cell section of the DRAM have been described. It can be applied to a contact hole for connection, and has the same effect.

[0051]

As described above, according to the present invention, a conductive film is formed under the interlayer insulating film, and the interlayer insulating film and the conductive film thereunder are sequentially etched to form a contact hole. Since the sidewall insulating film is formed, the insulating property between the electrode layer formed in the contact hole and other wiring layers is good, a sufficient alignment margin in lithography can be secured, and the contact hole can be easily and reliably formed. A method for manufacturing a semiconductor device suitable for high integration that can be formed can be provided.

According to the invention, an insulating film is formed,
After forming a conductive film and an interlayer insulating film thereon, the interlayer insulating film and the conductive film thereunder are sequentially etched to form a contact hole, and then a sidewall insulating film is formed on the inner wall of the contact hole, and the contact hole bottom is formed. In order to remove the insulating film, the insulation between the electrode layer formed in the contact hole and other wiring layers is good,
It is possible to provide a method of manufacturing a semiconductor device suitable for high integration in which a sufficient alignment margin in lithography can be secured, a contact hole can be easily formed with high reliability, and damage to a semiconductor substrate can be reduced.

Further, according to the present invention, since the conductive film below the interlayer insulating film is formed on the entire surface of the semiconductor substrate, the conductive film can be easily formed, and the above-mentioned effects can be obtained easily and reliably.

According to the present invention, in the manufacture of a semiconductor memory device, a conductive film is formed below an interlayer insulating film, and the interlayer insulating film and the conductive film thereunder are sequentially etched to connect a bit line or a storage node. After forming the contact hole, a sidewall insulating film is formed on the inner wall of the contact hole, so that the insulating property between the bit line or storage node formed in the contact hole and another wiring layer such as a gate electrode is good, and the A method for manufacturing a semiconductor device suitable for high integration, in which a sufficient alignment margin can be secured and a contact hole can be easily and reliably formed, can be provided.

According to the invention, in the manufacture of a semiconductor memory device, an insulating film is formed, a conductive film and an interlayer insulating film are formed thereon, and then the interlayer insulating film and the conductive film thereunder are sequentially etched. A contact hole for connecting a bit line or a storage node is formed, and then a sidewall insulating film is formed on the inner wall of the contact hole, and a bit line or a contact hole formed in the contact hole is formed to remove the insulating film at the bottom of the contact hole. Good insulation between the storage node and other wiring layers such as gate electrodes, sufficient alignment margin in lithography can be secured, contact holes can be easily and reliably formed, and damage to the semiconductor substrate can be reduced. A method for manufacturing a semiconductor device suitable for high integration can be provided.

According to the present invention, since the insulating film formed under the conductive film is processed into the sidewall insulating film on the side surface of the gate electrode in the peripheral circuit region, the above-described effects can be easily obtained.

According to the present invention, since the conductive film below the interlayer insulating film is formed on the entire surface of the semiconductor substrate, the conductive film can be easily formed, and the above-described effects can be easily and reliably obtained.

According to the present invention, since the conductive film is formed on the entire surface to form the bit line contact hole and the storage node contact hole, the bit line, the storage node and the gate electrode can be well insulated from each other. It is possible to provide a method of manufacturing a semiconductor device suitable for high integration, in which bit line contact holes and storage node contact holes can be formed easily and with high reliability.

According to the present invention, a conductive film is formed on the entire surface to form a bit line contact hole and a bit line.
Since the interlayer insulating film is etched so that the bit line is exposed when the storage node contact hole is formed, and then the exposed portion of the bit line and the conductive film below the interlayer insulating film are etched, alignment in lithography when forming the storage node contact hole is performed. Is further facilitated, and a more reliable semiconductor device can be manufactured.

According to the present invention, after forming the bit line contact hole and the bit line, the interlayer insulating film is etched so that the bit line is exposed when the storage node contact hole is formed, and then the exposed portion of the bit line and the interlayer insulating film are formed. Since the lower conductive film is etched, alignment in lithography when forming a storage node contact hole is further facilitated, and a more reliable semiconductor device can be manufactured.

Further, according to the present invention, a conductive film is formed below the interlayer insulating film, a contact hole is formed in such a manner that the conductive film and the interlayer insulating film have openings coincident with each other, and a sidewall insulating film is formed on the inner wall of the contact hole. Because a film was formed,
A semiconductor device suitable for high integration, in which the insulating property between the electrode layer in the contact hole and another wiring layer is good and the contact hole can be easily and reliably formed.

According to the present invention, since the contact hole is provided for the bit line or the storage node in the semiconductor memory device, the insulation between the bit line or the storage node and another wiring layer such as a gate electrode is good, and A semiconductor device suitable for high integration in which a line contact hole or a storage node contact hole can be easily and reliably formed is obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a memory cell of a DRAM according to a first embodiment of the present invention;

FIG. 2 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention;

FIG. 4 is a cross sectional view showing a step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention;

FIG. 6 is a sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention;

FIG. 7 is a sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the first embodiment of the present invention;

FIG. 8 is a sectional view showing a structure of a memory cell of a DRAM according to a second embodiment of the present invention;

FIG. 9 is a plan view showing a structure of a memory cell of the DRAM.

FIG. 10 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 11 is a sectional view showing a structure of a memory cell of a DRAM according to a third embodiment of the present invention;

FIG. 12 is a sectional view showing one step in a method of manufacturing a memory cell of a DRAM according to a third embodiment of the present invention;

FIG. 13 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step in a method for manufacturing a memory cell of a DRAM according to the third embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 16 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 17 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 19 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the third embodiment of the present invention.

FIG. 20 is a sectional view showing a structure of a memory cell of a DRAM according to a fourth embodiment of the present invention;

FIG. 21 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the fourth embodiment of the present invention.

FIG. 22 is a cross sectional view showing a step in a method for manufacturing a memory cell of a DRAM according to the fourth embodiment of the present invention.

FIG. 23 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the fourth embodiment of the present invention.

FIG. 24 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the fourth embodiment of the present invention.

FIG. 25 is a cross sectional view showing one step in a method for manufacturing a memory cell of the DRAM according to the fourth embodiment of the present invention.

FIG. 26 is a cross sectional view showing a step in a method for manufacturing a memory cell of the DRAM according to the fourth embodiment of the present invention.

FIG. 27 is a sectional view showing a structure of a memory cell of a conventional DRAM.

FIG. 28 is a cross-sectional view showing a method for manufacturing a memory cell of a conventional DRAM.

FIG. 29 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another conventional example.

FIG. 30 is a cross-sectional view illustrating a conventional problem.

FIG. 31 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another conventional example.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 4 gate electrode, 5 oxide film as insulating film, 6 source / drain region as impurity diffusion layer, 7 sidewall oxide film as sidewall insulating film, 18 polysilicon film as conductive film, 19
Interlayer insulating film, 20 bit line contact holes, 21
A sidewall oxide film as a sidewall insulating film,
22 bit line, 23 second interlayer insulating film, 24 storage node contact hole, 25 sidewall oxide film as sidewall insulating film, 26 storage node, 29 storage node contact hole,
30 Side wall oxide film as side wall insulating film, 31 oxide film as insulating film, 32, 33 polysilicon film as conductive film, 34 bit line contact hole.

Claims (12)

[Claims] A first step of forming, on a semiconductor substrate, a gate electrode having an insulating film on the surface and a sidewall insulating film on the side, and an impurity diffusion layer on both sides of the gate electrode; A second step of forming an interlayer insulating film on the conductive film after the formation, and a third step of sequentially etching the interlayer insulating film and the conductive film to form a contact hole exposing the surface of the impurity diffusion layer. And forming a sidewall insulating film on the inner wall of the contact hole to insulate the surface of the conductive film, and then forming an electrode layer connected to the impurity diffusion layer through the contact hole. A method for manufacturing a semiconductor device, comprising: A first step of forming a gate electrode, an impurity diffusion layer on both sides of the gate electrode, and an insulating film covering the surface of the gate electrode and the impurity diffusion layer on a semiconductor substrate; A second step of forming an interlayer insulating film on the conductive film after the formation, and a third step of sequentially etching the interlayer insulating film and the conductive film to form an opening serving as a contact hole and exposing the insulating film. Forming a sidewall insulating film on the inner wall of the contact hole to insulate the surface of the conductive film and etching the insulating film to expose the surface of the impurity diffusion layer, and then forming the impurity through the contact hole. A fourth step of forming an electrode layer connected to the diffusion layer. 3. The method according to claim 1, wherein the conductive film formed in the second step is formed on the entire surface of the semiconductor substrate. 4. A method for manufacturing a semiconductor memory device comprising a MOS capacitor and a MOS transistor, comprising: a gate electrode serving as a word line having an insulating film on a surface and a sidewall insulating film on a side surface on a semiconductor substrate; A first step of forming an impurity diffusion layer on both sides of the gate electrode, a second step of forming a conductive film and then forming an interlayer insulating film on the conductive film, and sequentially forming the interlayer insulating film and the conductive film A third step of etching to form a contact hole exposing the surface of the impurity diffusion layer, and forming a sidewall insulating film on the inner wall of the contact hole to insulate the surface of the conductive film; A fourth step of forming a bit line or a storage node connected to the impurity diffusion layer. Method. 5. A method for manufacturing a semiconductor memory device comprising a MOS capacitor and a MOS transistor, comprising: a gate electrode serving as a word line on a semiconductor substrate; an impurity diffusion layer on both sides of the gate electrode; A first step of forming an insulating film covering the surface of the diffusion layer, a second step of forming an interlayer insulating film on the conductive film after forming the conductive film, and sequentially forming the interlayer insulating film and the conductive film. A third step of exposing the insulating film by forming an opening serving as a contact hole by etching, and forming a sidewall insulating film on the inner wall of the contact hole for insulating the conductive film surface and etching the insulating film. After exposing the surface of the impurity diffusion layer, the bit line or storage connected to the impurity diffusion layer via the contact hole is formed. A fourth step of forming a node;
A method for manufacturing a semiconductor device, comprising: 6. A semiconductor memory device comprising: a MOS capacitor;
An insulating film having a memory cell region constituted by an OS transistor and a peripheral circuit region, and an insulating film formed in the first step;
6. The method of manufacturing a semiconductor device according to claim 5, wherein after being formed on the entire surface of the semiconductor substrate, the side wall insulating film on the side surface of the gate electrode is processed only in the peripheral circuit region. 7. A conductive film formed in the second step is formed by a MOS
5. The semiconductor device according to claim 4, wherein said capacitor is formed on the entire surface of a memory cell region including a capacitor and a MOS transistor.
7. The method for manufacturing a semiconductor device according to any one of items 1 to 6. 8. A bit line contact hole is formed by performing first to fourth steps to form a bit line connected to the impurity diffusion layer, and thereafter, a second interlayer insulating film is formed. After performing a third step on the interlayer insulating film including the interlayer insulating film and the conductive film to form a storage node contact hole, a fourth step is performed on the storage node contact hole to form an inner wall on the inner wall. 8. The method according to claim 7, wherein the storage node is formed after forming the sidewall insulating film. 9. When forming a storage node contact hole after forming a bit line, a second interlayer insulating film and an interlayer insulating film are etched so that an end of the bit line is exposed, and then the bit line is formed. 9. The method according to claim 8, wherein the exposed portion and the conductive film are etched. 10. After performing the first and second steps, a bit line contact hole is formed to form a bit line connected to the impurity diffusion layer, and then, a second interlayer insulating film is formed. Performing a third step to etch the interlayer insulating film including the second interlayer insulating film so that the end of the bit line is exposed, and then etch the exposed portion of the bit line and the conductive film to store the bit line; 7. The method according to claim 4, wherein a fourth step is performed after forming the node contact hole to form a sidewall insulating film on the inner wall of the storage node contact hole and then form the storage node. The manufacturing method of the semiconductor device described in the above. 11. A conductive film, an interlayer insulating film on the conductive film, a contact hole, and a contact hole formed on a semiconductor substrate having a gate electrode and an element diffusion layer formed on both sides of the gate electrode. An electrode layer connected to the impurity diffusion layer via a hole, the contact hole is provided in the conductive film and the interlayer insulating film so that the opening is aligned, and the conductive film surface is formed on an inner wall thereof. A semiconductor device having a sidewall insulating film formed thereon for insulation. 12. An electrode layer comprising a MOS capacitor and a MOS capacitor.
2. A bit line or a storage node of a semiconductor memory device comprising a transistor.
2. The semiconductor device according to 1.